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Merge pull request #16005 from benpicco/cpu/nrf52_gpio_count

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cpu/nrf5x_common: make GPIO_PIN macro model independent
This commit is contained in:
Alexandre Abadie 2021-02-16 16:18:29 +01:00 committed by GitHub
commit bcb23da368
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 8 additions and 3 deletions
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5
cpu/nrf51/include/cpu_conf.h
View File

@ -57,6 +57,11 @@ extern "C" {
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
/** @} */
/**
* @brief nRF51 only has one GPIO block
*/
#define GPIO_COUNT (1U)
/**
* @brief Due to RAM restrictions, we need to limit the default GNRC packet
* buffer size on these CPUs

2
cpu/nrf5x_common/include/periph_cpu_common.h
View File

@ -46,7 +46,7 @@ extern "C" {
*
* The port definition is used (and zeroed) to suppress compiler warnings
*/
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
#if GPIO_COUNT > 1
#define GPIO_PIN(x,y) ((x << 5) | y)
#else
#define GPIO_PIN(x,y) ((x & 0) | y)

4
cpu/nrf5x_common/periph/gpio.c
View File

@ -86,7 +86,7 @@ static inline NRF_GPIO_Type *port(gpio_t pin)
*/
static inline int pin_num(gpio_t pin)
{
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
#if GPIO_COUNT > 1
return (pin & PIN_MASK);
#else
return (int)pin;
@ -184,7 +184,7 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
/* configure the GPIOTE channel: set even mode, pin and active flank */
NRF_GPIOTE->CONFIG[_pin_index] = (GPIOTE_CONFIG_MODE_Event |
(pin_num(pin) << GPIOTE_CONFIG_PSEL_Pos) |
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
#if GPIO_COUNT > 1
((pin & PORT_BIT) << 8) |
#endif
(flank << GPIOTE_CONFIG_POLARITY_Pos));