From 044acf1175900dd8a4d3be7ff48d4d25997ee345 Mon Sep 17 00:00:00 2001
From: Alexandre Abadie <alexandre.abadie@inria.fr>
Date: Tue, 13 Oct 2020 22:03:25 +0200
Subject: [PATCH] cpu/stm32: enable power overdrive on f4 and f7

This is only enabled if the HCLK clock is above 168MHz on F4 and 180MHz on f7
---
 cpu/stm32/stmclk/stmclk_f2f4f7.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/cpu/stm32/stmclk/stmclk_f2f4f7.c b/cpu/stm32/stmclk/stmclk_f2f4f7.c
index 3388a07875..af2912a49a 100644
--- a/cpu/stm32/stmclk/stmclk_f2f4f7.c
+++ b/cpu/stm32/stmclk/stmclk_f2f4f7.c
@@ -479,6 +479,25 @@ void stmclk_init_sysclk(void)
     /* Flash config */
     FLASH->ACR = FLASH_ACR_CONFIG;
 
+    /* Enable Over-Drive if HCLK > 168MHz on F4 or HCLK > 180MHz on F7 */
+#if defined(CPU_FAM_STM32F4) && defined(PWR_CR_ODEN)
+    if (CLOCK_AHB > MHZ(168)) {
+        PWR->CR |= PWR_CR_ODEN;
+        while (!(PWR->CSR & PWR_CSR_ODRDY)) {}
+        PWR->CR |= PWR_CR_ODSWEN;
+        while (!(PWR->CSR & PWR_CSR_ODSWRDY)) {}
+    }
+#endif
+
+#if defined(CPU_FAM_STM32F7)
+    if (CLOCK_AHB > MHZ(180)) {
+        PWR->CR1 |= PWR_CR1_ODEN;
+        while (!(PWR->CSR1 & PWR_CSR1_ODRDY)) {}
+        PWR->CR1 |= PWR_CR1_ODSWEN;
+        while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY)) {}
+    }
+#endif
+
     /* disable all active clocks except HSI -> resets the clk configuration */
     RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);