diff --git a/cpu/stm32_common/cpu_common.c b/cpu/stm32_common/cpu_common.c
index c453cedd73..945b1d09ff 100644
--- a/cpu/stm32_common/cpu_common.c
+++ b/cpu/stm32_common/cpu_common.c
@@ -91,13 +91,13 @@ void periph_clk_en(bus_t bus, uint32_t mask)
         case IOP:
             RCC->IOPENR |= mask;
             break;
-#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
-      || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
+#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) || \
+      defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
         case AHB:
             RCC->AHBENR |= mask;
             break;
-#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
-      || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
+#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+      defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
         case AHB1:
             RCC->AHB1ENR |= mask;
             break;
@@ -144,13 +144,13 @@ void periph_clk_dis(bus_t bus, uint32_t mask)
         case IOP:
             RCC->IOPENR &= ~(mask);
             break;
-#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) \
-      || defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
+#elif defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32F1) || \
+      defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3)
         case AHB:
             RCC->AHBENR &= ~(mask);
             break;
-#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) \
-      || defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
+#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+      defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32F7)
         case AHB1:
             RCC->AHB1ENR &= ~(mask);
             break;
diff --git a/cpu/stm32_common/include/periph_cpu_common.h b/cpu/stm32_common/include/periph_cpu_common.h
index 2a2123d3ab..e7ff4fffd0 100644
--- a/cpu/stm32_common/include/periph_cpu_common.h
+++ b/cpu/stm32_common/include/periph_cpu_common.h
@@ -34,10 +34,10 @@ extern "C" {
     defined(CPU_FAM_STM32F3)
 #define CLOCK_LSI           (40000U)
 #elif defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
-    defined(CPU_FAM_STM32L1)
+      defined(CPU_FAM_STM32L1)
 #define CLOCK_LSI           (37000U)
 #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32L4)
+      defined(CPU_FAM_STM32L4)
 #define CLOCK_LSI           (32000U)
 #else
 #error "error: LSI clock speed not defined for your target CPU"
diff --git a/cpu/stm32_common/periph/uart.c b/cpu/stm32_common/periph/uart.c
index 1e91ff582e..28cc9ddfb6 100644
--- a/cpu/stm32_common/periph/uart.c
+++ b/cpu/stm32_common/periph/uart.c
@@ -34,9 +34,9 @@
 #include "periph/gpio.h"
 #include "pm_layered.h"
 
-#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
-    || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
-    || defined(CPU_FAM_STM32F7)
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
+    defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
+    defined(CPU_FAM_STM32F7)
 #define ISR_REG     ISR
 #define ISR_TXE     USART_ISR_TXE
 #define ISR_TC      USART_ISR_TC
@@ -368,9 +368,9 @@ void uart_poweroff(uart_t uart)
 
 static inline void irq_handler(uart_t uart)
 {
-#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) \
-    || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
-    || defined(CPU_FAM_STM32F7)
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
+    defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) || \
+    defined(CPU_FAM_STM32F7)
 
     uint32_t status = dev(uart)->ISR;
 
diff --git a/cpu/stm32_common/stmclk.c b/cpu/stm32_common/stmclk.c
index 577c24058e..ad8755c71d 100644
--- a/cpu/stm32_common/stmclk.c
+++ b/cpu/stm32_common/stmclk.c
@@ -19,8 +19,9 @@
  * @}
  */
 
-#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) \
-    || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+    defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || \
+    defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
 
 #include "cpu.h"
 #include "stmclk.h"
@@ -41,7 +42,8 @@
  * @name    PLL configuration
  * @{
  */
-#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
+#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+    defined(CPU_FAM_STM32F7)
 /* figure out which input to use */
 #if (CLOCK_HSE)
 #define PLL_SRC                  RCC_PLLCFGR_PLLSRC_HSE
@@ -147,7 +149,8 @@
  * @name    Deduct the needed flash wait states from the core clock frequency
  * @{
  */
-#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(STM32F3)
+#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+    defined(CPU_FAM_STM32F3)
 #define FLASH_WAITSTATES        ((CLOCK_CORECLOCK - 1) / 24000000U)
 #else
 #define FLASH_WAITSTATES        (CLOCK_CORECLOCK / 30000000U)
@@ -158,7 +161,8 @@
 #define FLASH_ACR_CONFIG        (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
 #elif defined(CPU_FAM_STM32F7)
 #define FLASH_ACR_CONFIG        (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
-#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
+#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+      defined(CPU_FAM_STM32F3)
 #define FLASH_ACR_CONFIG        (FLASH_ACR_PRFTBE | FLASH_WAITSTATES)
 #endif
 /** @} */
@@ -208,9 +212,11 @@ void stmclk_init_sysclk(void)
     RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
 #endif
     /* now we can safely configure and start the PLL */
-#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
+#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+    defined(CPU_FAM_STM32F7)
     RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q | PLL_R);
-#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
+#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
+      defined(CPU_FAM_STM32F3)
     /* reset PLL configuration bits */
     RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL);
     /* set PLL configuration */