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boards/p-nucleo-wb55: adapt to new generic clock config

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This commit is contained in:
Alexandre Abadie 2020-08-26 19:46:42 +02:00
parent b6dd78864b
commit c1a655c069
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GPG Key ID: 1C919A403CAE1405
1 changed files with 24 additions and 58 deletions
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82
boards/p-nucleo-wb55/include/periph_conf.h
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@ -21,6 +21,30 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
/* Add specific clock configuration (HSE, LSE) for this board here */
#define CLOCK_CORECLOCK_MAX MHZ(64)
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (1)
#endif
#define CLOCK_HSE MHZ(32)
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (5)
#endif
/* EXTAHB (HCLK2) max freq 32 Mhz*/
#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3
#define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2)
#include "l4/cfg_clock_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
@ -29,64 +53,6 @@
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (32000000U)
#ifndef CLOCK_LSE
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz)
*/
#define CLOCK_LSE (1)
#endif
/* 0: enable MSI only if HSE isn't available
* 1: always enable MSI (e.g. if USB or RNG is used)*/
#define CLOCK_MSI_ENABLE (1)
#ifndef CLOCK_MSI_LSE_PLL
/* 0: disable Hardware auto calibration with LSE
* 1: enable Hardware auto calibration with LSE (PLL-mode)
*/
#define CLOCK_MSI_LSE_PLL (1)
#endif
/* give the target core clock (HCLK) frequency [in Hz], maximum: 64MHz */
#define CLOCK_CORECLOCK (64000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2:8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 64MHz MAX!
*/
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (32)
#define CLOCK_PLL_R (4)
/* EXTAHB (HCLK2) max freq 32 Mhz*/
#define CLOCK_EXTAHB_DIV RCC_EXTCFGR_C2HPRE_3
#define CLOCK_EXTAHB (CLOCK_CORECLOCK / 2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV 0x00000000U
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV 0x00000000U
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2_DIV 0x00000000U
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name UART configuration
* @{