Merge pull request #15200 from maribu/mii
drivers: Add utilities for Ethernet Media-Independent Interface (MII) and use them in STM32 `periph_eth`
This commit is contained in:
benpicco
GitHub
commit
c1b0e47e98
@ -35,6 +35,7 @@
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#include "f2f4f7/cfg_clock_default_120.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_usb_otg_fs.h"
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#include "mii.h"
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#ifdef __cplusplus
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extern "C" {
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@ -248,7 +249,7 @@ static const adc_conf_t adc_config[] = {
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static const eth_conf_t eth_config = {
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.mode = RMII,
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.addr = { 0 },
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.speed = ETH_SPEED_100TX_FD,
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.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
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.dma = 6,
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.dma_chan = 8,
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.phy_addr = 0x00,
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@ -35,6 +35,7 @@
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#include "cfg_usb_otg_fs.h"
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#include "mii.h"
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#ifdef __cplusplus
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extern "C" {
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@ -219,7 +220,7 @@ static const spi_conf_t spi_config[] = {
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static const eth_conf_t eth_config = {
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.mode = RMII,
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.addr = { 0 },
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.speed = ETH_SPEED_100TX_FD,
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.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
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.dma = 7,
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.dma_chan = 8,
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.phy_addr = 0x00,
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@ -35,6 +35,7 @@
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#include "cfg_usb_otg_fs.h"
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#include "mii.h"
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#ifdef __cplusplus
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extern "C" {
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@ -167,7 +168,7 @@ static const spi_conf_t spi_config[] = {
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static const eth_conf_t eth_config = {
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.mode = RMII,
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.addr = { 0 },
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.speed = ETH_SPEED_100TX_FD,
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.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
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.dma = 3,
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.dma_chan = 8,
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.phy_addr = 0x00,
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@ -1018,34 +1018,24 @@ void dma_prepare(dma_t dma, void *mem, size_t len, bool incr_mem);
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* @brief STM32 Ethernet configuration mode
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*/
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typedef enum {
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MII = 18, /**< Configuration for MII */
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RMII = 9, /**< Configuration for RMII */
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SMI = 2, /**< Configuration for SMI */
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MII = 18, /**< Configuration for MII */
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RMII = 9, /**< Configuration for RMII */
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SMI = 2, /**< Configuration for SMI */
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} eth_mode_t;
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/**
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* @brief STM32 Ethernet speed options
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*/
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typedef enum {
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ETH_SPEED_10T_HD = 0x0000,
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ETH_SPEED_10T_FD = 0x0100,
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ETH_SPEED_100TX_HD = 0x2000,
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ETH_SPEED_100TX_FD = 0x2100,
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} eth_speed_t;
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/**
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* @brief Ethernet Peripheral configuration
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*/
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typedef struct {
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eth_mode_t mode; /**< Select configuration mode */
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uint8_t addr[6]; /**< Ethernet MAC address */
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eth_speed_t speed; /**< Speed selection */
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uint16_t speed; /**< Speed selection */
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uint8_t dma; /**< Locical CMA Descriptor used for TX */
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uint8_t dma_chan; /**< DMA channel used for TX */
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char phy_addr; /**< PHY address */
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uint8_t phy_addr; /**< PHY address */
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gpio_t pins[]; /**< Pins to use. MII requires 18 pins,
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RMII 9 and SMI 9. Not all speeds are
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supported by all modes. */
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RMII 9 and SMI 9. Not all speeds are
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supported by all modes. */
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} eth_conf_t;
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/**
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@ -1144,121 +1134,6 @@ typedef struct eth_dma_desc {
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#define TX_DESC_STAT_OWN (BIT31) /**< If set, descriptor is owned by DMA, otherwise by CPU */
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/** @} */
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/**
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* @name Ethernet PHY Common Registers
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* @{
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*/
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#define PHY_BMCR (0x00)
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#define PHY_BSMR (0x01)
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#define PHY_PHYIDR1 (0x02)
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#define PHY_PHYIDR2 (0x03)
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#define PHY_ANAR (0x04)
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#define PHY_ANLPAR (0x05)
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#define PHY_ANER (0x06)
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#define PHY_ANNPTR (0x07)
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/** @} */
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/**
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* @name Ethernet PHY BMCR Fields
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* @{
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*/
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#define BMCR_RESET (0x8000)
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#define BMCR_LOOPBACK (0x4000)
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#define BMCR_SPEED_SELECT (0x2000)
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#define BMCR_AN (0x1000)
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#define BMCR_POWER_DOWN (0x0800)
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#define BMCR_ISOLATE (0x0400)
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#define BMCR_RESTART_AN (0x0200)
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#define BMCR_DUPLEX_MODE (0x0100)
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#define BMCR_COLLISION_TEST (0x0080)
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/** @} */
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/**
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* @name Ethernet PHY BSMR Fields
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* @{
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*/
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#define BSMR_100BASE_T4 (0x8000)
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#define BSMR_100BASE_TX_FDUPLEX (0x4000)
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#define BSMR_100BASE_TX_HDUPLEX (0x2000)
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#define BSMR_10BASE_T_FDUPLEX (0x1000)
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#define BSMR_10BASE_T_HDUPLEX (0x0800)
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#define BSMR_NO_PREAMBLE (0x0040)
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#define BSMR_AN_COMPLETE (0x0020)
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#define BSMR_REMOTE_FAULT (0x0010)
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#define BSMR_AN_ABILITY (0x0008)
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#define BSMR_LINK_STATUS (0x0004)
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#define BSMR_JABBER_DETECT (0x0002)
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#define BSMR_EXTENDED_CAP (0x0001)
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/** @} */
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/**
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* @name Ethernet PHY PHYIDR1 Fields
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*/
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#define PHYIDR1_OUI (0xffff)
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/**
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* @name Ethernet PHY PHYIDR2 Fields
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* @{
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*/
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#define PHYIDR2_OUI (0xfe00)
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#define PHYIDR2_MODEL (0x01f0)
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#define PHYIDR2_REV (0x0007)
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/** @} */
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/**
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* @name Ethernet PHY ANAR Fields
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* @{
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*/
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#define ANAR_NEXT_PAGE (0x8000)
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#define ANAR_REMOTE_FAULT (0x2000)
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#define ANAR_PAUSE (0x0600)
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#define ANAR_100BASE_T4 (0x0200)
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#define ANAR_100BASE_TX_FDUPLEX (0x0100)
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#define ANAR_100BASE_TX_HDUPLEX (0x0080)
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#define ANAR_10BASE_T_FDUPLEX (0x0040)
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#define ANAR_10BASE_T_HDUPLEX (0x0020)
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#define ANAR_SELECTOR (0x000f)
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/** @} */
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/**
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* @name Ethernet PHY ANLPAR Fields
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* @{
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*/
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#define ANLPAR_NEXT_PAGE (0x8000)
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#define ANLPAR_ACK (0x4000)
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#define ANLPAR_REMOTE_FAULT (0x2000)
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#define ANLPAR_PAUSE (0x0600)
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#define ANLPAR_100BASE_T4 (0x0200)
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#define ANLPAR_100BASE_TX_FDUPLEX (0x0100)
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#define ANLPAR_100BASE_TX_HDUPLEX (0x0080)
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#define ANLPAR_10BASE_T_FDUPLEX (0x0040)
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#define ANLPAR_10BASE_T_HDUPLEX (0x0020)
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#define ANLPAR_SELECTOR (0x000f)
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/** @} */
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/**
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* @name Ethernet PHY ANNPTR Fields
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* @{
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*/
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#define ANNPTR_NEXT_PAGE (0x8000)
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#define ANNPTR_MSG_PAGE (0x2000)
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#define ANNPTR_ACK2 (0x1000)
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#define ANNPTR_TOGGLE_TX (0x0800)
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#define ANNPTR_CODE (0x03ff)
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/** @} */
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/**
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* @name Ethernet PHY ANER Fields
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* @{
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*/
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#define ANER_PDF (0x0010)
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#define ANER_LP_NEXT_PAGE_ABLE (0x0008)
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#define ANER_NEXT_PAGE_ABLE (0x0004)
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#define ANER_PAGE_RX (0x0002)
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#define ANER_LP_AN_ABLE (0x0001)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -25,6 +25,7 @@
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#include "bitarithm.h"
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#include "iolist.h"
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#include "luid.h"
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#include "mii.h"
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#include "mutex.h"
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#include "net/ethernet.h"
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#include "net/netdev/eth.h"
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@ -150,7 +151,7 @@ static inline void _mii_reg_write(uint8_t reg, uint16_t value)
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static inline bool _get_link_status(void)
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{
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return (_mii_reg_read(PHY_BSMR) & BSMR_LINK_STATUS);
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return (_mii_reg_read(MII_BMSR) & MII_BMSR_LINK);
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}
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static void stm32_eth_get_addr(char *out)
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@ -305,7 +306,7 @@ static int stm32_eth_init(netdev_t *netdev)
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/* configure the PHY (standard for all PHY's) */
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/* if there's no PHY, this has no effect */
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_mii_reg_write(PHY_BMCR, BMCR_RESET);
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_mii_reg_write(MII_BMCR, MII_BMCR_RESET);
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/* speed from conf */
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ETH->MACCR |= (ETH_MACCR_ROD | ETH_MACCR_IPCO | ETH_MACCR_APCS |
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@ -351,7 +352,7 @@ static int stm32_eth_init(netdev_t *netdev)
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/* configure speed, do it at the end so the PHY had time to
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* reset */
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_mii_reg_write(PHY_BMCR, eth_config.speed);
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_mii_reg_write(MII_BMCR, eth_config.speed);
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return 0;
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}
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179
drivers/include/mii.h
Normal file
179
drivers/include/mii.h
Normal file
@ -0,0 +1,179 @@
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/*
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* Copyright (C) 2020 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup drivers_mii Ethernet Media-Independent Interface (MII)
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* Utilities
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* @ingroup drivers_netdev
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*
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* This module contains constants and helpers as library to help working with
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* Ethernet PHYs connected via the Media-Independent Interface (MII) or the
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* Reduced Media-Independent Interface (RMII)
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*
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* @{
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*
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* @file
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* @brief Interface definition for MII/RMII h
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*
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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*/
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#ifndef MII_H
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#define MII_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "bitarithm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Common MII Management Register Set
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*
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* All registers except @ref MII_BMCR and @ref MII_BMSR are extended registers.
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* Support for extended registers is indicated by the @ref MII_BMSR_EXTENDED
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* bit in the @ref MII_BMSR register.
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*
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* @{
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*/
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#define MII_BMCR (0x00U) /**< Basic mode control register */
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#define MII_BMSR (0x01U) /**< Basic mode status register */
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#define MII_PHYID1 (0x02U) /**< PHY Identifier 1 */
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#define MII_PHYID2 (0x03U) /**< PHY Identifier 2 */
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#define MII_ADVERTISE (0x04U) /**< Auto-Negotiation Advertisement */
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#define MII_LPA (0x05U) /**< Link Parter Abilities */
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#define MII_EXPANSION (0x06U) /**< Auto-Negotiation Expansion */
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#define MII_ESTATUS (0x0fU) /**< Extended Status Register */
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/** @} */
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/**
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* @name Bits in the MII Basic Mode Control Register
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* @{
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*/
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#define MII_BMCR_RESET BIT15 /**< Set to perform PHY reset */
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#define MII_BMCR_LOOP BIT14 /**< Set to enable loopback mode */
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#define MII_BMCR_AN_ENABLE BIT12 /**< Set to enable auto-negotiation */
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#define MII_BMCR_POWER_DOWN BIT11 /**< Set to power down PHY */
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#define MII_BMCR_ISOLATE BIT10 /**< Set to electrically isolate PHY from
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MII (PHY becomes inoperational) */
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#define MII_BMCR_AN_RESTART BIT9 /**< Set to restart auto-negotation */
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#define MII_BMCR_FULL_DPLX BIT8 /**< Set for full duplex */
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#define MII_BMCR_HALF_DPLX (0) /**< Set for half duplex */
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#define MII_BMCR_COLL_TEST BIT7 /**< Set to enable collision signal test */
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#define MII_BMCR_SPEED_10 (0) /**< Set speed to 10 Mbps */
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#define MII_BMCR_SPEED_100 BIT13 /**< Set speed to 100 Mbps */
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#define MII_BMCR_SPEED_1000 BIT6 /**< Set speed to 1 Gbps */
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/** @} */
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/**
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* @name Bits in the MII Basic Mode Status Register
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* @{
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*/
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#define MII_BMSR_100_T4 BIT15 /**< PHY supports 100BASE-T4 (half-duplex) */
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#define MII_BMSR_100_TX_F BIT14 /**< PHY supports 100BASE-TX, full duplex */
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#define MII_BMSR_100_TX_H BIT13 /**< PHY supports 100BASE-TX, half duplex */
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#define MII_BMSR_10_F BIT12 /**< PHY supports 10BASE-T, full duplex */
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#define MII_BMSR_10_H BIT11 /**< PHY supports 10BASE-T, half duplex */
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#define MII_BMSR_100_T2_F BIT10 /**< PHY supports 100BASE-T2, full duplex */
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#define MII_BMSR_100_T2_H BIT9 /**< PHY supports 100BASE-T2, half duplex */
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#define MII_BMSR_ESTATUS BIT8 /**< Set, if @ref MII_ESTATUS is
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available */
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#define MII_BMSR_AN_DONE BIT5 /**< Set when auto-negotiation is done */
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#define MII_BMSR_FAULT BIT4 /**< Set when remote fault condition
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is detected */
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#define MII_BMSR_HAS_AN BIT3 /**< Set if PHY can auto-negotiate */
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#define MII_BMSR_LINK BIT2 /**< Set if link is up */
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#define MII_BMSR_JABBER BIT1 /**< Set when jabber condition detected */
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#define MII_BMSR_EXTENDED BIT0 /**< Extended MII registers available */
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/** @} */
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/**
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* @name Bits in the MII Extended Mode Advertisement Register
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* @{
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*/
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#define MII_ADVERTISE_100_F BIT8 /**< Advertise 100BASE-T, full duplex */
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#define MII_ADVERTISE_100_H BIT7 /**< Advertise 100BASE-T, half duplex */
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#define MII_ADVERTISE_10_F BIT6 /**< Advertise 10BASE-T, full duplex */
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#define MII_ADVERTISE_10_H BIT5 /**< Advertise 10BASE-T, half duplex */
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#define MII_ADVERTISE_100 (BIT7 | BIT8) /**< Advertise 100BASE-T */
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#define MII_ADVERTISE_10 (BIT5 | BIT6) /**< Advertise 10BASE-T */
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/** @} */
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/**
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* @name Bits in the MII Extended Mode Advertisement Register
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* @{
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*/
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#define MII_LPA_100_F BIT8 /**< Partner can 100BASE-T, full duplex */
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#define MII_LPA_100_H BIT7 /**< Partner can 100BASE-T, half duplex */
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#define MII_LPA_10_F BIT6 /**< Partner can 10BASE-T, full duplex */
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#define MII_LPA_10_H BIT5 /**< Partner can 10BASE-T, half duplex */
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#define MII_LPA_100 (BIT7 | BIT8) /**< Partner can 100BASE-T */
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#define MII_LPA_10 (BIT5 | BIT6) /**< Partner can 10BASE-T */
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/** @} */
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/**
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* @brief Check if an Ethernet PHY supports 100 Mbps at full duplex
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*
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* @param[in] bmsr Value of the MII basic mode status register
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*
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* @retval true PHY supports 100 Mbps at full duplex
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* @retval false PHY does not support 100 Mbps at full duplex
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*/
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static inline bool mii_can_100_mbps_full_dp(uint16_t bmsr)
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{
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return (bmsr & (MII_BMSR_100_TX_F | MII_BMSR_100_T2_F));
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}
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/**
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* @brief Check if an Ethernet PHY supports 100 Mbps at half duplex
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*
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* @param[in] bmsr Value of the MII basic mode status register
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*
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* @retval true PHY supports 100 Mbps at half duplex
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* @retval false PHY does not support 100 Mbps at half duplex
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*/
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static inline bool mii_can_100_mbps_half_dp(uint16_t bmsr)
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{
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return (bmsr & (MII_BMSR_100_T4 | MII_BMSR_100_TX_H | MII_BMSR_100_T2_H));
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}
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/**
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* @brief Check if an Ethernet PHY supports 10 Mbps at full duplex
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*
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* @param[in] bmsr Value of the MII basic mode status register
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*
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* @retval true PHY supports 10 Mbps at full duplex
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* @retval false PHY does not support 10 Mbps at full duplex
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*/
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static inline bool mii_can_10_mbps_full_dp(uint16_t bmsr)
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{
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return (bmsr & MII_BMSR_10_F);
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}
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/**
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* @brief Check if an Ethernet PHY supports 10 Mbps at half duplex
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*
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* @param[in] bmsr Value of the MII basic mode status register
|
||||
*
|
||||
* @retval true PHY supports 10 Mbps at half duplex
|
||||
* @retval false PHY does not support 10 Mbps at half duplex
|
||||
*/
|
||||
static inline bool mii_can_10_mbps_half_dp(uint16_t bmsr)
|
||||
{
|
||||
return (bmsr & MII_BMSR_10_H);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* MII_H */
|
||||
/** @} */
|
||||
Loading…
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Reference in New Issue
Block a user