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Merge pull request #2282 from gebart/pr/k60-initial

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Add support for Kinetis K60 CPUs and Eistec Mulle IoT board
This commit is contained in:
Oleg Hahm 2015-04-10 00:22:21 +02:00
commit c1ecccfbd8
41 changed files with 27935 additions and 0 deletions
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# tell the Makefile.base which module to build
MODULE = $(BOARD)_base
include $(RIOTBASE)/Makefile.base

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ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
USEMODULE += at86rf231
ifeq (,$(filter netdev_base,$(USEMODULE)))
USEMODULE += transceiver
endif
endif
# The Mulle uses NVRAM to store persistent variables, such as boot count.
#~ USEMODULE += nvram_spi
# Uncomment above when #2353 is merged.

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FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_random
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += transceiver

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# define the cpu used by the Mulle board
export CPU = k60
# Default GDB port
export GDBPORT ?= 3333
# MULLE_SERIAL is used to select which specific Mulle board we are compiling for.
# This was called MULLE_BOARD_SERIAL_NUMBER previously, renamed because
# MULLE_BOARD_SERIAL_NUMBER is too long to type.
ifdef MULLE_SERIAL
ifeq "200" "$(word 1, $(sort 200 $(MULLE_SERIAL)))"
# >= 200
ifneq "220" "$(word 1, $(sort 220 $(MULLE_SERIAL)))"
# < 220
CPU_MODEL = K60DN256ZVLL10
# It seems some of the MK60DZ10 devices have problems with JTAG speeds >= around 400 KHz
# when programming, we reduce the speed to 300 KHz with this command.
CPU_OOCD_FLAGS += -c 'adapter_khz 300'
else
# >= 220
CPU_MODEL = K60DN512VLL10
endif
endif
CFLAGS += -DMULLE_SERIAL=$(MULLE_SERIAL)
endif
### CPU part number (must have a specific linker script for each part)
# Note that MK60DN256ZVLL10 (version 1.x) and MK60DN256VLL10 (version 2.x, no Z)
# only differ in some register locations etc, not in the actual memory layout,
# so it is safe to use the same linker script for both version 1.x and version
# 2.x silicon.
# The linker script needs to know the flash and RAM sizes of the device.
ifeq ($(CPU_MODEL),)
CPU_MODEL = K60DN512VLL10
endif
export CPU_MODEL
# Host OS name
OS := $(shell uname)
# OpenOCD settings for Mulle board.
# Try to determine which version of the OpenOCD config file we should use.
# Specify PROGRAMMER_VERSION or PROGRAMMER_SERIAL to choose a specific programmer board.
ifeq ($(PROGRAMMER_VERSION),)
ifneq ($(PROGRAMMER_SERIAL),)
# Makefile-way of comparing numbers, using lexicographical sorting since we don't have any arithmetic comparisons.
# Programmers with serial 100 -- 148 are version 0.60
# Programmers with serial 301 -- 330 are version 0.70
ifeq "100" "$(word 1, $(sort 100 $(PROGRAMMER_SERIAL)))"
# >= 100
ifneq "149" "$(word 1, $(sort 149 $(PROGRAMMER_SERIAL)))"
# < 149
PROGRAMMER_VERSION = 0.60
else
# >= 149
PROGRAMMER_VERSION = 0.70
endif
endif
endif
# Default to version 0.60 programmer for now.
PROGRAMMER_VERSION ?= 0.60
endif
export OPENOCD_CONFIG = $(RIOTBOARD)/$(BOARD)/dist/openocd/mulle-programmer-$(PROGRAMMER_VERSION).conf
# Add serial matching command
ifneq ($(PROGRAMMER_SERIAL),)
OPENOCD_EXTRA_INIT += -c 'ftdi_serial $(PROGRAMMER_SERIAL)'
endif
OPENOCD_EXTRA_INIT += $(CPU_OOCD_FLAGS)
ifeq ($(PORT),)
# try to find tty name by serial number, only works on Linux currently.
ifeq ($(OS),Linux)
ifneq ($(PROGRAMMER_SERIAL),)
PORT := $(shell $(RIOTBASE)/dist/tools/usb-serial/find-tty.sh '^$(PROGRAMMER_SERIAL)$$')
else
# find-tty.sh will return the first USB tty if no serial is given.
PORT := $(shell $(RIOTBASE)/dist/tools/usb-serial/find-tty.sh)
endif
else ifeq ($(OS),Darwin)
PORT := $(shell ls -1 /dev/tty.usbserial* | head -n 1)
endif
endif
# TODO: add support for windows as host platform
ifeq ($(PORT),)
# None of the above methods worked, set some sane default value for PORT.
$(info CAUTION: No terminal port for your host system found!)
PORT := /dev/ttyUSB0
endif
export PORT
# Default optimization level, possible to override from command line.
OPTIMIZATION ?= -Os
# Default debug level
DEBUG_CFLAGS ?= -g3 -ggdb
# Target triple for the build. Use arm-none-eabi if you are unsure.
export TARGET_TRIPLE ?= arm-none-eabi
# Toolchain prefix, defaults to target triple followed by a dash, you will most likely not need to touch this.
export PREFIX ?= $(if $(TARGET_TRIPLE),$(TARGET_TRIPLE)-)
export GDBPREFIX ?= $(PREFIX)
# define tools used for building the project
export CC = $(PREFIX)gcc
export CXX = $(PREFIX)g++
export AR = $(PREFIX)ar
export AS = $(PREFIX)as
export LINK = $(PREFIX)gcc
export SIZE = $(PREFIX)size
export OBJCOPY = $(PREFIX)objcopy
export OPENOCD ?= openocd
export GDB ?= $(GDBPREFIX)gdb
export DBG = $(GDB)
export TERMPROG ?= $(RIOTBASE)/dist/tools/pyterm/pyterm
export FLASHER = $(RIOTBASE)/dist/tools/openocd/openocd.sh
export DEBUGGER = $(RIOTBASE)/dist/tools/openocd/openocd.sh
export DEBUGSERVER = $(RIOTBASE)/dist/tools/openocd/openocd.sh
export RESET = $(RIOTBASE)/dist/tools/openocd/openocd.sh
export TERMFLAGS += -p "$(PORT)"
export FFLAGS = flash $(OPENOCD_EXTRA_INIT)
export DEBUGGER_FLAGS = debug $(OPENOCD_EXTRA_INIT)
export DEBUGSERVER_FLAGS = debug-server $(OPENOCD_EXTRA_INIT)
export RESET_FLAGS = reset $(OPENOCD_EXTRA_INIT)
# define build specific options
CPU_USAGE = -mcpu=cortex-m4
FPU_USAGE = -mfloat-abi=soft -msoft-float
export CFLAGS += \
$(DEBUG_CFLAGS) \
-std=gnu99 \
$(OPTIMIZATION) \
-Wall -Wstrict-prototypes -Werror=implicit-function-declaration \
$(CPU_USAGE) \
$(FPU_USAGE) \
-mlittle-endian \
-mthumb \
-fno-common \
-fshort-enums \
-ffunction-sections \
-fdata-sections \
-fno-builtin \
-fno-strict-aliasing \
-fsigned-char \
#
export CXXFLAGS += \
-ffunction-sections \
-fdata-sections \
-fno-builtin \
#
export ASFLAGS += \
$(DEBUG_CFLAGS) \
$(CPU_USAGE) \
$(FPU_USAGE) \
-mlittle-endian \
#
export LINKFLAGS += \
$(DEBUG_CFLAGS) \
-std=gnu99 \
$(CPU_USAGE) \
$(FPU_USAGE) \
-mlittle-endian \
-static \
-mthumb \
-nostartfiles \
-Wl,--fatal-warnings \
#
export LINKFLAGS += -T$(LINKERSCRIPT)
export OFLAGS ?= -O ihex
ifdef BUILD_WITH_CLANG
ifneq ($(BUILD_WITH_CLANG),0)
export CFLAGS += -target $(TARGET_TRIPLE)
export CXXFLAGS += -target $(TARGET_TRIPLE)
export LINKFLAGS += -target $(TARGET_TRIPLE)
export CC = clang
export CXX = clang++
export LINK = clang
export LLVMPREFIX ?= llvm-
export AS = $(LLVMPREFIX)as
export AR = $(LLVMPREFIX)ar
export NM = $(LLVMPREFIX)nm
# There is no LLVM linker yet, use binutils.
#export LINKER = $(LLVMPREFIX)ld
# objcopy does not have a clear substitute in LLVM
#export OBJCOPY = $(LLVMPREFIX)objcopy
export OBJDUMP = $(LLVMPREFIX)objdump
# LLVM lacks a binutils strip tool as well...
#export STRIP = $(LLVMPREFIX)strip
export SIZE = $(LLVMPREFIX)size
# Since Clang is not installed as a separate instance for each crossdev target
# we need to tell it where to look for platform specific includes (Newlib
# headers instead of Linux/Glibc headers.)
# On GCC this is done when building the cross compiler toolchain so we do not
# actually need to specify the include paths for system includes.
# Ubuntu gcc-arm-embedded toolchain (https://launchpad.net/gcc-arm-embedded)
# places newlib headers in several places, but the primary source seem to be
# /etc/alternatives/gcc-arm-none-eabi-include
# Gentoo crossdev places newlib headers in /usr/arm-none-eabi/include
# Ubuntu also seem to put a copy of the newlib headers in the same place as
# Gentoo crossdev, but we prefer to look at /etc/alternatives first.
# On OSX, newlib includes are possibly located in
# /usr/local/opt/arm-none-eabi*/arm-none-eabi/include
NEWLIB_INCLUDE_PATTERNS ?= \
/etc/alternatives/gcc-$(TARGET_TRIPLE)-include \
/usr/$(TARGET_TRIPLE)/include \
/usr/local/opt/$(TARGET_TRIPLE)*/$(TARGET_TRIPLE)/include \
#
# Use the wildcard Makefile function to search for existing directories matching
# the patterns above. We use the -isystem gcc/clang argument to add the include
# directories as system include directories.
NEWLIB_INCLUDES ?= \
$(foreach dir, \
$(foreach pat, $(NEWLIB_INCLUDE_PATTERNS), $(wildcard $(pat))), \
-isystem $(dir))
endif
endif
export INCLUDES += $(NEWLIB_INCLUDES)
# use newlib nano-specs if available
ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null </dev/null ; echo $$?),0)
export LINKFLAGS += -specs=nano.specs -lc
endif
# export board specific includes to the global includes-listing
export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include
include $(RIOTBOARD)/$(BOARD)/Makefile.dep

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/*
* Copyright (C) 2014-2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_mulle
* @{
*
* @file
* @brief Board specific implementations for the Mulle board
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include <stddef.h> /* for NULL */
#include <stdio.h>
#include "board.h"
#include "cpu.h"
#include "mcg.h"
#include "periph/gpio.h"
#include "periph/uart.h"
#include "periph/rtc.h"
#include "devicemap.h"
/**
* @brief Initialize the boards on-board LEDs
*
* The LEDs are initialized here in order to be able to use them in the early
* boot for diagnostics.
*
*/
static inline void leds_init(void);
/** @brief Initialize the GPIO pins controlling the power switches. */
static inline void power_pins_init(void);
/**
* @brief Set clock prescalers to safe values
*
* This should be done before switching to FLL/PLL as clock source to ensure
* that all clocks remain within the specified limits.
*/
static inline void set_safe_clock_dividers(void);
/** @brief Set the FLL source clock to RTC32k */
static inline void set_fll_source(void);
void board_init(void)
{
/* initialize the boards LEDs, this is done first for debugging purposes */
leds_init();
LED_RED_ON;
/* Initialize RTC oscillator as early as possible since we are using it as a
* base clock for the FLL.
* It takes a while to stabilize the oscillator, therefore we do this as
* soon as possible during boot in order to let it stabilize while other
* stuff is initializing. */
/* If the clock is not stable then the UART will have the wrong baud rate
* for debug prints as well */
rtc_init();
/* Set up clocks */
set_safe_clock_dividers();
set_fll_source();
kinetis_mcg_set_mode(KINETIS_MCG_FEE);
/* At this point we need to wait for 1 ms until the clock is stable.
* Since the clock is not yet stable we can only guess how long we must
* wait. I have tried to make this as short as possible but still being able
* to read the initialization messages written on the UART.
* (If the clock is not stable all UART output is garbled until it has
* stabilized) */
for (int i = 0; i < 100000; ++i) {
asm volatile("nop\n");
}
/* Update SystemCoreClock global var */
SystemCoreClockUpdate();
/* initialize the CPU */
cpu_init();
LED_YELLOW_ON;
devicemap_init();
LED_GREEN_ON;
/* Initialize power control pins */
power_pins_init();
/* Turn on Vperiph for peripherals */
gpio_set(MULLE_POWER_VPERIPH);
/* Turn on AVDD for reading voltages */
gpio_set(MULLE_POWER_AVDD);
}
static inline void leds_init(void)
{
/* The pin configuration can be found in board.h and periph_conf.h */
gpio_init_out(LED_RED_GPIO, GPIO_NOPULL);
gpio_init_out(LED_YELLOW_GPIO, GPIO_NOPULL);
gpio_init_out(LED_GREEN_GPIO, GPIO_NOPULL);
}
static inline void power_pins_init(void)
{
gpio_init_out(MULLE_POWER_AVDD, GPIO_NOPULL);
gpio_init_out(MULLE_POWER_VPERIPH, GPIO_NOPULL);
gpio_init_out(MULLE_POWER_VSEC, GPIO_NOPULL);
gpio_clear(MULLE_POWER_AVDD);
gpio_clear(MULLE_POWER_VPERIPH);
gpio_clear(MULLE_POWER_VSEC);
}
static inline void set_safe_clock_dividers(void)
{
/*
* We want to achieve the following clocks:
* Core/system: <100MHz
* Bus: <50MHz
* FlexBus: <50MHz
* Flash: <25MHz
*
* using dividers 1-2-2-4 will obey the above limits when using a 96MHz FLL source.
*/
SIM->CLKDIV1 = (
SIM_CLKDIV1_OUTDIV1(CONFIG_CLOCK_K60_SYS_DIV) | /* Core/System clock divider */
SIM_CLKDIV1_OUTDIV2(CONFIG_CLOCK_K60_BUS_DIV) | /* Bus clock divider */
SIM_CLKDIV1_OUTDIV3(CONFIG_CLOCK_K60_FB_DIV) | /* FlexBus divider, not used in Mulle */
SIM_CLKDIV1_OUTDIV4(CONFIG_CLOCK_K60_FLASH_DIV)); /* Flash clock divider */
}
static inline void set_fll_source(void)
{
/* Select FLL as source (as opposed to PLL) */
SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK);
/* Use external 32kHz RTC clock as source for OSC32K */
/* This is also done by hwtimer_arch, but we need it sooner than
* hwtimer_init. */
#if K60_CPU_REV == 1
SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL_MASK;
#elif K60_CPU_REV == 2
SIM->SOPT1 = (SIM->SOPT1 & ~(SIM_SOPT1_OSC32KSEL_MASK)) | SIM_SOPT1_OSC32KSEL(2);
#else
#error Unknown K60 CPU revision
#endif
/* Select RTC 32kHz clock as reference clock for the FLL */
#if K60_CPU_REV == 1
/* Rev 1 parts */
SIM->SOPT2 |= SIM_SOPT2_MCGCLKSEL_MASK;
#elif K60_CPU_REV == 2
/* Rev 2 parts */
MCG->C7 = (MCG_C7_OSCSEL_MASK);
#else
#error Unknown K60 CPU revision
#endif
}

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_mulle
* @{
*/
/**
* @file
* @brief Mulle config module implementation
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @note Waiting for PR #2353 (NVRAM API) before implementing this.
*/
#include <stdint.h>
#include <string.h>
#include "config.h"
void config_load(void)
{
/* TODO: Implement */
}
uint8_t config_save(void)
{
/* TODO: Implement */
return 0;
}

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/*
* Copyright (C) 2014-2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_mulle
* @{
*
* @file
* @brief Device I/O mappings for the Mulle platform.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include <stddef.h> /* for NULL */
#include "devopttab.h"
#include "devicemap.h"
#include "devio-uart.h"
#include "devio-null.h"
#include "cpu.h"
#include "periph_conf.h"
#include "periph/uart.h"
#if UART_0_EN
static const devoptab_t dotab_uart0 = {
"UART0", /* name */
1, /* isatty */
S_IFCHR | S_IRWXU | S_IRWXG | S_IRWXO, /* Character device, 0777 perms (crwxrwxrwx) */
devnull_open_r,
devnull_close_r,
uart0_write_r,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
#endif
#if UART_1_EN
static const devoptab_t dotab_uart1 = {
"UART1", /* name */
1, /* isatty */
S_IFCHR | S_IRWXU | S_IRWXG | S_IRWXO, /* Character device, 0777 perms (crwxrwxrwx) */
devnull_open_r,
devnull_close_r,
uart1_write_r,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
#endif
#if UART_2_EN
static const devoptab_t dotab_uart2 = {
"UART2", /* name */
1, /* isatty */
S_IFCHR | S_IRWXU | S_IRWXG | S_IRWXO, /* Character device, 0777 perms (crwxrwxrwx) */
devnull_open_r,
devnull_close_r,
uart2_write_r,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
#endif
#if UART_3_EN
static const devoptab_t dotab_uart3 = {
"UART3", /* name */
1, /* isatty */
S_IFCHR | S_IRWXU | S_IRWXG | S_IRWXO, /* Character device, 0777 perms (crwxrwxrwx) */
devnull_open_r,
devnull_close_r,
uart3_write_r,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
#endif
#if UART_4_EN
static const devoptab_t dotab_uart4 = {
"UART4", /* name */
1, /* isatty */
S_IFCHR | S_IRWXU | S_IRWXG | S_IRWXO, /* Character device, 0777 perms (crwxrwxrwx) */
devnull_open_r,
devnull_close_r,
uart4_write_r,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
#endif
static const devoptab_t dotab_stdin = {
"stdin", /* name */
1, /* isatty */
S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, /* Character device, 0444 perms (cr--r--r--) */
devnull_open_r,
devnull_close_r,
NULL,
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
static const devoptab_t dotab_stdout = {
"stdout", /* name */
1, /* isatty */
S_IFCHR | S_IWUSR | S_IWGRP | S_IWOTH, /* Character device, 0222 perms (c-w--w--w-) */
devnull_open_r,
devnull_close_r,
#if UART_0_EN
uart0_write_r,
#else
NULL, /* No stdout */
#endif
NULL, /* Not yet implemented */
NULL, /* No seeking on UART */
NULL, /* No fstat on UART */
};
/* This table maps the standard streams to device operations table entries. */
const devoptab_t *devoptab_list[MAX_OPEN_DEVICES] = { 0 };
static const devoptab_name_t devoptab_names[] = {
#if UART_0_EN
{"UART0", &dotab_uart0},
#endif
#if UART_1_EN
{"UART1", &dotab_uart1},
#endif
#if UART_2_EN
{"UART2", &dotab_uart2},
#endif
#if UART_3_EN
{"UART3", &dotab_uart3},
#endif
#if UART_4_EN
{"UART4", &dotab_uart4},
#endif
};
const devoptab_name_list_t devoptab_name_list = {
sizeof(devoptab_names) / sizeof(devoptab_names[0]), /* len */
&devoptab_names[0], /* data */
};
void devicemap_init(void)
{
/* Set up stdin, stdout and stderr */
devoptab_list[STDIN_FILENO] = &dotab_stdin;
devoptab_list[STDOUT_FILENO] = &dotab_stdout;
devoptab_list[STDERR_FILENO] = &dotab_stdout;
}

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set architecture arm
set arm force-mode thumb
set remote hardware-breakpoint-limit 6
set remote hardware-watchpoint-limit 4

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Mulle OpenOCD configuration files
=================================
The configuration file in this directory has been tested with OpenOCD v0.7.0.
The interface used is ftdi, OpenOCD must be built with --enable-ftdi
To start the OpenOCD GDB server:
openocd -f mulle.cfg

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#
# Mulle programming board.
#
# The Mulle programming board uses a FTDI FT2232H chip for USB UART and JTAG
# combined functionality.
#
# Reduce this if you are having problems with losing connection to the Mulle
adapter_khz 1000
# JTAG interface configuration
interface ftdi
ftdi_device_desc "Mulle Programmer v0.60"
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
ftdi_layout_init 0x0008 0x005b
# These are the pins that are used for SRST and TRST. Note that the Mulle
# programming board inverts the reset signal between the FTDI chip and the MCU,
# so we need to use -ndata here to tell OpenOCD that the signals are active HIGH.
ftdi_layout_signal nTRST -ndata 0x0010
ftdi_layout_signal nSRST -ndata 0x0040
# In the eyes of OpenOCD, the reset signal is push-pull, because of the hardware
# design however, it is actually open drain.
# The trst pin can only be used if the MCU has been configured by setting the
# correct pin multiplexing function on the TRST pin (PTA5).
# If you have configured the TRST pin correctly you can change srst_only to
# trst_and_srst
reset_config srst_only srst_push_pull srst_gates_jtag
# MCU
gdb_memory_map enable
gdb_flash_program enable
source [find target/k60.cfg]
#
# Bank definition for the 'program flash' (instructions and/or data)
#
flash bank $_CHIPNAME.pflash.0 kinetis 0x00000000 0x20000 0 4 $_TARGETNAME
flash bank $_CHIPNAME.pflash.1 kinetis 0x00020000 0x20000 0 4 $_TARGETNAME
# The following section makes new gdb connections cause the MCU to do a system
# reset, in order to be in a known state.
# Comment this out in order to be able to debug an already started program.
$_TARGETNAME configure -event gdb-attach {
echo "Resetting because of gdb-attach event..."
# To make flash probe and gdb load to flash work we need a reset init.
reset init
}

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#
# Mulle programming board.
#
# The Mulle programming board uses a FTDI FT2232H chip for USB UART and JTAG
# combined functionality.
#
# Reduce this if you are having problems with losing connection to the Mulle
adapter_khz 1000
# JTAG interface configuration
interface ftdi
ftdi_device_desc "Mulle Programmer v0.70"
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 1
ftdi_layout_init 0x0008 0x005b
# These are the pins that are used for SRST and TRST. Active LOW on programmer
# boards v0.70 and up (used to be active HIGH)
ftdi_layout_signal nTRST -data 0x0010
ftdi_layout_signal nSRST -data 0x0040
# In the eyes of OpenOCD, the reset signal is push-pull, because of the hardware
# design however, it is actually open drain.
# The trst pin can only be used if the MCU has been configured by setting the
# correct pin multiplexing function on the TRST pin (PTA5).
# If you have configured the TRST pin correctly you can change srst_only to
# trst_and_srst
reset_config srst_only srst_push_pull srst_gates_jtag
# MCU
gdb_memory_map enable
gdb_flash_program enable
source [find target/k60.cfg]
#
# Bank definition for the 'program flash' (instructions and/or data)
#
flash bank $_CHIPNAME.pflash.0 kinetis 0x00000000 0x40000 0 4 $_TARGETNAME
flash bank $_CHIPNAME.pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
# The following section makes new gdb connections cause the MCU to do a system
# reset, in order to be in a known state.
# Comment this out in order to be able to debug an already started program.
$_TARGETNAME configure -event gdb-attach {
echo "Resetting because of gdb-attach event..."
# To make flash probe and gdb load to flash work we need a reset init.
reset init
}

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/*
* Copyright (C) 2014 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup board_mulle Eistec Mulle
* @ingroup boards
* @brief Board specific files for Eistec Mulle IoT boards
* @{
*
* @file
* @brief Board specific definitions for the Eistec Mulle IoT board
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef BOARD_H_
#define BOARD_H_
#include "cpu.h"
#include "periph_conf.h"
/* Use the on board RTC 32kHz clock for LPTMR clocking. */
#undef LPTIMER_CLKSRC
/** @brief Clock source for the LPTMR module */
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
/** Disable hardware watchdog, for debugging purposes, don't use this on production builds. */
#define DISABLE_WDOG 1
/**
* @name Assign the first hardware timer.
* This timer will be used to implement an absolute reference for hwtimer_now() et al.
*/
#define HW_TIMER TIMER_0
/**
* @name Number of subsequent channels of the PIT to assign to the RIOT hardware
* timer library, starting after the HW_TIMER above.
*/
#define HW_TIMERS_COUNT 1
/**
* @name Define UART device and baudrate for stdio
* @{
*/
#define STDIO UART_0
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */
/**
* @name LEDs configuration
* @{
*/
#define LED_RED_GPIO GPIO_0
#define LED_RED_PORT GPIO_0_DEV
#define LED_RED_PIN GPIO_0_PIN
#define LED_YELLOW_GPIO GPIO_1
#define LED_YELLOW_PORT GPIO_1_DEV
#define LED_YELLOW_PIN GPIO_1_PIN
#define LED_GREEN_GPIO GPIO_2
#define LED_GREEN_PORT GPIO_2_DEV
#define LED_GREEN_PIN GPIO_2_PIN
/** @} */
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_RED_ON (BITBAND_REG(LED_RED_PORT->PSOR, LED_RED_PIN) = 1)
#define LED_RED_OFF (BITBAND_REG(LED_RED_PORT->PCOR, LED_RED_PIN) = 1)
#define LED_RED_TOGGLE (BITBAND_REG(LED_RED_PORT->PTOR, LED_RED_PIN) = 1)
#define LED_YELLOW_ON (BITBAND_REG(LED_YELLOW_PORT->PSOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_OFF (BITBAND_REG(LED_YELLOW_PORT->PCOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_TOGGLE (BITBAND_REG(LED_YELLOW_PORT->PTOR, LED_YELLOW_PIN) = 1)
#define LED_GREEN_ON (BITBAND_REG(LED_GREEN_PORT->PSOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_OFF (BITBAND_REG(LED_GREEN_PORT->PCOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_TOGGLE (BITBAND_REG(LED_GREEN_PORT->PTOR, LED_GREEN_PIN) = 1)
/** @} */
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
/**
* Define the type for the radio packet length for the transceiver
*/
typedef uint8_t radio_packet_length_t;
#ifdef __cplusplus
}
#endif
/**
* @name Define the interface to the AT86RF231 radio
* @{
*/
#define AT86RF231_SPI SPI_0
#define AT86RF231_CS GPIO_14
#define AT86RF231_INT GPIO_12
/** @todo work around missing RESET pin on Mulle v0.6x */
#define AT86RF231_RESET GPIO_5
#define AT86RF231_SLEEP GPIO_13
/** @} */
/**
* @name LIS3DH configuration
* @{
*/
#define LIS3DH_INT1 GPIO_3
#define LIS3DH_INT2 GPIO_4
#define LIS3DH_CS GPIO_15
#define LIS3DH_SPI SPI_2
/** @} */
/**
* @name Mulle power control configuration
*/
/** @{ */
#define MULLE_POWER_AVDD GPIO_6 /**< AVDD enable pin */
#define MULLE_POWER_VPERIPH GPIO_7 /**< VPERIPH enable pin */
#define MULLE_POWER_VSEC GPIO_5 /**< VSEC enable pin */
/** @} */
/**
* @name K60 clock dividers
*/
/** @{ */
/**
* System clock divider setting, the actual hardware register value, see reference manual for details.
*/
#define CONFIG_CLOCK_K60_SYS_DIV 0x00
/**
* Bus clock divider setting, the actual hardware register value, see reference manual for details
*/
#define CONFIG_CLOCK_K60_BUS_DIV 0x01
/**
* Flexbus clock divider setting, the actual hardware register value, see reference manual for details
*/
#define CONFIG_CLOCK_K60_FB_DIV 0x01
/**
* Flash clock divider setting, the actual hardware register value, see reference manual for details
*/
#define CONFIG_CLOCK_K60_FLASH_DIV 0x03
/** @} */
#endif /* BOARD_H_ */
/** @} */

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/*
* Copyright (C) 2014-2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#ifndef DEVICEMAP_H_
#define DEVICEMAP_H_
/**
* @ingroup board_mulle
* @{
*
* @file
* @brief Device I/O mappings for the Mulle platform.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
*/
#include "devopttab.h"
/** Maximum number of file descriptors allocated to hardware devices. All fd's
* above this number will be remapped to CFS accesses. */
#define MAX_OPEN_DEVICES 16 /* Arbitrarily chosen */
/** Number of IO devices in this platform implementation */
#define NUM_IO_DEVICES 16 /* Arbitrarily chosen */
#ifdef __cplusplus
extern "C" {
#endif
/* This table maps the standard streams to device operations table entries. */
extern const devoptab_t *devoptab_list[MAX_OPEN_DEVICES];
/* This table maps filenames to devices */
/** @brief Mappings between file name and device handle */
typedef struct {
const char *name; /**< Device file name */
const devoptab_t *devoptab; /**< Pointer to device operations table entry */
} devoptab_name_t;
/** @brief Table of device files */
typedef struct {
unsigned int len; /**< number of entries */
const devoptab_name_t *data; /**< Pointer to first table entry */
} devoptab_name_list_t;
extern const devoptab_name_list_t devoptab_name_list;
/** @brief Initialize the device map */
void devicemap_init(void);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* !defined(DEVICEMAP_H_) */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup board_mulle
* @{
*
* @file
* @name Peripheral MCU configuration for the Eistec Mulle
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef MULLE_PERIPH_CONF_H
#define MULLE_PERIPH_CONF_H
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Clock system configuration
* @{
*/
#define KINETIS_CPU_USE_MCG 1
#define KINETIS_MCG_USE_ERC 1
#define KINETIS_MCG_USE_PLL 0
#define KINETIS_MCG_DCO_RANGE (96000000U)
#define KINETIS_MCG_ERC_OSCILLATOR 0
#define KINETIS_MCG_ERC_FRDIV 0
#define KINETIS_MCG_ERC_RANGE 0
#define KINETIS_MCG_ERC_FREQ (32768U)
/* Base clocks, used by SystemCoreClockUpdate */
/** Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL_CLK_HZ 8000000u
/** Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u
/** Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u
/** Value of the fast internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u
/** Default System clock value */
#define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u)
/** @todo Investigate the side effects of making F_CPU run-time variable */
#define F_CPU DEFAULT_SYSTEM_CLOCK
/** @} */
/**
* @name Timer configuration
* @{
*/
#define TIMER_NUMOF (1U)
#define TIMER_0_EN 1
#define TIMER_1_EN 0
#define TIMER_IRQ_PRIO 1
#define TIMER_DEV PIT
#define TIMER_MAX_VALUE (0xffffffff)
#define TIMER_CLOCK SystemBusClock
#define TIMER_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT) = 1)
/* Timer 0 configuration */
#define TIMER_0_PRESCALER_CH 0
#define TIMER_0_COUNTER_CH 1
#define TIMER_0_ISR isr_pit1
#define TIMER_0_IRQ_CHAN PIT1_IRQn
/* Timer 1 configuration */
#define TIMER_1_PRESCALER_CH 2
#define TIMER_1_COUNTER_CH 3
#define TIMER_1_ISR isr_pit3
#define TIMER_1_IRQ_CHAN PIT3_IRQn
/** @} */
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (2U)
#define UART_0_EN 1
#define UART_1_EN 1
#define UART_2_EN 0
#define UART_3_EN 0
#define UART_4_EN 0
#define UART_IRQ_PRIO 1
/* UART 0 device configuration */
#define UART_0_DEV UART1
#define UART_0_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
#define UART_0_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
#define UART_0_CLK (SystemSysClock)
#define UART_0_IRQ_CHAN UART1_RX_TX_IRQn
#define UART_0_ISR isr_uart1_status
/* UART 0 pin configuration */
#define UART_0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define UART_0_PORT PORTC
#define UART_0_TX_PIN 4
#define UART_0_RX_PIN 3
/* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
* section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
#define UART_0_AF 3
#define UART_0_TX_PCR_MUX 3
#define UART_0_RX_PCR_MUX 3
/* UART 1 device configuration */
#define UART_1_DEV UART0
#define UART_1_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
#define UART_1_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
#define UART_1_CLK (SystemSysClock)
#define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
#define UART_1_ISR isr_uart0_status
/* UART 1 pin configuration */
#define UART_1_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
#define UART_1_PORT PORTA
#define UART_1_TX_PIN 14
#define UART_1_RX_PIN 15
/* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
* section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
#define UART_1_AF 3
#define UART_1_TX_PCR_MUX 3
#define UART_1_RX_PCR_MUX 3
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (2U)
#define ADC_0_EN 1
#define ADC_1_EN 1
#define ADC_MAX_CHANNELS 6
/* ADC 0 configuration */
#define ADC_0_DEV ADC0
#define ADC_0_CHANNELS 4
#define ADC_0_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 1)
#define ADC_0_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 0)
#define ADC_0_PORT_CLKEN() /* no PORT pins configured */
#define ADC_0_MODULE_CLOCK SystemBusClock
/* ADC 0 channel 0 pin config */
#define ADC_0_CH0 26 /* Temp sensor channel */
#define ADC_0_CH0_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_0_CH0_PIN 0
#define ADC_0_CH0_PIN_AF 0
/* ADC 0 channel 1 pin config */
#define ADC_0_CH1 27 /* Band gap channel */
#define ADC_0_CH1_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_0_CH1_PIN 0
#define ADC_0_CH1_PIN_AF 0
/* ADC 0 channel 2 pin config */
#define ADC_0_CH2 29 /* V_REFSH */
#define ADC_0_CH2_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_0_CH2_PIN 0
#define ADC_0_CH2_PIN_AF 0
/* ADC 0 channel 3 pin config */
#define ADC_0_CH3 30 /* V_REFSL */
#define ADC_0_CH3_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_0_CH3_PIN 0
#define ADC_0_CH3_PIN_AF 0
/* ADC 0 channel 4 pin config */
#define ADC_0_CH4 4
#define ADC_0_CH4_PORT 0
#define ADC_0_CH4_PIN 0
#define ADC_0_CH4_PIN_AF 0
/* ADC 0 channel 5 pin config */
#define ADC_0_CH5 5
#define ADC_0_CH5_PORT 0
#define ADC_0_CH5_PIN 0
#define ADC_0_CH5_PIN_AF 0
/* ADC 1 configuration */
#define ADC_1_DEV ADC1
#define ADC_1_CHANNELS 2
#define ADC_1_CLKEN() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 1)
#define ADC_1_CLKDIS() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 0)
#define ADC_1_PORT_CLKEN() /* no PORT pins configured */
#define ADC_1_MODULE_CLOCK SystemBusClock
/* ADC 1 channel 0 pin config */
#define ADC_1_CH0 0 /* DADP0, connected externally to Mulle Vbat/2 on PGA1_DP */
#define ADC_1_CH0_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_1_CH0_PIN 0
#define ADC_1_CH0_PIN_AF 0
/* ADC 1 channel 1 pin config */
#define ADC_1_CH1 19 /* AD19, connected externally to Mulle Vchr/2 on PGA1_DM */
#define ADC_1_CH1_PORT 0 /* this channel is not part of the pin mux on this CPU */
#define ADC_1_CH1_PIN 0
#define ADC_1_CH1_PIN_AF 0
/* ADC 1 channel 2 pin config */
#define ADC_1_CH2 12
#define ADC_1_CH2_PIN 0
#define ADC_1_CH2_PIN_AF 0
#define ADC_1_CH2_PORT 0
/* ADC 1 channel 3 pin config */
#define ADC_1_CH3 13
#define ADC_1_CH3_PIN 0
#define ADC_1_CH3_PIN_AF 0
#define ADC_1_CH3_PORT 0
/* ADC 1 channel 4 pin config */
#define ADC_1_CH4 14
#define ADC_1_CH4_PIN 0
#define ADC_1_CH4_PIN_AF 0
#define ADC_1_CH4_PORT 0
/* ADC 1 channel 5 pin config */
#define ADC_1_CH5 15
#define ADC_1_CH5_PIN 0
#define ADC_1_CH5_PIN_AF 0
#define ADC_1_CH5_PORT 0
/** @} */
/**
* @name PWM configuration
* @{
*/
#define PWM_NUMOF (0U)
#define PWM_0_EN 1
#define PWM_1_EN 1
#define PWM_MAX_CHANNELS 4
/** @} */
/**
* @name SPI configuration
* @{
*/
#define SPI_NUMOF 3
#define SPI_0_EN 1
#define SPI_1_EN 1
#define SPI_2_EN 1
#define SPI_3_EN 0
#define SPI_4_EN 0
#define SPI_5_EN 0
#define SPI_6_EN 0
#define SPI_7_EN 0
#define MULLE_PASTE_PARTS(left, index, right) MULLE_PASTE_PARTS2(left, index, right)
#define MULLE_PASTE_PARTS2(left, index, right) left##index##right
/* SPI 0 device config */
/* SPI_0 (in RIOT) is mapped to SPI0, CTAS=0 in hardware */
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
#define SPI_0_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO 1
#define SPI_0_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
#define SPI_0_SCK_PIN 1
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_AF 2
#define SPI_0_SIN_PORT PORTD
#define SPI_0_SIN_PIN 3
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_AF 2
#define SPI_0_SOUT_PORT PORTD
#define SPI_0_SOUT_PIN 2
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_AF 2
#define SPI_0_PCS0_PORT PORTD
#define SPI_0_PCS0_PIN 0
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_0_PCS0_ACTIVE_LOW 1
#define SPI_0_PCS1_ACTIVE_LOW 1
#define SPI_0_PCS2_ACTIVE_LOW 1
#define SPI_0_PCS3_ACTIVE_LOW 1
/* SPI 1 device config */
/* SPI_1 (in RIOT) is mapped to SPI1, CTAS=0 in hardware */
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
#define SPI_1_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO 1
#define SPI_1_FREQ SystemBusClock
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
#define SPI_1_SCK_PIN 2
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_AF 2
#define SPI_1_SIN_PORT PORTE
#define SPI_1_SIN_PIN 3
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_AF 2
#define SPI_1_SOUT_PORT PORTE
#define SPI_1_SOUT_PIN 1
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_AF 2
#define SPI_1_PCS0_PORT PORTE
#define SPI_1_PCS0_PIN 4
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_1_PCS0_ACTIVE_LOW 1
#define SPI_1_PCS1_ACTIVE_LOW 1
#define SPI_1_PCS2_ACTIVE_LOW 1
#define SPI_1_PCS3_ACTIVE_LOW 1
/* SPI 2 device config */
/* SPI_2 (in RIOT) is mapped to SPI0, CTAS=1 in hardware */
#define SPI_2_INDEX 0
#define SPI_2_CTAS 1
#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
#define SPI_2_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO 1
#define SPI_2_FREQ SystemBusClock
/* SPI 2 pin configuration, must be the same as the other RIOT device using this
* hardware module */
#define SPI_2_SCK_PORT PORTD
#define SPI_2_SCK_PIN 1
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_AF 2
#define SPI_2_SIN_PORT PORTD
#define SPI_2_SIN_PIN 3
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_AF 2
#define SPI_2_SOUT_PORT PORTD
#define SPI_2_SOUT_PIN 2
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_AF 2
#define SPI_2_PCS0_PORT PORTD
#define SPI_2_PCS0_PIN 0
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_2_PCS0_ACTIVE_LOW 1
#define SPI_2_PCS1_ACTIVE_LOW 1
#define SPI_2_PCS2_ACTIVE_LOW 1
#define SPI_2_PCS3_ACTIVE_LOW 1
/**
* @name SPI delay timing configuration
* @{ */
/* These values are necessary for communicating with the AT86RF212B when running
* the MCU core at high clock frequencies. */
/* NB: The given values are the reciprocals of the time, in order to compute the
* scalers using only integer math. */
#define SPI_0_TCSC_FREQ (5555555) /* It looks silly, but this is correct. 1/180e-9 */
#define SPI_0_TASC_FREQ (5454545) /* It looks silly, but this is correct. 1/183e-9 */
#define SPI_0_TDT_FREQ (4000000) /* 1/250e-9 */
/* SPI_1 timings */
#define SPI_1_TCSC_FREQ (0)
#define SPI_1_TASC_FREQ (0)
#define SPI_1_TDT_FREQ (0)
/* SPI_2 timings */
#define SPI_2_TCSC_FREQ (0)
#define SPI_2_TASC_FREQ (0)
#define SPI_2_TDT_FREQ (0)
/** @} */
/** @} */
/**
* @name I2C configuration
* @{
*/
#define I2C_NUMOF (1U)
#define I2C_CLK SystemBusClock
#define I2C_0_EN 1
#define I2C_1_EN 0
#define I2C_IRQ_PRIO 1
/**
* @name I2C baud rate configuration
* @{
*/
/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
#define KINETIS_I2C_F_ICR_LOW (0x3D)
#define KINETIS_I2C_F_MULT_LOW (2)
/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
#define KINETIS_I2C_F_MULT_NORMAL (1)
/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
#define KINETIS_I2C_F_ICR_FAST (0x17)
#define KINETIS_I2C_F_MULT_FAST (0)
/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
/** @} */
/* I2C 0 device configuration */
#define I2C_0_DEV I2C0
#define I2C_0_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
#define I2C_0_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
#define I2C_0_IRQ I2C0_IRQn
#define I2C_0_IRQ_HANDLER isr_i2c0
/* I2C 0 pin configuration */
#define I2C_0_PORT PORTB
#define I2C_0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define I2C_0_PIN_AF 2
#define I2C_0_SDA_PIN 1
#define I2C_0_SCL_PIN 2
#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
/** @} */
/**
* @name GPIO configuration
* @{
*/
#define GPIO_NUMOF 26
#define GPIO_0_EN 1
#define GPIO_1_EN 1
#define GPIO_2_EN 1
#define GPIO_3_EN 1
#define GPIO_4_EN 1
#define GPIO_5_EN 1
#define GPIO_6_EN 1
#define GPIO_7_EN 1
#define GPIO_8_EN 1
#define GPIO_9_EN 1
#define GPIO_10_EN 1
#define GPIO_11_EN 1
#define GPIO_12_EN 1
#define GPIO_13_EN 1
#define GPIO_14_EN 1
#define GPIO_15_EN 1
#define GPIO_16_EN 1
#define GPIO_17_EN 1
#define GPIO_18_EN 1
#define GPIO_19_EN 1
#define GPIO_20_EN 1
#define GPIO_21_EN 1
#define GPIO_22_EN 1
#define GPIO_23_EN 1
#define GPIO_24_EN 1
#define GPIO_25_EN 1
#define GPIO_IRQ_PRIO 1
/* GPIO channel 0 config */
/* Red LED */
#define GPIO_0_PORT PORTC
#define GPIO_0_PORT_BASE PORTC_BASE
#define GPIO_0_DEV PTC
#define GPIO_0_PIN 15
#define GPIO_0_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_0_IRQ PORTC_IRQn
#define GPIO_0_ISR isr_portc_pin_detect
/* GPIO channel 1 config */
/* Yellow LED */
#define GPIO_1_PORT PORTC
#define GPIO_1_PORT_BASE PORTC_BASE
#define GPIO_1_DEV PTC
#define GPIO_1_PIN 14
#define GPIO_1_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_1_IRQ PORTC_IRQn
#define GPIO_1_ISR isr_portc_pin_detect
/* GPIO channel 2 config */
/* Green LED */
#define GPIO_2_PORT PORTC
#define GPIO_2_PORT_BASE PORTC_BASE
#define GPIO_2_DEV PTC
#define GPIO_2_PIN 13
#define GPIO_2_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_2_IRQ PORTC_IRQn
#define GPIO_2_ISR isr_portc_pin_detect
/* GPIO channel 3 config */
/* LIS3DH INT1 */
#define GPIO_3_PORT PORTC
#define GPIO_3_PORT_BASE PORTC_BASE
#define GPIO_3_DEV PTC
#define GPIO_3_PIN 18
#define GPIO_3_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_3_IRQ PORTC_IRQn
#define GPIO_3_ISR isr_portc_pin_detect
/* GPIO channel 4 config */
/* LIS3DH INT2 */
#define GPIO_4_PORT PORTC
#define GPIO_4_PORT_BASE PORTC_BASE
#define GPIO_4_DEV PTC
#define GPIO_4_PIN 17
#define GPIO_4_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_4_IRQ PORTC_IRQn
#define GPIO_4_ISR isr_portc_pin_detect
/* GPIO channel 5 config */
/* VSEC enable */
#define GPIO_5_PORT PORTB
#define GPIO_5_PORT_BASE PORTB_BASE
#define GPIO_5_DEV PTB
#define GPIO_5_PIN 16
#define GPIO_5_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_5_IRQ PORTB_IRQn
#define GPIO_5_ISR isr_portb_pin_detect
/* GPIO channel 6 config */
/* AVDD enable */
#define GPIO_6_PORT PORTB
#define GPIO_6_PORT_BASE PORTB_BASE
#define GPIO_6_DEV PTB
#define GPIO_6_PIN 17
#define GPIO_6_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_6_IRQ PORTB_IRQn
#define GPIO_6_ISR isr_portb_pin_detect
/* GPIO channel 7 config */
/* VPERIPH enable */
#define GPIO_7_PORT PORTD
#define GPIO_7_PORT_BASE PORTD_BASE
#define GPIO_7_DEV PTD
#define GPIO_7_PIN 7
#define GPIO_7_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_7_IRQ PORTD_IRQn
#define GPIO_7_ISR isr_portd_pin_detect
/* GPIO channel 8 config */
/* MC34673 enable */
#define GPIO_8_PORT PORTB
#define GPIO_8_PORT_BASE PORTB_BASE
#define GPIO_8_DEV PTB
#define GPIO_8_PIN 23
#define GPIO_8_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_8_IRQ PORTB_IRQn
#define GPIO_8_ISR isr_portb_pin_detect
/* GPIO channel 9 config */
/* MC34673 CHG */
#define GPIO_9_PORT PORTB
#define GPIO_9_PORT_BASE PORTB_BASE
#define GPIO_9_DEV PTB
#define GPIO_9_PIN 22
#define GPIO_9_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_9_IRQ PORTB_IRQn
#define GPIO_9_ISR isr_portb_pin_detect
/* GPIO channel 10 config */
/* MC34673 PPR */
#define GPIO_10_PORT PORTB
#define GPIO_10_PORT_BASE PORTB_BASE
#define GPIO_10_DEV PTB
#define GPIO_10_PIN 21
#define GPIO_10_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_10_IRQ PORTB_IRQn
#define GPIO_10_ISR isr_portb_pin_detect
/* GPIO channel 11 config */
/* MC34673 FAST */
#define GPIO_11_PORT PORTB
#define GPIO_11_PORT_BASE PORTB_BASE
#define GPIO_11_DEV PTB
#define GPIO_11_PIN 20
#define GPIO_11_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_11_IRQ PORTB_IRQn
#define GPIO_11_ISR isr_portb_pin_detect
/* GPIO channel 12 config */
/* AT86RF212 IRQ */
#define GPIO_12_PORT PORTB
#define GPIO_12_PORT_BASE PORTB_BASE
#define GPIO_12_DEV PTB
#define GPIO_12_PIN 9
#define GPIO_12_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_12_IRQ PORTB_IRQn
#define GPIO_12_ISR isr_portb_pin_detect
/* GPIO channel 13 config */
/* AT86RF212 SLP_TR */
#define GPIO_13_PORT PORTE
#define GPIO_13_PORT_BASE PORTE_BASE
#define GPIO_13_DEV PTE
#define GPIO_13_PIN 6
#define GPIO_13_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_13_IRQ PORTE_IRQn
#define GPIO_13_ISR isr_porte_pin_detect
/* GPIO channel 14 config */
/* AT86RF212 SS */
#define GPIO_14_PORT PORTD
#define GPIO_14_PORT_BASE PORTD_BASE
#define GPIO_14_DEV PTD
#define GPIO_14_PIN 4
#define GPIO_14_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_14_IRQ PORTD_IRQn
#define GPIO_14_ISR isr_portd_pin_detect
/* GPIO channel 15 config */
/* LIS3DH CS */
#define GPIO_15_PORT PORTD
#define GPIO_15_PORT_BASE PORTD_BASE
#define GPIO_15_DEV PTD
#define GPIO_15_PIN 0
#define GPIO_15_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_15_IRQ PORTD_IRQn
#define GPIO_15_ISR isr_portd_pin_detect
/* GPIO channel 16 config */
/* FM25L04B CS */
#define GPIO_16_PORT PORTD
#define GPIO_16_PORT_BASE PORTD_BASE
#define GPIO_16_DEV PTD
#define GPIO_16_PIN 6
#define GPIO_16_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_16_IRQ PORTD_IRQn
#define GPIO_16_ISR isr_portd_pin_detect
/* GPIO channel 17 config */
/* M25P16 CS */
#define GPIO_17_PORT PORTD
#define GPIO_17_PORT_BASE PORTD_BASE
#define GPIO_17_DEV PTD
#define GPIO_17_PIN 5
#define GPIO_17_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_17_IRQ PORTD_IRQn
#define GPIO_17_ISR isr_portd_pin_detect
/* GPIO channel 18 config */
/* General purpose expansion PTB18 */
#define GPIO_18_PORT PORTB
#define GPIO_18_PORT_BASE PORTB_BASE
#define GPIO_18_DEV PTB
#define GPIO_18_PIN 18
#define GPIO_18_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_18_IRQ PORTB_IRQn
#define GPIO_18_ISR isr_portb_pin_detect
/* GPIO channel 19 config */
/* General purpose expansion PTB19 */
#define GPIO_19_PORT PORTB
#define GPIO_19_PORT_BASE PORTB_BASE
#define GPIO_19_DEV PTB
#define GPIO_19_PIN 19
#define GPIO_19_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_19_IRQ PORTB_IRQn
#define GPIO_19_ISR isr_portb_pin_detect
/* GPIO channel 20 config */
/* General purpose expansion PTC0 */
#define GPIO_20_PORT PORTC
#define GPIO_20_PORT_BASE PORTC_BASE
#define GPIO_20_DEV PTC
#define GPIO_20_PIN 0
#define GPIO_20_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_20_IRQ PORTC_IRQn
#define GPIO_20_ISR isr_portc_pin_detect
/* GPIO channel 21 config */
/* General purpose expansion PTC1 */
#define GPIO_21_PORT PORTC
#define GPIO_21_PORT_BASE PORTC_BASE
#define GPIO_21_DEV PTC
#define GPIO_21_PIN 1
#define GPIO_21_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_21_IRQ PORTC_IRQn
#define GPIO_21_ISR isr_portc_pin_detect
/* GPIO channel 22 config */
/* General purpose expansion PTC2 */
#define GPIO_22_PORT PORTC
#define GPIO_22_PORT_BASE PORTC_BASE
#define GPIO_22_DEV PTC
#define GPIO_22_PIN 2
#define GPIO_22_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_22_IRQ PORTC_IRQn
#define GPIO_22_ISR isr_portc_pin_detect
/* GPIO channel 23 config */
/* General purpose expansion PTC5 */
#define GPIO_23_PORT PORTC
#define GPIO_23_PORT_BASE PORTC_BASE
#define GPIO_23_DEV PTC
#define GPIO_23_PIN 5
#define GPIO_23_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_23_IRQ PORTC_IRQn
#define GPIO_23_ISR isr_portc_pin_detect
/* GPIO channel 24 config */
/* General purpose expansion PTC6 */
#define GPIO_24_PORT PORTC
#define GPIO_24_PORT_BASE PORTC_BASE
#define GPIO_24_DEV PTC
#define GPIO_24_PIN 6
#define GPIO_24_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_24_IRQ PORTC_IRQn
#define GPIO_24_ISR isr_portc_pin_detect
/* GPIO channel 25 config */
/* General purpose expansion PTC7 */
#define GPIO_25_PORT PORTC
#define GPIO_25_PORT_BASE PORTC_BASE
#define GPIO_25_DEV PTC
#define GPIO_25_PIN 7
#define GPIO_25_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_25_IRQ PORTC_IRQn
#define GPIO_25_ISR isr_portc_pin_detect
/** @} */
/**
* @name RTC configuration
* @{
*/
/* RIOT RTC implementation uses RTT for underlying timekeeper */
#define RTC_NUMOF (1U)
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_IRQ_PRIO 1
#define RTT_IRQ RTC_IRQn
#define RTT_ISR isr_rtc_alarm
#define RTT_DEV RTC
#define RTT_UNLOCK() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (1) /* in Hz */
/**
* RTC module crystal load capacitance configuration bits.
*/
/* enable 12pF load capacitance, might need adjusting.. */
#define RTT_LOAD_CAP_BITS (RTC_CR_SC8P_MASK | RTC_CR_SC4P_MASK)
/** @} */
/**
* @name Random Number Generator configuration
* @{
*/
#define RANDOM_NUMOF (1U)
#define RANDOM_CLKEN() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
#define RANDOM_CLKDIS() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* MULLE_PERIPH_CONF_H */
/** @} */

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# define the module that is build
MODULE = cpu
# add a list of subdirectories, that should also be build
DIRS = periph $(CORTEX_M4_COMMON) devio $(KINETIS_COMMON)
include $(RIOTBASE)/Makefile.base

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# this CPU implementation is using the explicit core/CPU interface
export CFLAGS += -DCOREIF_NG=1
# export the peripheral drivers to be linked into the final binary
export USEMODULE += periph
# Posix device I/O interface
export USEMODULE += devio
# tell the build system that the CPU depends on the Cortex-M common files
export USEMODULE += cortex-m4_common
# tell the build system that the CPU depends on the Kinetis common files
export USEMODULE += kinetis_common
# define path to cortex-m common module, which is needed for this CPU
export CORTEX_M4_COMMON = $(RIOTCPU)/cortex-m4_common/
# define path to kinetis module, which is needed for this CPU
export KINETIS_COMMON = $(RIOTCPU)/kinetis_common/
# CPU depends on the cortex-m common module, so include it
include $(CORTEX_M4_COMMON)Makefile.include
# CPU depends on the kinetis module, so include it
include $(KINETIS_COMMON)Makefile.include
# define the linker script to use for this CPU
export LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
export LINKERSCRIPT = $(CPU_MODEL).ld
#export the CPU model
MODEL = $(shell echo $(CPU_MODEL)|tr 'a-z' 'A-Z')
export CFLAGS += -DCPU_MODEL_$(MODEL)
# include CPU specific includes
export INCLUDES += -I$(RIOTCPU)/$(CPU)/include
# add the CPU specific system calls implementations for the linker
export UNDEF += $(BINDIR)cpu/syscalls.o
export UNDEF += $(BINDIR)cpu/ssp.o
export UNDEF += $(BINDIR)cpu/interrupt_vector.o

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include <stdint.h>
#include "cpu.h"
#include "board.h"
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Implementation of K60 CPU initialization.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
extern void *_vector_rom[];
/** @brief Current core clock frequency */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/** @brief Current system clock frequency */
uint32_t SystemSysClock = DEFAULT_SYSTEM_CLOCK;
/** @brief Current bus clock frequency */
uint32_t SystemBusClock = DEFAULT_SYSTEM_CLOCK;
/** @brief Current FlexBus clock frequency */
uint32_t SystemFlexBusClock = DEFAULT_SYSTEM_CLOCK;
/** @brief Current flash clock frequency */
uint32_t SystemFlashClock = DEFAULT_SYSTEM_CLOCK;
/** @brief Number of full PIT ticks in one microsecond. */
uint32_t PIT_ticks_per_usec = (DEFAULT_SYSTEM_CLOCK / 1000000ul);
/**
* @brief Check the running CPU identification to find if we are running on the
* wrong hardware.
*/
static void check_running_cpu_revision(void);
/**
* @brief Initialize the CPU, set IRQ priorities
*/
void cpu_init(void)
{
/* Check that we are running on the CPU that this code was built for */
check_running_cpu_revision();
/* configure the vector table location to internal flash */
SCB->VTOR = (uint32_t)_vector_rom;
/* set pendSV interrupt to lowest possible priority */
NVIC_SetPriority(PendSV_IRQn, 0xff);
}
static void check_running_cpu_revision(void)
{
/* Check that the running CPU revision matches the compiled revision */
if (SCB->CPUID != K60_EXPECTED_CPUID) {
uint32_t CPUID = SCB->CPUID; /* This is only to ease debugging, type
* "print /x CPUID" in gdb */
uint32_t SILICON_REVISION = (SCB->CPUID & SCB_CPUID_REVISION_Msk) + 1;
(void)CPUID; /* prevents compiler warnings about an unused variable. */
(void)SILICON_REVISION;
/* Running on the wrong CPU, the clock initialization is different
* between silicon revision 1.x and 2.x (LSB of CPUID) */
/* If you unexpectedly end up on this line when debugging:
* Rebuild the code using the correct value for K60_CPU_REV */
__ASM volatile ("bkpt #99\n");
while (1);
}
}
void SystemCoreClockUpdate(void)
{
/* Variable to store output clock frequency of the MCG module */
uint32_t MCGOUT_clock;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
#if K60_CPU_REV == 1
/* rev.1 silicon */
if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
/* System oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL_CLK_HZ;
}
else {
/* RTC 32 kHz oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL32k_CLK_HZ;
}
#else /* K60_CPU_REV */
/* rev.2 silicon */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
/* System oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL_CLK_HZ;
}
else {
/* RTC 32 kHz oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL32k_CLK_HZ;
}
#endif /* K60_CPU_REV */
uint8_t divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
/* Calculate the divided FLL reference clock */
MCGOUT_clock /= divider;
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
/* If high range is enabled, additional 32 divider is active */
MCGOUT_clock /= 32u;
}
}
else {
/* The slow internal reference clock is selected */
MCGOUT_clock = CPU_INT_SLOW_CLK_HZ;
}
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case (0x0u):
MCGOUT_clock *= 640u;
break;
case (MCG_C4_DRST_DRS(0b01)): /* 0x20u */
MCGOUT_clock *= 1280u;
break;
case (MCG_C4_DRST_DRS(0b10)): /* 0x40u */
MCGOUT_clock *= 1920u;
break;
case (MCG_C4_DRST_DRS(0b11)): /* 0x60u */
MCGOUT_clock *= 2560u;
break;
case (MCG_C4_DMX32_MASK): /* 0x80u */
MCGOUT_clock *= 732u;
break;
case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b01)): /* 0xA0u */
MCGOUT_clock *= 1464u;
break;
case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b10)): /* 0xC0u */
MCGOUT_clock *= 2197u;
break;
case (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0b11)): /* 0xE0u */
MCGOUT_clock *= 2929u;
break;
default:
break;
}
}
else {
/* PLL is selected */
/* Calculate the PLL reference clock */
uint8_t divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUT_clock = (uint32_t)(CPU_XTAL_CLK_HZ / divider);
/* Calculate the MCG output clock */
divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUT_clock *= divider;
}
}
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b01)) { /* 0x40u */
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
/* Slow internal reference clock selected */
MCGOUT_clock = CPU_INT_SLOW_CLK_HZ;
}
else {
/* Fast internal reference clock selected */
#if K60_CPU_REV == 1
/* rev.1 silicon */
MCGOUT_clock = CPU_INT_FAST_CLK_HZ;
#else /* K60_CPU_REV */
/* rev.2 silicon */
MCGOUT_clock = CPU_INT_FAST_CLK_HZ /
(1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
#endif /* K60_CPU_REV */
}
}
else if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0b10)) { /* 0x80u */
/* External reference clock is selected */
#if K60_CPU_REV == 1
/* rev.1 silicon */
if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
/* System oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL_CLK_HZ;
}
else {
/* RTC 32 kHz oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL32k_CLK_HZ;
}
#else /* K60_CPU_REV */
/* rev.2 silicon */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
/* System oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL_CLK_HZ;
}
else {
/* RTC 32 kHz oscillator drives MCG clock */
MCGOUT_clock = CPU_XTAL32k_CLK_HZ;
}
#endif /* K60_CPU_REV */
}
else {
/* Reserved value */
return;
}
/* Core clock and system clock use the same divider setting */
SystemCoreClock = SystemSysClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK)
>> SIM_CLKDIV1_OUTDIV1_SHIFT)));
SystemBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >>
SIM_CLKDIV1_OUTDIV2_SHIFT)));
SystemFlexBusClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >>
SIM_CLKDIV1_OUTDIV3_SHIFT)));
SystemFlashClock = (MCGOUT_clock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >>
SIM_CLKDIV1_OUTDIV4_SHIFT)));
/* Module helper variables */
if (SystemBusClock >= 1000000) {
/* PIT module clock_delay_usec scale factor */
PIT_ticks_per_usec = (SystemBusClock + 500000) / 1000000; /* Rounded to nearest integer */
}
else {
/* less than 1 MHz clock frequency on the PIT module, round up. */
PIT_ticks_per_usec = 1;
}
}
/** @} */

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MODULE = devio
include $(RIOTBASE)/Makefile.base

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device I/O helpers for a no-op device, implementations.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include <reent.h>
#include <errno.h>
#include <string.h>
#include "devio-null.h"
int devnull_open_r(struct _reent *r, const char *path, int flags, int mode)
{
return 0;
}
int devnull_close_r(struct _reent *r, int fd)
{
return 0;
}
long devnull_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
/* Aaand... it's gone!*/
return len;
}
long devnull_read_r(struct _reent *r, int fd, char *ptr, int len)
{
/* Read null bytes */
memset(ptr, '\0', len);
return len;
}
long devnull_lseek_r(struct _reent *r, int fd, int ptr, int dir)
{
r->_errno = ENOSYS;
return -1;
}
long devnull_fstat_r(struct _reent *r, int fd, char *ptr, int len)
{
r->_errno = ENOSYS;
return -1;
}

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device I/O helpers for UARTs on K60, implementation.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include <string.h>
#include "devio-uart.h"
#include "periph/uart.h"
#include "cpu.h"
static inline long uart_write_r(uart_t uart_num, struct _reent *r, int fd, const char *ptr,
int len)
{
int i = 0;
while (i < len) {
uart_write_blocking(uart_num, ptr[i]);
++i;
}
return i;
}
static long uart_read_r(uart_t uart_num, struct _reent *r, int fd, char *ptr, int len)
{
/* not yet implemented */
return 0;
}
#if UART_0_EN
long uart0_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
return uart_write_r(UART_0, r, fd, ptr, len);
}
#endif
#if UART_1_EN
long uart1_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
return uart_write_r(UART_1, r, fd, ptr, len);
}
#endif
#if UART_2_EN
long uart2_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
return uart_write_r(UART_2, r, fd, ptr, len);
}
#endif
#if UART_3_EN
long uart3_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
return uart_write_r(UART_3, r, fd, ptr, len);
}
#endif
#if UART_4_EN
long uart4_write_r(struct _reent *r, int fd, const char *ptr, int len)
{
return uart_write_r(UART_4, r, fd, ptr, len);
}
#endif
#if UART_0_EN
long uart0_read_r(struct _reent *r, int fd, char *ptr, int len)
{
return uart_read_r(UART_0, r, fd, ptr, len);
}
#endif

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Compatibility definitions between MK60D10.h and MK60DZ10.h
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef MK60_COMP_H_
#define MK60_COMP_H_
#ifdef __cplusplus
extern "C"
{
#endif
#if K60_CPU_REV == 1
/* Some compatibility defines to minimize the ifdefs needed for the register
* name changes */
#define SIM_SCGC6_SPI0_MASK SIM_SCGC6_DSPI0_MASK
#define SIM_SCGC6_SPI0_SHIFT SIM_SCGC6_DSPI0_SHIFT
#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
#define MCG_C5_PRDIV0_MASK MCG_C5_PRDIV_MASK
#define MCG_C6_VDIV0_MASK MCG_C6_VDIV_MASK
#define UART_BASES { UART0, UART1, UART2, UART3, UART4, UART5 }
#define LPTMR0_IRQn LPTimer_IRQn
/* Rev 2.x made the OSC32KSEL field into a bitfield (is a single bit in 1.x) */
#define SIM_SOPT1_OSC32KSEL(a) (SIM_SOPT1_OSC32KSEL_MASK)
#endif /* K60_CPU_REV == 1 */
/* Compatibility defines for compatibility with differing module names between
* MK60 and MKW22 headers */
#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
#ifndef OSC0
/* Compatibility definition */
#define OSC0 OSC
#endif
#ifndef MCG_C2_RANGE0
/* Rev 2 parts renamed the parameter RANGE -> RANGE0 */
#define MCG_C2_RANGE0 MCG_C2_RANGE
#endif
#ifdef __cplusplus
}
#endif
#endif /* MK60_COMP_H_ */
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @defgroup cpu_k60 Freescale Kinetis K60
* @ingroup cpu
* @brief CPU specific implementations for the Freescale Kinetis K60
* @{
*
* @file
* @brief Implementation specific CPU configuration options
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef CPU_CONF_H_
#define CPU_CONF_H_
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10)
/* Rev. 2.x silicon */
#define K60_CPU_REV 2
#include "MK60D10.h"
/** The expected CPUID value, can be used to implement a check that we are
* running on the right hardware */
#define K60_EXPECTED_CPUID 0x410fc241u
/* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
#define KINETIS_RNGA (RNG)
#elif defined(CPU_MODEL_K60DN512ZVLL10) || defined(CPU_MODEL_K60DN256ZVLL10)
/* Rev. 1.x silicon */
#define K60_CPU_REV 1
#include "MK60DZ10.h"
/** The expected CPUID value, can be used to implement a check that we are
* running on the right hardware */
#define K60_EXPECTED_CPUID 0x410fc240u
/* K60 rev 1.x has the cryptographically strong RNGB module */
#define KINETIS_RNGB (RNG)
#else
#error Unknown CPU model. Update Makefile.include in the board directory.
#endif
/* Compatibility definitions between the two different Freescale headers */
#include "MK60-comp.h"
/**
* @name GPIO pin mux function numbers
*/
/** @{ */
#define PIN_MUX_FUNCTION_ANALOG 0
#define PIN_MUX_FUNCTION_GPIO 1
/** @} */
/**
* @name GPIO interrupt flank settings
*/
/** @{ */
#define PIN_INTERRUPT_RISING 0b1001
#define PIN_INTERRUPT_FALLING 0b1010
#define PIN_INTERRUPT_EDGE 0b1011
/** @} */
/**
* @name Kernel stack size configuration
*
* TODO: Tune this
* @{
*/
#define KERNEL_CONF_STACKSIZE_PRINTF (1024)
#ifndef KERNEL_CONF_STACKSIZE_DEFAULT
#define KERNEL_CONF_STACKSIZE_DEFAULT (1024)
#endif
#define KERNEL_CONF_STACKSIZE_IDLE (256)
/** @} */
/**
* @name Length and address for reading CPU_ID (named UID in Freescale documents)
* @{
*/
#define CPUID_ID_LEN (16)
#define CPUID_ID_PTR ((void *)(&(SIM->UIDH)))
/** @} */
#ifndef UART0_BUFSIZE
/**
* @brief UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
*/
#define UART0_BUFSIZE (128)
#endif
/**
* @name UART driver settings
*/
/** @{ */
/** UART typedef from CPU header. */
#define KINETIS_UART UART_Type
/** @} */
/**
* @name Clock settings for the LPTMR0 timer
* @{
*/
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
#define LPTIMER_CLKSRC_OSCERCLK 3 /**< system oscillator output, clock from RF-Part */
#ifndef LPTIMER_CLKSRC
#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K /**< default clock source */
#endif
#if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
#define LPTIMER_CLK_PRESCALE 1
#define LPTIMER_SPEED 1000000
#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK)
#define LPTIMER_CLK_PRESCALE 1
#define LPTIMER_SPEED 1000000
#elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K)
#define LPTIMER_CLK_PRESCALE 0
#define LPTIMER_SPEED 32768
#else
#define LPTIMER_CLK_PRESCALE 0
#define LPTIMER_SPEED 1000
#endif
/** IRQ priority for hwtimer interrupts */
#define LPTIMER_IRQ_PRIO 1
/** IRQ channel for hwtimer interrupts */
#define LPTIMER_IRQ_CHAN LPTMR0_IRQn
#if K60_CPU_REV == 1
/*
* The CNR register latching in LPTMR0 was added in silicon rev 2.x. With
* rev 1.x we do not need to do anything in order to read the current timer counter
* value
*/
#define LPTIMER_CNR_NEEDS_LATCHING 0
#elif K60_CPU_REV == 2
#define LPTIMER_CNR_NEEDS_LATCHING 1
#endif
/** @} */
/**
* @name Power mode hardware details
*/
/** @{ */
#if K60_CPU_REV == 1
#define KINETIS_PMCTRL MC->PMCTRL
#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = MC_PMCTRL_LPLLSM(x) | MC_PMCTRL_LPWUI_MASK)
/* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
/* Note: This register can only be written once after each reset, so we must
* enable all power modes that we wish to use. */
#define KINETIS_UNLOCK_PMPROT() (MC->PMPROT |= MC_PMPROT_ALLS_MASK | MC_PMPROT_AVLP_MASK)
#elif K60_CPU_REV == 2
#define KINETIS_PMCTRL SMC->PMCTRL
#define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
#define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
#else
#error Unknown K60 CPU revision!
#endif
/**
* @name STOP mode bitfield values
* @{
*/
/** @brief Normal STOP */
#define KINETIS_POWER_MODE_NORMAL (0b000)
/** @brief VLPS STOP */
#define KINETIS_POWER_MODE_VLPS (0b010)
/** @brief LLS STOP */
#define KINETIS_POWER_MODE_LLS (0b011)
/** @} */
/**
* @brief Wake up source number for the LPTMR0
*
* In order to let the hwtimer wake the CPU from low power modes, we need to
* enable this wake up source.
*/
#define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
/**
* @brief IRQn name to enable LLWU IRQ in NVIC
*/
#define KINETIS_LLWU_IRQ LLW_IRQn
/**
* @brief Enable clock gate on LLWU module.
*/
#define LLWU_UNLOCK() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
/**
* @brief Internal modules whose interrupts are mapped to LLWU wake up sources.
*
* Other modules CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
*/
typedef enum llwu_wakeup_module {
KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
KINETIS_LPM_WAKEUP_MODULE_END,
} llwu_wakeup_module_t;
/**
* @brief enum that maps physical pins to wakeup pin numbers in LLWU module
*
* Other pins CAN NOT be used to wake the CPU from LLS or VLLSx power modes.
*/
typedef enum llwu_wakeup_pin {
KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
KINETIS_LPM_WAKEUP_PIN_END
} llwu_wakeup_pin_t;
/** @} */
/** @name K60 PORT ISR names
* @{ */
#define ISR_PORT_A isr_porta_pin_detect
#define ISR_PORT_B isr_portb_pin_detect
#define ISR_PORT_C isr_portc_pin_detect
#define ISR_PORT_D isr_portd_pin_detect
#define ISR_PORT_E isr_porte_pin_detect
/** @} */
/** @brief Number of packets in transceiver queue */
#define TRANSCEIVER_BUFFER_SIZE (3)
/**
* @name Bit band macros
* @{
*/
/* Generic bitband conversion routine */
/** @brief Convert bit-band region address and bit number to bit-band alias address
*
* @param[in] addr base address in non-bit-banded memory
* @param[in] bit bit number within the word
*
* @return Address of the bit within the bit-band memory region
*/
#define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
/**
* @brief Bitband 32 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
/**
* @brief Bitband 16 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
/**
* @brief Bitband 8 bit access to variable stored in SRAM_U
*
* @note SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
* @note var must be declared 'volatile'
*/
#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
/**
* @brief Bitband 32 bit access to peripheral register
*/
#define BITBAND_PERIPH32(reg, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 16 bit access to peripheral register
*/
#define BITBAND_PERIPH16(reg, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 8 bit access to peripheral register
*/
#define BITBAND_PERIPH8(reg, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H_ */
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device I/O helpers for a no-op device.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef DEVIO_NULL_H_
#define DEVIO_NULL_H_
#ifdef __cplusplus
extern "C"
{
#endif
int devnull_open_r(struct _reent *r, const char *path, int flags, int mode);
int devnull_close_r(struct _reent *r, int fd);
long devnull_write_r(struct _reent *r, int fd, const char *ptr, int len);
long devnull_read_r(struct _reent *r, int fd, char *ptr, int len);
long devnull_lseek_r(struct _reent *r, int fd, int ptr, int dir);
long devnull_fstat_r(struct _reent *r, int fd, char *ptr, int len);
#ifdef __cplusplus
}
#endif
#endif /* !defined(DEVIO_NULL_H_) */
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include <reent.h>
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device I/O helpers for UARTs on K60.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef DEVIO_UART_H_
#define DEVIO_UART_H_
#ifdef __cplusplus
extern "C"
{
#endif
long uart0_write_r(struct _reent *r, int fd, const char *ptr, int len);
long uart1_write_r(struct _reent *r, int fd, const char *ptr, int len);
long uart2_write_r(struct _reent *r, int fd, const char *ptr, int len);
long uart3_write_r(struct _reent *r, int fd, const char *ptr, int len);
long uart4_write_r(struct _reent *r, int fd, const char *ptr, int len);
long uart0_read_r(struct _reent *r, int fd, char *ptr, int len);
#ifdef __cplusplus
}
#endif
#endif /* !defined(DEVIO_UART_H_) */
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include <sys/stat.h>
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#include <reent.h>
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device operations table.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
#ifndef DEVOPTTAB_H_
#define DEVOPTTAB_H_
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @brief Device operations table
*
* Inspired by http://neptune.billgatliff.com/newlib.html
*
* A simple "device operations" table, with function pointers for all the kinds
* of activities you would expect a stream-like device to support.
*/
typedef struct {
const char *name; /**< Device filename */
const int isatty; /**< isatty() return code (usually 0 or 1) */
const int st_mode; /**< st_mode code, see man 2 stat */
int (*open_r)(struct _reent *r, const char *path, int flags,
int mode); /**< pointer to open() function for this device */
int (*close_r)(struct _reent *r, int fd); /**< pointer to close() function for this device */
long(*write_r)(struct _reent *r, int fd, const char *ptr,
int len); /**< pointer to write() function for this device */
long(*read_r)(struct _reent *r, int fd, char *ptr,
int len); /**< pointer to read() function for this device */
long(*lseek_r)(struct _reent *r, int fd, int ptr,
int dir); /**< pointer to lseek() function for this device */
long(*fstat_r)(struct _reent *r, int fd, char *ptr,
int len); /**< pointer to fstat() function for this device */
} devoptab_t;
#ifdef __cplusplus
}
#endif
#endif
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief CPU specific hwtimer configuration options
*
* @author Hauke Petersen <hauke.peterse@fu-berlin.de>
*/
#ifndef HWTIMER_CPU_H_
#define HWTIMER_CPU_H_
#include "cpu.h"
#ifdef __cplusplus
extern "C"
{
#endif
/**
* @name Hardware timer configuration
* @{
*/
#define HWTIMER_MAXTIMERS 1 /**< the HW timer is using the LPTMR as its hardware timer */
#define HWTIMER_SPEED 32768 /**< LPTMR is running at 32.768 kHz */
#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< Virtually extended to 32 bits from 16 bits hardware counter. */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* HWTIMER_CPU_H_ */
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#ifndef SYSTEM_MK60D10_H_
#define SYSTEM_MK60D10_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Device specific configuration file for MK60D10 (header file)
*/
/**
* \brief Current core clock frequency
*
* MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-M4 core.
*/
extern uint32_t SystemCoreClock;
/**
* \brief Current system clock frequency
*
* MCGOUTCLK divided by OUTDIV1 clocks the crossbar switch and bus masters
* directly connected to the crossbar. In addition, this clock is used for UART0
* and UART1.
*/
extern uint32_t SystemSysClock;
/**
* \brief Current bus clock frequency
*
* MCGOUTCLK divided by OUTDIV2 clocks the bus slaves and peripheral (excluding
* memories).
*/
extern uint32_t SystemBusClock;
/**
* \brief Current FlexBus clock frequency
*
* MCGOUTCLK divided by OUTDIV3 clocks the external FlexBus interface.
*/
extern uint32_t SystemFlexBusClock;
/**
* \brief Current flash clock frequency
*
* MCGOUTCLK divided by OUTDIV4 clocks the flash memory.
*/
extern uint32_t SystemFlashClock;
/**
* \brief Updates all of the SystemCoreClock variables.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and
* calculates the current core clock.
*/
void SystemCoreClockUpdate(void);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK60D10_H_) */

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system_MK60D10.h

490
cpu/k60/interrupt_vector.c Normal file
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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
*
* @brief Interrupt vector for K60 MCU.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @note It is not necessary to modify this file to define custom interrupt
* service routines. All symbols are defined weak, it is only necessary to
* define a function with the same name in another file to override the default
* interrupt handlers.
*/
/**
* @name Interrupt vector definition
* @{
*/
#include "cpu.h"
#include "fault_handlers.h"
#include "wdog.h"
extern void *_estack[];
extern void *_sstack[];
typedef void (*ISR_func)(void);
/**
* @brief Unconditional jump to isr_unhandled()
*
* This function is only necessary since we can not declare weak aliases to
* functions outside the translation unit (.c-file). The default isr_unhandled()
* is defined in kinetis_common/fault_handlers.c.
*/
void isr_default_handler(void) __attribute__((naked));
void isr_default_handler(void)
{
__ASM volatile ("b isr_unhandled\n");
}
/**
* @brief Early reset handler used to instrument the stack before it becomes in use.
*
* This function will fill the interrupt context-stack with canary values so
* that it can be checked to measure stack usage, similar to CREATE_STACKTEST in
* @ref thread_create
*/
void pre_reset_handler(void);
/** @brief Interrupt stack canary value
*
* @note 0xe7fe is the ARM Thumb machine code equivalent of asm("bl #-2\n") or
* 'while (1);', i.e. an infinite loop.
*/
#define STACK_CANARY_WORD 0xE7FEE7FEu
void pre_reset_handler(void)
{
/*
* Important: Keep this function as simple as possible, we must not use any
* stack space or we will crash, since we will overwrite all of the stack.
*/
/* Disable watchdog first, it is necessary to do within 256 cycles.
* After this we will completely overwrite the stack so all necessary
* variables must be stored in registers or as immediate values in the
* machine code. */
wdog_disable();
/*
* The register keyword suggests to the compiler to place the variable in a
* register instead of on the stack. Using the register keyword is not a
* guarantee that the variable will be placed in a register. However, this
* function has been verified manually by disassembling the GCC output to
* ensure no stack is being used until after the write loop is finished.
*/
register uint32_t *p;
/* Fill stack space with canary values */
for (p = (uint32_t *)_sstack; p < (uint32_t *)_estack; ++p) {
*p = STACK_CANARY_WORD;
}
/* Now launch the real reset handler. */
__ASM volatile("b reset_handler\n");
/* reset_handler should never return */
while (1);
}
#define ISR_VECTOR_SECTION __attribute__ ((used,section(".vector_table")))
#define UNHANDLED_ALIAS __attribute__((weak, alias("isr_default_handler")));
/* ARM Cortex defined interrupt vectors */
/**
* @brief Default reset handler.
*/
void reset_handler(void) __attribute__((naked));
void isr_nmi(void) UNHANDLED_ALIAS;
void isr_hard_fault(void) UNHANDLED_ALIAS;
void isr_mem_manage(void) UNHANDLED_ALIAS;
void isr_bus_fault(void) UNHANDLED_ALIAS;
void isr_usage_fault(void) UNHANDLED_ALIAS;
void isr_reserved(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
/* void isr_reserved(void) UNHANDLED_ALIAS; */
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_svc(void) UNHANDLED_ALIAS;
void isr_debug_mon(void) UNHANDLED_ALIAS;
/* void _isr_reserved(void) UNHANDLED_ALIAS; */
void isr_pendsv(void) UNHANDLED_ALIAS;
void isr_systick(void) UNHANDLED_ALIAS;
/* device-specific (freescale) defined interrupt vectors */
void isr_dma0_complete(void) UNHANDLED_ALIAS;
void isr_dma1_complete(void) UNHANDLED_ALIAS;
void isr_dma2_complete(void) UNHANDLED_ALIAS;
void isr_dma3_complete(void) UNHANDLED_ALIAS;
void isr_dma4_complete(void) UNHANDLED_ALIAS;
void isr_dma5_complete(void) UNHANDLED_ALIAS;
void isr_dma6_complete(void) UNHANDLED_ALIAS;
void isr_dma7_complete(void) UNHANDLED_ALIAS;
void isr_dma8_complete(void) UNHANDLED_ALIAS;
void isr_dma9_complete(void) UNHANDLED_ALIAS;
void isr_dma10_complete(void) UNHANDLED_ALIAS;
void isr_dma11_complete(void) UNHANDLED_ALIAS;
void isr_dma12_complete(void) UNHANDLED_ALIAS;
void isr_dma13_complete(void) UNHANDLED_ALIAS;
void isr_dma14_complete(void) UNHANDLED_ALIAS;
void isr_dma15_complete(void) UNHANDLED_ALIAS;
void isr_dma_error(void) UNHANDLED_ALIAS;
void isr_mcm(void) UNHANDLED_ALIAS;
void isr_flash_command_complete(void) UNHANDLED_ALIAS;
void isr_flash_read_collision(void) UNHANDLED_ALIAS;
void isr_low_voltage(void) UNHANDLED_ALIAS;
void isr_llwu(void) UNHANDLED_ALIAS;
void isr_watchdog(void) UNHANDLED_ALIAS;
void isr_random_number_generator(void) UNHANDLED_ALIAS;
void isr_i2c0(void) UNHANDLED_ALIAS;
void isr_i2c1(void) UNHANDLED_ALIAS;
void isr_spi0(void) UNHANDLED_ALIAS;
void isr_spi1(void) UNHANDLED_ALIAS;
void isr_spi2(void) UNHANDLED_ALIAS;
void isr_can0_ored_msg_buffer(void) UNHANDLED_ALIAS;
void isr_can0_bus_off(void) UNHANDLED_ALIAS;
void isr_can0_error(void) UNHANDLED_ALIAS;
void isr_can0_tx_warn(void) UNHANDLED_ALIAS;
void isr_can0_rx_warn(void) UNHANDLED_ALIAS;
void isr_can0_wake_up(void) UNHANDLED_ALIAS;
void isr_i2s0_tx(void) UNHANDLED_ALIAS;
void isr_i2s0_rx(void) UNHANDLED_ALIAS;
void isr_can1_ored_msg_buffer(void) UNHANDLED_ALIAS;
void isr_can1_bus_off(void) UNHANDLED_ALIAS;
void isr_can1_error(void) UNHANDLED_ALIAS;
void isr_can1_tx_warn(void) UNHANDLED_ALIAS;
void isr_can1_rx_warn(void) UNHANDLED_ALIAS;
void isr_can1_wake_up(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_uart0_lon(void) UNHANDLED_ALIAS;
void isr_uart0_status(void) UNHANDLED_ALIAS;
void isr_uart0_error(void) UNHANDLED_ALIAS;
void isr_uart1_status(void) UNHANDLED_ALIAS;
void isr_uart1_error(void) UNHANDLED_ALIAS;
void isr_uart2_status(void) UNHANDLED_ALIAS;
void isr_uart2_error(void) UNHANDLED_ALIAS;
void isr_uart3_status(void) UNHANDLED_ALIAS;
void isr_uart3_error(void) UNHANDLED_ALIAS;
void isr_uart4_status(void) UNHANDLED_ALIAS;
void isr_uart4_error(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_adc0(void) UNHANDLED_ALIAS;
void isr_adc1(void) UNHANDLED_ALIAS;
void isr_cmp0(void) UNHANDLED_ALIAS;
void isr_cmp1(void) UNHANDLED_ALIAS;
void isr_cmp2(void) UNHANDLED_ALIAS;
void isr_ftm0(void) UNHANDLED_ALIAS;
void isr_ftm1(void) UNHANDLED_ALIAS;
void isr_ftm2(void) UNHANDLED_ALIAS;
void isr_cmt(void) UNHANDLED_ALIAS;
void isr_rtc_alarm(void) UNHANDLED_ALIAS;
void isr_rtc_seconds(void) UNHANDLED_ALIAS;
void isr_pit0(void) UNHANDLED_ALIAS;
void isr_pit1(void) UNHANDLED_ALIAS;
void isr_pit2(void) UNHANDLED_ALIAS;
void isr_pit3(void) UNHANDLED_ALIAS;
void isr_pdb(void) UNHANDLED_ALIAS;
void isr_usb_otg(void) UNHANDLED_ALIAS;
void isr_usb_charger_detect(void) UNHANDLED_ALIAS;
void isr_enet_1588_timer(void) UNHANDLED_ALIAS;
void isr_enet_tx(void) UNHANDLED_ALIAS;
void isr_enet_rx(void) UNHANDLED_ALIAS;
void isr_enet_error_misc(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_sdhc(void) UNHANDLED_ALIAS;
void isr_dac0(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_tsi(void) UNHANDLED_ALIAS;
void isr_mcg(void) UNHANDLED_ALIAS;
void isr_lptmr0(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_porta_pin_detect(void) UNHANDLED_ALIAS;
void isr_portb_pin_detect(void) UNHANDLED_ALIAS;
void isr_portc_pin_detect(void) UNHANDLED_ALIAS;
void isr_portd_pin_detect(void) UNHANDLED_ALIAS;
void isr_porte_pin_detect(void) UNHANDLED_ALIAS;
/* void isr_reserved(void) UNHANDLED_ALIAS; */
/* void isr_reserved(void) UNHANDLED_ALIAS; */
void isr_software(void) UNHANDLED_ALIAS;
/**
* @brief Interrupt vector definition
*/
const ISR_func isr_vector[256] ISR_VECTOR_SECTION = {
/* ARM Cortex defined interrupt vectors */
(ISR_func)_estack,
pre_reset_handler,
isr_nmi,
isr_hard_fault,
isr_mem_manage,
isr_bus_fault,
isr_usage_fault,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_svc,
isr_debug_mon,
isr_reserved,
isr_pendsv,
isr_systick,
/* Device-specific (Freescale defined) interrupt vectors */
isr_dma0_complete,
isr_dma1_complete,
isr_dma2_complete,
isr_dma3_complete,
isr_dma4_complete,
isr_dma5_complete,
isr_dma6_complete,
isr_dma7_complete,
isr_dma8_complete,
isr_dma9_complete,
isr_dma10_complete,
isr_dma11_complete,
isr_dma12_complete,
isr_dma13_complete,
isr_dma14_complete,
isr_dma15_complete,
isr_dma_error,
isr_mcm,
isr_flash_command_complete,
isr_flash_read_collision,
isr_low_voltage,
isr_llwu,
isr_watchdog,
isr_random_number_generator,
isr_i2c0,
isr_i2c1,
isr_spi0,
isr_spi1,
isr_spi2,
isr_can0_ored_msg_buffer,
isr_can0_bus_off,
isr_can0_error,
isr_can0_tx_warn,
isr_can0_rx_warn,
isr_can0_wake_up,
isr_i2s0_tx,
isr_i2s0_rx,
isr_can1_ored_msg_buffer,
isr_can1_bus_off,
isr_can1_error,
isr_can1_tx_warn,
isr_can1_rx_warn,
isr_can1_wake_up,
isr_reserved,
isr_uart0_lon,
isr_uart0_status,
isr_uart0_error,
isr_uart1_status,
isr_uart1_error,
isr_uart2_status,
isr_uart2_error,
isr_uart3_status,
isr_uart3_error,
isr_uart4_status,
isr_uart4_error,
isr_reserved,
isr_reserved,
isr_adc0,
isr_adc1,
isr_cmp0,
isr_cmp1,
isr_cmp2,
isr_ftm0,
isr_ftm1,
isr_ftm2,
isr_cmt,
isr_rtc_alarm,
isr_rtc_seconds,
isr_pit0,
isr_pit1,
isr_pit2,
isr_pit3,
isr_pdb,
isr_usb_otg,
isr_usb_charger_detect,
isr_enet_1588_timer,
isr_enet_tx,
isr_enet_rx,
isr_enet_error_misc,
isr_reserved,
isr_sdhc,
isr_dac0,
isr_reserved,
isr_tsi,
isr_mcg,
isr_lptmr0,
isr_reserved,
isr_porta_pin_detect,
isr_portb_pin_detect,
isr_portc_pin_detect,
isr_portd_pin_detect,
isr_porte_pin_detect,
isr_reserved,
isr_reserved,
isr_software, /* Vector 110 */
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved,
isr_reserved /* vector 255 */
};
/** @} */
/** @} */

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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
vectors (rx) : ORIGIN = 0x0, LENGTH = 0x400
flashsec (rx) : ORIGIN = 0x400, LENGTH = 0x10
flash (rx) : ORIGIN = 0x410, LENGTH = 256K - 0x410
sram_l (rwx) : ORIGIN = 0x20000000 - 32K, LENGTH = 32K /* Only accessible via code bus. */
sram_u (rwx) : ORIGIN = 0x20000000, LENGTH = 32K /* Only accessible via system bus. */
}
INCLUDE kinetis-base.ld

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cpu/k60/ldscripts/K60DN256ZVLL10.ld Symbolic link
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K60DN256VLL10.ld

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cpu/k60/ldscripts/K60DN512VLL10.ld Normal file
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OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
vectors (rx) : ORIGIN = 0x0, LENGTH = 0x400
flashsec (rx) : ORIGIN = 0x400, LENGTH = 0x10
flash (rx) : ORIGIN = 0x410, LENGTH = 512K - 0x410
sram_l (rwx) : ORIGIN = 0x20000000 - 64K, LENGTH = 64K /* Only accessible via code bus. */
sram_u (rwx) : ORIGIN = 0x20000000, LENGTH = 64K /* Only accessible via system bus. */
}
INCLUDE kinetis-base.ld

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cpu/k60/ldscripts/K60DN512ZVLL10.ld Symbolic link
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K60DN512VLL10.ld

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/*
* Copyright (C) 2014 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Implementation of the kernel's power management interface
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*
* @}
*/
#include "cpu.h"
#include "arch/lpm_arch.h"
static inline void wait(void)
{
/* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead
* of deep sleep.
*/
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
/* WFI instruction will start entry into WAIT mode */
__WFI();
}
void lpm_arch_init(void)
{
/* Stub waiting for https://github.com/RIOT-OS/RIOT/pull/2605 */
}
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
switch (target) {
case LPM_ON:
/* MCU is active, do not go to low power */
break;
case LPM_IDLE:
case LPM_SLEEP:
case LPM_POWERDOWN:
case LPM_OFF:
wait();
break;
case LPM_UNKNOWN:
default:
break;
}
return 0;
}
enum lpm_mode lpm_arch_get(void)
{
/* TODO */
return LPM_ON;
}
void lpm_arch_awake(void)
{
/* TODO */
}
void lpm_arch_begin_awake(void)
{
/* TODO */
}
void lpm_arch_end_awake(void)
{
/* TODO */
}

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MODULE = periph
include $(RIOTBASE)/Makefile.base

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include "cpu.h"
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Implementation of stack smashing protection helper functions used by GCC's -fstack-protector
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
void *__stack_chk_guard = 0;
void __stack_chk_guard_setup(void)
{
unsigned char *p;
p = (unsigned char *) &__stack_chk_guard;
/* TODO: This should be replaced by a random number to use as a canary value */
p[0] = 0;
p[1] = 0;
p[2] = '\n';
p[3] = 255;
}
/*
* Arrange so that the __stack_chk_guard_setup function is called during
* early init.
*/
void __attribute__((section(".preinit_array")))(*preinit__stack_chk_guard_setup[])(void) = {__stack_chk_guard_setup};
/**
* @brief Handler for stack smashing protection failure.
*
* This is called if the SSP checks fail, which means that the stack has been
* corrupted.
*/
void __attribute__((noreturn)) __stack_chk_fail(void)
{
asm volatile ("bkpt #1");
while (1);
}
/** @} */

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/*
* Copyright (C) 2015 Eistec AB
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
#include <unistd.h>
#include <sys/reent.h>
#include <sys/times.h>
#include <string.h>
#include <stdio.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <errno.h>
#include "cpu.h"
#include "board.h"
#include "devopttab.h"
#include "devicemap.h"
#include "thread.h"
#if CFS_ENABLED
#include "cfs.h"
#endif /* CFS_ENABLED */
#include "mutex.h"
#include "ringbuffer.h"
#include "periph/uart.h"
#ifdef MODULE_UART0
#include "board_uart0.h"
#endif
/**
* @ingroup cpu_k60
* @{
*
* @file
* @brief Syscall implementations for K60 CPU.
*
* @author Joakim Gebart <joakim.gebart@eistec.se>
*/
/* Empty environment definition */
char *__env[1] = { 0 };
char **environ = __env;
/* Lock variable used to protect sbrk_r from clobbering the break variable when
* called simultaneously from more than one thread. */
static mutex_t sbrk_mutex = MUTEX_INIT;
/* Align all sbrk arguments to this many bytes */
#define DYNAMIC_MEMORY_ALIGN 4
#ifndef MODULE_UART0
/**
* @brief use mutex for waiting on incoming UART chars
*/
static mutex_t uart_rx_mutex;
static char rx_buf_mem[STDIO_RX_BUFSIZE];
static ringbuffer_t rx_buf;
#endif
/**
* @brief Receive a new character from the UART and put it into the receive buffer
*/
static void stdio_rx_cb(void *arg, char data)
{
#ifndef MODULE_UART0
(void)arg;
ringbuffer_add_one(&rx_buf, data);
mutex_unlock(&uart_rx_mutex);
#else
if (uart0_handler_pid) {
uart0_handle_incoming(data);
uart0_notify_thread();
}
#endif
}
/**
* @brief Initialize NewLib, called by __libc_init_array() from the startup script
*/
void _init(void)
{
#ifndef MODULE_UART0
mutex_init(&uart_rx_mutex);
ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_RX_BUFSIZE);
#endif
uart_init(STDIO, STDIO_BAUDRATE, stdio_rx_cb, 0, 0);
}
/**
* @brief Free resources on NewLib de-initialization, not used for RIOT
*/
void _fini(void)
{
/* nothing to do here */
}
/* ************************ */
/* Process control syscalls */
/* ************************ */
void
_exit(int code)
{
#if DEVELHELP
volatile int status; /* volatile to prevent optimizations to remove the variable from memory */
status = code;
(void)status; /* Suppress compiler warnings about unused variable */
/* See local variable `status` during debugger break. */
asm volatile ("bkpt #0");
#else
NVIC_SystemReset();
#endif
while (1);
}
int
_fork_r(struct _reent *r)
{
/* return "not supported" */
r->_errno = ENOTSUP;
return -1;
}
int
_execve_r(struct _reent *r, const char *name, char *const *argv, char *const *env)
{
/* Not supported */
(void)name; /* Suppress compiler warnings about unused parameters */
(void)argv;
(void)env;
r->_errno = ENOMEM;
return -1;
}
int
_kill_r(struct _reent *r, int pid, int sig)
{
/* Not supported */
(void)pid; /* Suppress compiler warnings about unused parameters */
(void)sig;
r->_errno = EINVAL;
return -1;
}
pid_t
_getpid(void)
{
return sched_active_pid;
}
pid_t
_getpid_r(struct _reent *ptr)
{
(void) ptr;
return sched_active_pid;
}
clock_t
_times_r(struct _reent *r, struct tms *buf)
{
/* Not supported, yet */
(void)buf; /* Suppress compiler warnings about unused parameters */
r->_errno = EACCES;
return -1;
}
int
_wait_r(struct _reent *r, int *status)
{
/* Not supported, yet */
(void)status; /* Suppress compiler warnings about unused parameters */
r->_errno = ECHILD;
return -1;
}
/* ******************************** */
/* File descriptor related syscalls */
/* ******************************** */
/**
* @brief Internal helper for generating FDs
*
* @return An unallocated file descriptor, -1 if no free FD can be found.
*/
static int get_next_dev_fd(void);
static int get_next_dev_fd(void)
{
int fd;
for (fd = 0; fd < MAX_OPEN_DEVICES; ++fd) {
if (devoptab_list[fd] == NULL) {
return fd;
}
}
return -1;
}
int
_open_r(struct _reent *r, const char *name, int flags, int mode)
{
unsigned int i;
int fd;
#if CFS_ENABLED
int cfs_flags = 0;
#endif
/* Search for devices */
for (i = 0; i < devoptab_name_list.len; ++i) {
if (strcmp(devoptab_name_list.data[i].name, name) == 0) {
/* Device found */
fd = get_next_dev_fd();
if (fd < 0) {
/* No free FDs. */
/* ENFILE means too many file descriptors open, system-wide. */
r->_errno = ENFILE;
return -1;
}
/* Set up device operations table and call open method */
devoptab_list[fd] = devoptab_name_list.data[i].devoptab;
/* open_r method is mandatory */
devoptab_list[fd]->open_r(r, name, flags, mode);
return fd;
}
}
#if CFS_ENABLED
/* Not a device name, try searching for files. */
/* Translate POSIX O_* flags to CFS */
if (flags & O_APPEND) {
cfs_flags |= CFS_APPEND;
}
if (flags & O_RDWR) {
cfs_flags |= CFS_READ | CFS_WRITE;
}
if (flags & O_RDONLY) {
cfs_flags |= CFS_READ;
}
if (flags & O_WRONLY) {
cfs_flags |= CFS_WRITE;
}
fd = cfs_open(name, cfs_flags);
if (fd < 0) {
/* Not found or whatever, CFS doesn't tell us why it failed. */
r->_errno = ENOENT;
return -1;
}
fd += MAX_OPEN_DEVICES; /* Remap from CFS FD number */
return fd;
#else
r->_errno = ENOENT;
return -1;
#endif
}
int
_close_r(struct _reent *r, int fd)
{
int ret;
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
#if CFS_ENABLED
/* CFS file */
fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */
cfs_close(fd);
#endif
return 0; /* cfs_close does not indicate failures */
}
if (devoptab_list[fd] == NULL) {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
if (devoptab_list[fd]->close_r == NULL) {
/* Function not implemented */
r->_errno = ENOSYS;
return -1;
}
/* Call method from device operations table */
ret = devoptab_list[fd]->close_r(r, fd);
if (ret == 0) {
/* Successfully closed, clear out device operations table entry to free up
* the file descriptor. */
devoptab_list[fd] = NULL;
}
return ret;
}
ssize_t
_read_r(struct _reent *r, int fd, void *ptr, size_t len)
{
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
#if CFS_ENABLED
int ret;
/* CFS file */
fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */
/* this is not really reentrant */
ret = cfs_read(fd, ptr, len);
if (ret < 0) {
r->_errno = EBADF;
}
return ret;
#else
r->_errno = EBADF;
return -1;
#endif
}
if (devoptab_list[fd] == NULL) {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
if (devoptab_list[fd]->read_r == NULL) {
/* Function not implemented */
r->_errno = ENOSYS;
return -1;
}
/* Call method from device operations table */
return devoptab_list[fd]->read_r(r, fd, ptr, len);
}
ssize_t
_write_r(struct _reent *r, int fd, const void *ptr, size_t len)
{
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
#if CFS_ENABLED
int ret;
/* CFS file */
fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */
/* this is not really reentrant */
ret = cfs_write(fd, (const char *)ptr, len);
if (ret < 0) {
r->_errno = EBADF;
}
return ret;
#else
r->_errno = EBADF;
return -1;
#endif
}
if (devoptab_list[fd] == NULL) {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
if (devoptab_list[fd]->write_r == NULL) {
/* Function not implemented */
r->_errno = ENOSYS;
return -1;
}
/* Call method from device operations table */
return devoptab_list[fd]->write_r(r, fd, ptr, len);
}
off_t
_lseek_r(struct _reent *r, int fd, off_t offset, int whence)
{
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
#if CFS_ENABLED
int ret;
/* CFS file */
fd -= MAX_OPEN_DEVICES; /* Remap to CFS FD number */
/* CFS_SEEK_* macros used by the CFS whence parameter is assumed to
* correspond with POSIX constants */
/* this is not really reentrant */
ret = cfs_seek(fd, offset, whence);
if (ret < 0) {
r->_errno = EBADF;
}
return ret;
#else
r->_errno = EBADF;
return -1;
#endif
}
if (devoptab_list[fd] == NULL) {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
if (devoptab_list[fd]->lseek_r == NULL) {
/* Function not implemented */
r->_errno = ENOSYS;
return -1;
}
/* Call method from device operations table */
return devoptab_list[fd]->lseek_r(r, fd, offset, whence);
}
int
_fstat_r(struct _reent *r, int fd, struct stat *st)
{
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
/* CFS file */
st->st_mode = S_IFREG | S_IRWXU | S_IRWXG | S_IRWXO; /* regular file, 0777 perms (-rwxrwxrwx) */
/** \todo Handle file size with fstat */
/* st->st_uid = 0; */
/* st->st_gid = 0; */
/* st->st_size = 0; */
return 0;
}
if (devoptab_list[fd] != NULL) {
/* Check device operations table to determine mode */
st->st_mode = devoptab_list[fd]->st_mode;
return 0;
}
else {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
}
int
_isatty_r(struct _reent *r, int fd)
{
if (fd < 0) {
/* invalid file descriptor */
r->_errno = EBADF;
return -1;
}
if (fd >= MAX_OPEN_DEVICES) {
/* CFS file, not a TTY */
r->_errno = ENOTTY;
return 0;
}
if (devoptab_list[fd] != NULL) {
/* Check device operations table to determine if it is considered a TTY */
if (devoptab_list[fd]->isatty == 0) {
r->_errno = ENOTTY;
}
return devoptab_list[fd]->isatty;
}
else {
/* nothing mapped on that FD */
r->_errno = EBADF;
return -1;
}
}
/* Compatibility define for newlib built without REENTRANT_SYSCALLS_PROVIDED */
int
_isatty(int fd)
{
/* _REENT is an internal newlib macro, this may cause issues in some situations. */
return _isatty_r(_REENT, fd);
}
/* **************************** */
/* File system related syscalls */
/* **************************** */
int
_stat_r(struct _reent *r, const char *file, struct stat *st)
{
/* not supported, yet */
(void)file; /* Suppress compiler warnings about unused parameters */
(void)st;
r->_errno = ENOENT;
return -1;
}
int
_link_r(struct _reent *r, const char *old, const char *new)
{
/* not supported, yet */
(void)old; /* Suppress compiler warnings about unused parameters */
(void)new;
r->_errno = EMLINK;
return -1;
}
int
_unlink_r(struct _reent *r, const char *name)
{
/* not supported, yet */
(void)name; /* Suppress compiler warnings about unused parameters */
r->_errno = ENOENT;
return -1;
}
/* ********************************** */
/* Memory management related syscalls */
/* ********************************** */
/* Beginning of unallocated RAM, defined by the linker script */
extern int _heap_start;
/* End of RAM area available for allocation */
extern int _heap_end;
/* Current edge of dynamically allocated space */
static void *current_break = (void *)(&_heap_start);
/**
* Move the program break.
*
* This function can increase the size of the allocated memory.
*
* NEVER call this from ISRs (or anything that may call this function, e.g. malloc, free).
*/
void *_sbrk_r(struct _reent *r, ptrdiff_t increment)
{
void *ret;
/* Make sure we have exclusive access to the system break variable. */
mutex_lock(&sbrk_mutex);
/* Align memory increment to nearest DYNAMIC_MEMORY_ALIGN bytes upward */
if (increment % DYNAMIC_MEMORY_ALIGN) {
increment += DYNAMIC_MEMORY_ALIGN - (increment % DYNAMIC_MEMORY_ALIGN);
}
if (((uint8_t *)current_break + increment) < ((uint8_t *)(&_heap_end))) {
ret = current_break;
current_break = (void *)(((uint8_t *)current_break) + increment);
}
else {
r->_errno = ENOMEM;
ret = (void *) - 1;
}
mutex_unlock(&sbrk_mutex);
return ret;
}
/** @} */

1
dist/tools/licenses/patterns/cmsis-pal-freescale-mk60dz10 vendored Normal file
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@ -0,0 +1 @@
Version: rev\. 1\.2, 2011-09-08 Abstract: CMSIS Peripheral Access Layer for MK60DZ10 Copyright: 1997 - 2011 Freescale Semiconductor, Inc\. All Rights Reserved\.

2
doc/doxygen/riot.doxyfile
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@ -826,6 +826,8 @@ EXCLUDE_PATTERNS = */board/*/tools/* \
*/cpu/x86/include/x86_pci.h \ */cpu/x86/include/x86_pci.h \
*/cpu/sam3x8e/include/sam3x8e.h \ */cpu/sam3x8e/include/sam3x8e.h \
*/cpu/stm32l1/include/stm32l1xx.h \ */cpu/stm32l1/include/stm32l1xx.h \
*/cpu/k60/include/MK60D10.h \
*/cpu/k60/include/MK60DZ10.h \
# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names