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kinetis: Fix ADC clock computation

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The ADC prescaler computation was broken and gave too high ADC clock for
module clocks slower than 32 MHz (the >32 MHz case is already handled
separately)
This commit is contained in:
Joakim Nohlgård 2016-12-05 16:58:58 +01:00
parent 364874f7e1
commit c2ccc1bfa0
1 changed files with 5 additions and 5 deletions
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10
cpu/kinetis_common/periph/adc.c
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@ -158,15 +158,15 @@ int adc_init(adc_t line)
* than 12 MHz */ * than 12 MHz */
/* For the calibration it is important that the ADC clock is <= 4 MHz */ /* For the calibration it is important that the ADC clock is <= 4 MHz */
uint32_t adiv; uint32_t adiv;
int i = 4; if (CLOCK_BUSCLOCK > (ADC_MAX_CLK << 3)) {
if (CLOCK_BUSCLOCK > (ADC_MAX_CLK * 8)) {
adiv = ADC_CFG1_ADIV(3) | ADC_CFG1_ADICLK(1); adiv = ADC_CFG1_ADIV(3) | ADC_CFG1_ADICLK(1);
} }
else { else {
while ((i > 0) && (CLOCK_BUSCLOCK < (ADC_MAX_CLK * i))) { unsigned int i = 0;
i--; while ((i < 3) && (CLOCK_BUSCLOCK > (ADC_MAX_CLK << i))) {
++i;
} }
adiv = ADC_CFG1_ADIV(i - 1); adiv = ADC_CFG1_ADIV(i);
} }
/* set configuration register 1: clocking and precision */ /* set configuration register 1: clocking and precision */