cpu/lpc1768: Generalize uart to remove dev_enums

Change uart dev 1 to use UART2 on p9 and p10 since p0 and p1 are not accessable

boards/mbed_lpc1768/include/periph_conf.h

@@ -19,6 +19,8 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -47,42 +49,29 @@ extern "C" {
  * @name    UART configuration
  * @{
  */
-#define UART_NUMOF          (2U)
+static const uart_conf_t uart_config[] = {
-#define UART_0_EN           1
+    {
-#define UART_1_EN           1
+        .dev = (LPC_UART_TypeDef*)LPC_UART0,
+        .irq_rx = UART0_IRQn,
+        .pinsel = 0,
+        .pinsel_shift = 2,
+        .pinsel_af = 1,
+    },
+    {
+        .dev = (LPC_UART_TypeDef*)LPC_UART2,
+        .irq_rx = UART2_IRQn,
+        .pinsel = 0,
+        .pinsel_shift = 20,
+        .pinsel_af = 1,
+    }
+};
+
 #define UART_IRQ_PRIO       1
 
-/* UART 0 device configuration */
-#define UART_0_DEV          LPC_UART0
-#define UART_0_CLKSEL()     (LPC_SC->PCLKSEL0 &= ~(0x3 << 6))       /* PCLK := CCLK / 4 */
-#define UART_0_CLKEN()      (LPC_SC->PCONP |= (1 << 3))
-#define UART_0_CLKDIS()     (LPC_SC->PCONP &= ~(1 << 3))
-#define UART_0_IRQ          UART0_IRQn
 #define UART_0_ISR          isr_uart0
-/* UART 0 pin configuration */
+#define UART_1_ISR          isr_uart2
-#define UART_0_TX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_0_RX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_0_TX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_0_RX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_0_TX_PIN       (3)
-#define UART_0_RX_PIN       (2)
-#define UART_0_AF           (1)
 
-/* UART 1 device configuration */
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
-#define UART_1_DEV          LPC_UART3
-#define UART_1_CLKSEL()     (LPC_SC->PCLKSEL1 &= ~(0x3 << 18))      /* PCLK := CCLK / 4 */
-#define UART_1_CLKEN()      (LPC_SC->PCONP |= (1 << 25))
-#define UART_1_CLKDIS()     (LPC_SC->PCONP &= ~(1 << 25))
-#define UART_1_IRQ          UART3_IRQn
-#define UART_1_ISR          isr_uart3
-/* UART 1 pin configuration */
-#define UART_1_TX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_1_RX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_1_TX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_1_RX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_1_RX_PIN       (0)
-#define UART_1_TX_PIN       (1)
-#define UART_1_AF           (2)
 /** @} */
 
 #ifdef __cplusplus

boards/seeeduino_arch-pro/include/periph_conf.h

@@ -20,6 +20,8 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
+#include "periph_cpu.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -48,42 +50,30 @@ extern "C" {
  * @name    UART configuration
  * @{
  */
-#define UART_NUMOF          (2U)
+static const uart_conf_t uart_config[] = {
-#define UART_0_EN           1
+    {
-#define UART_1_EN           1
+        .dev = (LPC_UART_TypeDef*)LPC_UART0,
+        .irq_rx = UART0_IRQn,
+        .pinsel = 0,
+        .pinsel_shift = 2,
+        .pinsel_af = 1,
+    },
+    {
+        .dev = (LPC_UART_TypeDef*)LPC_UART3,
+        .irq_rx = UART3_IRQn,
+        .pinsel = 0,
+        .pinsel_shift = 0,
+        .pinsel_af = 2
+    }
+};
+
 #define UART_IRQ_PRIO       1
 
-/* UART 0 device configuration */
-#define UART_0_DEV          LPC_UART0
-#define UART_0_CLKSEL()     (LPC_SC->PCLKSEL0 &= ~(0x3 << 6))       /* PCLK := CCLK / 4 */
-#define UART_0_CLKEN()      (LPC_SC->PCONP |= (1 << 3))
-#define UART_0_CLKDIS()     (LPC_SC->PCONP &= ~(1 << 3))
-#define UART_0_IRQ          UART0_IRQn
 #define UART_0_ISR          isr_uart0
-/* UART 0 pin configuration */
-#define UART_0_TX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_0_RX_PINSEL    (LPC_PINCON->PINSEL0)
-#define UART_0_TX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_0_RX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_0_TX_PIN       (3)
-#define UART_0_RX_PIN       (2)
-#define UART_0_AF           (1)
-
-/* UART 1 device configuration */
-#define UART_1_DEV          LPC_UART3
-#define UART_1_CLKSEL()     (LPC_SC->PCLKSEL1 &= ~(0x3 << 18))      /* PCLK := CCLK / 4 */
-#define UART_1_CLKEN()      (LPC_SC->PCONP |= (1 << 25))
-#define UART_1_CLKDIS()     (LPC_SC->PCONP &= ~(1 << 25))
-#define UART_1_IRQ          UART3_IRQn
 #define UART_1_ISR          isr_uart3
-/* UART 1 pin configuration */
+
-#define UART_1_TX_PINSEL    (LPC_PINCON->PINSEL0)
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
-#define UART_1_RX_PINSEL    (LPC_PINCON->PINSEL0)
+
-#define UART_1_TX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_1_RX_PINMODE   (LPC_PINCON->PINMODE0)
-#define UART_1_RX_PIN       (0)
-#define UART_1_TX_PIN       (1)
-#define UART_1_AF           (2)
 /** @} */
 
 #ifdef __cplusplus

cpu/lpc1768/include/periph_cpu.h

@@ -75,6 +75,17 @@ typedef enum {
  */
 #define PM_NUM_MODES    (2U)
 
+/**
+ * @brief   UART device configuration
+ */
+typedef struct {
+    LPC_UART_TypeDef *dev;  /**< pointer to the UART device */
+    uint8_t irq_rx;         /**< RX IRQ number */
+    uint8_t pinsel;         /**< PINSEL# of the RX and TX pin */
+    uint8_t pinsel_shift;   /**< TX/RX bitshift of the PINSEL# register */
+    uint8_t pinsel_af;      /**< Alternate function of the PINSEL# register */
+} uart_conf_t;
+
 #ifdef __cplusplus
 }
 #endif

cpu/lpc1768/periph/uart.c

@@ -24,197 +24,153 @@
 #include "periph/uart.h"
 #include "periph_conf.h"
 
+/* For the clock modules we can take advantage of the offsets in the
+ * register map to find the bitshifting that is needed.
+ */
+#define _DEV_ADDR(uart)     ((uint32_t)(uart_config[uart].dev))
+#define _DEV_OFFSET(uart)   ((_DEV_ADDR(uart) - LPC_APB0_BASE) / 0x4000)
+
 /**
  * @brief UART device configurations
  */
 static uart_isr_ctx_t config[UART_NUMOF];
 
-static int init_base(uart_t uart, uint32_t baudrate);
+static inline void init_base(uart_t uart, uint32_t baudrate);
+
+/**
+ * @brief   Get the GPT register base for a timer
+ *
+ * @param[in] tim   index of the timer
+ *
+ * @return          base address
+ */
+static inline LPC_UART_TypeDef *dev(uart_t uart)
+{
+    assert(uart < UART_NUMOF);
+
+    return ((LPC_UART_TypeDef *)uart_config[uart].dev);
+}
 
 int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
 {
-    int res = init_base(uart, baudrate);
+    assert(uart < UART_NUMOF);
-    if (res != UART_OK) {
+    init_base(uart, baudrate);
-        return res;
-    }
 
     /* save callbacks */
     config[uart].rx_cb = rx_cb;
     config[uart].arg = arg;
 
-    switch (uart) {
+    /* configure and enable global device interrupts */
-#if UART_0_EN
+    NVIC_SetPriority(uart_config[uart].irq_rx, UART_IRQ_PRIO);
-        case UART_0:
+    NVIC_EnableIRQ(uart_config[uart].irq_rx);
-        /* configure and enable global device interrupts */
+    /* enable RX interrupt */
-        NVIC_SetPriority(UART_0_IRQ, UART_IRQ_PRIO);
+    dev(uart)->IER |= (1 << 0);
-        NVIC_EnableIRQ(UART_0_IRQ);
-        /* enable RX interrupt */
-        UART_0_DEV->IER |= (1 << 0);
-            break;
-#endif
-#if UART_1_EN
-        case UART_1:
-        /* configure and enable global device interrupts */
-        NVIC_SetPriority(UART_1_IRQ, UART_IRQ_PRIO);
-        NVIC_EnableIRQ(UART_1_IRQ);
-        /* enable RX interrupt */
-        UART_1_DEV->IER |= (1 << 0);
-            break;
-#endif
-    }
 
     return UART_OK;
 }
 
-static int init_base(uart_t uart, uint32_t baudrate)
+static inline void init_base(uart_t uart, uint32_t baudrate)
 {
-    switch (uart) {
+    /* Fixed baud rate. */
-#if UART_0_EN
+    assert(baudrate == 115200);
-        case UART_0:
+    assert(uart < UART_NUMOF);
-            /* this implementation only supports 115200 baud */
+    (void) baudrate;
-            if (baudrate != 115200) {
+    const uart_conf_t *cfg = &uart_config[uart];
-                return UART_NOBAUD;
+    /* The RX/TX must be together */
-            }
+    assert(cfg->pinsel_shift <= 27);
 
-            /* power on UART device and select peripheral clock */
+    /* power on UART device and select peripheral clock */
-            UART_0_CLKEN();
+    LPC_SC->PCONP |= (1 << _DEV_OFFSET(uart));
-            UART_0_CLKSEL();
+    if (_DEV_OFFSET(uart) >= 16) {
-            /* set mode to 8N1 and enable access to divisor latch */
+        LPC_SC->PCLKSEL1 &= ~(0x3 << ((_DEV_OFFSET(uart) * 2) - 32));
-            UART_0_DEV->LCR = ((0x3 << 0) | (1 << 7));
-            /* set baud rate registers (fixed for now) */
-            UART_0_DEV->DLM = 0;
-            UART_0_DEV->DLL = 13;
-            /* enable FIFOs */
-            UART_0_DEV->FCR = 1;
-            /* select and configure the pin for RX */
-            UART_0_RX_PINSEL &= ~(0x3 << (UART_0_RX_PIN * 2));
-            UART_0_RX_PINSEL |= (UART_0_AF << (UART_0_RX_PIN * 2));
-            UART_0_RX_PINMODE &= ~(0x3 << (UART_0_RX_PIN * 2));
-            UART_0_RX_PINMODE |= (0x2 << (UART_0_RX_PIN * 2));
-            /* select and configure the pin for TX */
-            UART_0_TX_PINSEL &= ~(0x3 << (UART_0_TX_PIN * 2));
-            UART_0_TX_PINSEL |= (UART_0_AF << (UART_0_TX_PIN * 2));
-            UART_0_TX_PINMODE &= ~(0x3 << (UART_0_TX_PIN * 2));
-            UART_0_TX_PINMODE |= (0x2 << (UART_0_TX_PIN * 2));
-            /* disable access to divisor latch */
-            UART_0_DEV->LCR &= ~(1 << 7);
-            break;
-#endif
-#if UART_1_EN
-        case UART_1:
-            /* this implementation only supports 115200 baud */
-            if (baudrate != 115200) {
-                return UART_NOBAUD;
-            }
-
-            /* power on UART device and select peripheral clock */
-            UART_1_CLKEN();
-            UART_1_CLKSEL();
-            /* set mode to 8N1 and enable access to divisor latch */
-            UART_1_DEV->LCR = ((0x3 << 0) | (1 << 7));
-            /* set baud rate registers (fixed for now) */
-            UART_1_DEV->DLM = 0;
-            UART_1_DEV->DLL = 13;
-            /* enable FIFOs */
-            UART_1_DEV->FCR = 1;
-            /* select and configure the pin for RX */
-            UART_1_RX_PINSEL &= ~(0x3 << (UART_1_RX_PIN * 2));
-            UART_1_RX_PINSEL |= (UART_1_AF << (UART_1_RX_PIN * 2));
-            UART_1_RX_PINMODE &= ~(0x3 << (UART_1_RX_PIN * 2));
-            UART_1_RX_PINMODE |= (0x2 << (UART_1_RX_PIN * 2));
-            /* select and configure the pin for TX */
-            UART_1_TX_PINSEL &= ~(0x3 << (UART_1_TX_PIN * 2));
-            UART_1_TX_PINSEL |= (UART_1_AF << (UART_1_TX_PIN * 2));
-            UART_1_TX_PINMODE &= ~(0x3 << (UART_1_TX_PIN * 2));
-            UART_1_TX_PINMODE |= (0x2 << (UART_1_TX_PIN * 2));
-            /* disable access to divisor latch */
-            UART_1_DEV->LCR &= ~(1 << 7);
-            break;
-#endif
-        default:
-            return UART_NODEV;
     }
+    else {
+        LPC_SC->PCLKSEL0 &= ~(0x3 << (_DEV_OFFSET(uart) * 2));
+    }
+    /* set mode to 8N1 and enable access to divisor latch */
+    dev(uart)->LCR = ((0x3 << 0) | (1 << 7));
+    /* set baud rate registers (fixed for now) */
+    dev(uart)->DLM = 0;
+    dev(uart)->DLL = 13;
+    /* enable FIFOs */
+    dev(uart)->FCR = 1;
 
-    return UART_OK;
+    /* Clear register for mux selection */
+    *(&LPC_PINCON->PINSEL0 + cfg->pinsel) &= ~(0xF << (cfg->pinsel_shift));
+    /* Select uart TX mux */
+    *(&LPC_PINCON->PINSEL0 + cfg->pinsel) |=
+            (cfg->pinsel_af << (cfg->pinsel_shift));
+    /* Select uart RX mux */
+    *(&LPC_PINCON->PINSEL0 + cfg->pinsel) |=
+            (cfg->pinsel_af << (cfg->pinsel_shift + 2));
+
+    /* Clear modes for RX and TX pins */
+    *(&LPC_PINCON->PINMODE0 + cfg->pinsel) &= ~(0xF << (cfg->pinsel_shift));
+    /* Set TX mode */
+    *(&LPC_PINCON->PINMODE0 + cfg->pinsel) |= (0x2 << (cfg->pinsel_shift));
+    /* Set RX mode */
+    *(&LPC_PINCON->PINMODE0 + cfg->pinsel) |= (0x2 << (cfg->pinsel_shift + 2));
+
+    /* disable access to divisor latch */
+    dev(uart)->LCR &= ~(1 << 7);
 }
 
 void uart_write(uart_t uart, const uint8_t *data, size_t len)
 {
-    LPC_UART_TypeDef *dev = NULL;
+    assert(uart < UART_NUMOF);
-
+    for (size_t i = 0; i < len; i++) {
-    switch (uart) {
+        /* wait for THRE bit to be set */
-#if UART_0_EN
+        while (!(dev(uart)->LSR & (1 << 5))) {}
-        case UART_0:
+        dev(uart)->THR = data[i];
-            dev = (LPC_UART_TypeDef *)UART_0_DEV;
-            break;
-#endif
-#if UART_1_EN
-        case UART_1:
-            dev = (LPC_UART_TypeDef *)UART_1_DEV;
-            break;
-#endif
-        default:
-            return;
-    }
-
-    if (dev) {
-        for (size_t i = 0; i < len; i++) {
-            while (!(dev->LSR & (1 << 5))) {}  /* wait for THRE bit to be set */
-            dev->THR = data[i];
-        }
     }
 }
 
 void uart_poweron(uart_t uart)
 {
-    switch (uart) {
+    assert(uart < UART_NUMOF);
-#if UART_0_EN
+    LPC_SC->PCONP |= (1 << _DEV_OFFSET(uart));
-        case UART_0:
-            UART_0_CLKEN();
-            break;
-#endif
-#if UART_1_EN
-        case UART_1:
-            UART_1_CLKEN();
-            break;
-#endif
-    }
 }
 
 void uart_poweroff(uart_t uart)
 {
-    switch (uart) {
+    assert(uart < UART_NUMOF);
-#if UART_0_EN
+    LPC_SC->PCONP &= ~(1 << _DEV_OFFSET(uart));
-        case UART_0:
-            UART_0_CLKDIS();
-            break;
-#endif
-#if UART_1_EN
-        case UART_1:
-            UART_1_CLKDIS();
-            break;
-#endif
-    }
 }
 
-#if UART_0_EN
+static void irq_handler(uart_t uart)
+{
+    assert(uart < UART_NUMOF);
+    if (dev(uart)->LSR & (1 << 0)) {
+        uint8_t data = (uint8_t)dev(uart)->RBR;
+        config[uart].rx_cb(config[uart].arg, data);
+    }
+    cortexm_isr_end();
+}
+
+#ifdef UART_0_ISR
 void UART_0_ISR(void)
 {
-    if (UART_0_DEV->LSR & (1 << 0)) {       /* is RDR flag set? */
+    irq_handler(UART_DEV(0));
-        uint8_t data = (uint8_t)UART_0_DEV->RBR;
-        config[UART_0].rx_cb(config[UART_0].arg, data);
-    }
-    cortexm_isr_end();
 }
 #endif
 
-#if UART_1_EN
+#ifdef UART_1_ISR
 void UART_1_ISR(void)
 {
-    if (UART_1_DEV->LSR & (1 << 0)) {       /* is RDR flag set? */
+    irq_handler(UART_DEV(1));
-        uint8_t data = (uint8_t)UART_1_DEV->RBR;
+}
-        config[UART_1].rx_cb(config[UART_1].arg, data);
+#endif
-    }
+
-    cortexm_isr_end();
+#ifdef UART_2_ISR
+void UART_2_ISR(void)
+{
+    irq_handler(UART_DEV(2));
+}
+#endif
+
+#ifdef UART_3_ISR
+void UART_3_ISR(void)
+{
+    irq_handler(UART_DEV(3));
 }
 #endif