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Merge pull request #11749 from aabadie/pr/cpu/stm32f3_flashpage

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cpu/stm32f3: add support for flashpage and flashpage_raw
This commit is contained in:
Francisco 2019-07-01 10:03:40 +02:00 committed by GitHub
commit c3aaf621b5
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3 changed files with 28 additions and 7 deletions
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18
cpu/stm32_common/periph/flashpage.c
View File

@ -77,7 +77,8 @@ static void _erase_page(void *page_addr)
#else #else
uint16_t *dst = page_addr; uint16_t *dst = page_addr;
#endif #endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
uint32_t hsi_state = (RCC->CR & RCC_CR_HSION); uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
/* the internal RC oscillator (HSI) must be enabled */ /* the internal RC oscillator (HSI) must be enabled */
stmclk_enable_hsi(); stmclk_enable_hsi();
@ -113,7 +114,7 @@ static void _erase_page(void *page_addr)
#endif #endif
CNTRL_REG |= (uint32_t)(pn << FLASH_CR_PNB_Pos); CNTRL_REG |= (uint32_t)(pn << FLASH_CR_PNB_Pos);
CNTRL_REG |= FLASH_CR_STRT; CNTRL_REG |= FLASH_CR_STRT;
#else /* CPU_FAM_STM32F0 || CPU_FAM_STM32F1 */ #else /* CPU_FAM_STM32F0 || CPU_FAM_STM32F1 || CPU_FAM_STM32F3 */
DEBUG("[flashpage] erase: setting the page address\n"); DEBUG("[flashpage] erase: setting the page address\n");
FLASH->AR = (uint32_t)dst; FLASH->AR = (uint32_t)dst;
/* trigger the page erase and wait for it to be finished */ /* trigger the page erase and wait for it to be finished */
@ -130,7 +131,8 @@ static void _erase_page(void *page_addr)
/* lock the flash module again */ /* lock the flash module again */
_lock(); _lock();
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
/* restore the HSI state */ /* restore the HSI state */
if (!hsi_state) { if (!hsi_state) {
stmclk_disable_hsi(); stmclk_disable_hsi();
@ -163,7 +165,8 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
const uint16_t *data_addr = data; const uint16_t *data_addr = data;
#endif #endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
uint32_t hsi_state = (RCC->CR & RCC_CR_HSION); uint32_t hsi_state = (RCC->CR & RCC_CR_HSION);
/* the internal RC oscillator (HSI) must be enabled */ /* the internal RC oscillator (HSI) must be enabled */
stmclk_enable_hsi(); stmclk_enable_hsi();
@ -174,7 +177,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
DEBUG("[flashpage_raw] write: now writing the data\n"); DEBUG("[flashpage_raw] write: now writing the data\n");
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32L4) defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
/* set PG bit and program page to flash */ /* set PG bit and program page to flash */
CNTRL_REG |= FLASH_CR_PG; CNTRL_REG |= FLASH_CR_PG;
#endif #endif
@ -187,7 +190,7 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
/* clear program bit again */ /* clear program bit again */
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32L4) defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4)
CNTRL_REG &= ~(FLASH_CR_PG); CNTRL_REG &= ~(FLASH_CR_PG);
#endif #endif
DEBUG("[flashpage_raw] write: done writing data\n"); DEBUG("[flashpage_raw] write: done writing data\n");
@ -195,7 +198,8 @@ void flashpage_write_raw(void *target_addr, const void *data, size_t len)
/* lock the flash module again */ /* lock the flash module again */
_lock(); _lock();
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
defined(CPU_FAM_STM32F3)
/* restore the HSI state */ /* restore the HSI state */
if (!hsi_state) { if (!hsi_state) {
stmclk_disable_hsi(); stmclk_disable_hsi();

3
cpu/stm32f3/Makefile.features
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@ -1 +1,4 @@
FEATURES_PROVIDED += periph_flashpage
FEATURES_PROVIDED += periph_flashpage_raw
-include $(RIOTCPU)/stm32_common/Makefile.features -include $(RIOTCPU)/stm32_common/Makefile.features

14
cpu/stm32f3/include/cpu_conf.h
View File

@ -43,6 +43,20 @@ extern "C" {
#define CPU_FLASH_BASE FLASH_BASE #define CPU_FLASH_BASE FLASH_BASE
/** @} */ /** @} */
/**
* @name Flash page configuration
* @{
*/
#define FLASHPAGE_SIZE (2048U)
#define FLASHPAGE_NUMOF (STM32_FLASHSIZE / FLASHPAGE_SIZE)
/* The minimum block size which can be written is 2B. However, the erase
* block is always FLASHPAGE_SIZE.
*/
#define FLASHPAGE_RAW_BLOCKSIZE (2U)
/* Writing should be always 4 bytes aligned */
#define FLASHPAGE_RAW_ALIGNMENT (4U)
/** @} */
#ifdef __cplusplus #ifdef __cplusplus
} }