From 88d7ecb857ece0e3814e2ef84405bdb84b09afaa Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 13:11:57 +0200 Subject: [PATCH 1/2] boards/stm32f0: introduce shared default clock configuration header --- .../stm32/include/f0/cfg_clock_default.h | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 boards/common/stm32/include/f0/cfg_clock_default.h diff --git a/boards/common/stm32/include/f0/cfg_clock_default.h b/boards/common/stm32/include/f0/cfg_clock_default.h new file mode 100644 index 0000000000..cb46d5b782 --- /dev/null +++ b/boards/common/stm32/include/f0/cfg_clock_default.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2020 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_common_stm32 + * @{ + * + * @file + * @brief Default clock configuration for STM32F0 + * + * @author Hauke Petersen + * @author José Ignacio Alamos + * @author Alexandre Abadie + */ + +#ifndef F0_CFG_CLOCK_DEFAULT_H +#define F0_CFG_CLOCK_DEFAULT_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock settings + * @{ + */ +/* give the target core clock (HCLK) frequency [in Hz], + * maximum: 48MHz */ +#define CLOCK_CORECLOCK MHZ(48) +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#ifndef CLOCK_HSE +#define CLOCK_HSE MHZ(8) +#endif +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#ifndef CLOCK_LSE +#define CLOCK_LSE (0) +#endif +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +#define CLOCK_APB2 (CLOCK_APB1) + +/* PLL factors */ +#ifndef CLOCK_PLL_PREDIV +#define CLOCK_PLL_PREDIV (1) +#endif +#ifndef CLOCK_PLL_MUL +#define CLOCK_PLL_MUL (6) +#endif +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* F0_CFG_CLOCK_DEFAULT_H */ +/** @} */ From 48a8d29c4eff8957a191503b85781b9dae2cebd9 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Sun, 30 Aug 2020 13:12:40 +0200 Subject: [PATCH 2/2] boards/stm32f0: use shared default clock configuration --- boards/nucleo-f030r8/include/periph_conf.h | 32 +++-------------- boards/nucleo-f031k6/include/periph_conf.h | 36 +++++-------------- boards/nucleo-f042k6/include/periph_conf.h | 36 +++++-------------- boards/nucleo-f070rb/include/periph_conf.h | 32 +++-------------- boards/nucleo-f072rb/include/periph_conf.h | 32 +++-------------- boards/nucleo-f091rc/include/periph_conf.h | 32 +++-------------- boards/stm32f030f4-demo/include/periph_conf.h | 29 +-------------- boards/stm32f0discovery/Makefile.include | 3 ++ boards/stm32f0discovery/include/periph_conf.h | 29 +-------------- 9 files changed, 37 insertions(+), 224 deletions(-) diff --git a/boards/nucleo-f030r8/include/periph_conf.h b/boards/nucleo-f030r8/include/periph_conf.h index 4b8fb8119a..bdaec4460a 100644 --- a/boards/nucleo-f030r8/include/periph_conf.h +++ b/boards/nucleo-f030r8/include/periph_conf.h @@ -21,40 +21,16 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ - #define CLOCK_CORECLOCK (48000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (8000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (1) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) - #define CLOCK_APB2 (CLOCK_APB1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (1) - #define CLOCK_PLL_MUL (6) - /** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/nucleo-f031k6/include/periph_conf.h b/boards/nucleo-f031k6/include/periph_conf.h index 7019fcadfb..ec8a57b986 100644 --- a/boards/nucleo-f031k6/include/periph_conf.h +++ b/boards/nucleo-f031k6/include/periph_conf.h @@ -20,41 +20,21 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* No HSE available on this board */ +#define CLOCK_HSE (0U) + +/* Adjust PLL factors when PLL is clocked by HSI */ +#define CLOCK_PLL_PREDIV (2) +#define CLOCK_PLL_MUL (12) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ -#define CLOCK_CORECLOCK (48000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_APB1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (2) -#define CLOCK_PLL_MUL (12) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-f042k6/include/periph_conf.h b/boards/nucleo-f042k6/include/periph_conf.h index b82a2b0d9b..e2c8a47af3 100644 --- a/boards/nucleo-f042k6/include/periph_conf.h +++ b/boards/nucleo-f042k6/include/periph_conf.h @@ -19,41 +19,21 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* No HSE available on this board */ +#define CLOCK_HSE (0U) + +/* Adjust PLL factors when PLL is clocked by HSI */ +#define CLOCK_PLL_PREDIV (2) +#define CLOCK_PLL_MUL (12) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ -#define CLOCK_CORECLOCK (48000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (0U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_APB1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (2) -#define CLOCK_PLL_MUL (12) -/** @} */ - /** * @name UART configuration * @{ diff --git a/boards/nucleo-f070rb/include/periph_conf.h b/boards/nucleo-f070rb/include/periph_conf.h index 6c5bca7fcd..46a226bde1 100644 --- a/boards/nucleo-f070rb/include/periph_conf.h +++ b/boards/nucleo-f070rb/include/periph_conf.h @@ -21,41 +21,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ - #define CLOCK_CORECLOCK (48000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (8000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (1) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) - #define CLOCK_APB2 (CLOCK_APB1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (1) - #define CLOCK_PLL_MUL (6) - /** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/nucleo-f072rb/include/periph_conf.h b/boards/nucleo-f072rb/include/periph_conf.h index 06f58920e4..eb4c6cac0a 100644 --- a/boards/nucleo-f072rb/include/periph_conf.h +++ b/boards/nucleo-f072rb/include/periph_conf.h @@ -20,41 +20,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ - #define CLOCK_CORECLOCK (48000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (8000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (1) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) - #define CLOCK_APB2 (CLOCK_APB1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (1) - #define CLOCK_PLL_MUL (6) - /** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/nucleo-f091rc/include/periph_conf.h b/boards/nucleo-f091rc/include/periph_conf.h index 19b268a997..4819fd29f0 100644 --- a/boards/nucleo-f091rc/include/periph_conf.h +++ b/boards/nucleo-f091rc/include/periph_conf.h @@ -19,41 +19,17 @@ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H +/* This board provides an LSE */ +#define CLOCK_LSE (1) + #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #include "cfg_i2c1_pb8_pb9.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ -#define CLOCK_CORECLOCK (48000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (1) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_APB1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (6) -/** @} */ - /** * @name DMA streams configuration * @{ diff --git a/boards/stm32f030f4-demo/include/periph_conf.h b/boards/stm32f030f4-demo/include/periph_conf.h index 5b7fe9e528..eb12644e4d 100644 --- a/boards/stm32f030f4-demo/include/periph_conf.h +++ b/boards/stm32f030f4-demo/include/periph_conf.h @@ -23,39 +23,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ - #define CLOCK_CORECLOCK (48000000U) - /* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ - #define CLOCK_HSE (8000000U) - /* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ - #define CLOCK_LSE (0) - /* peripheral clock setup */ - #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 - #define CLOCK_AHB (CLOCK_CORECLOCK / 1) - #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ - #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) - #define CLOCK_APB2 (CLOCK_APB1) - - /* PLL factors */ - #define CLOCK_PLL_PREDIV (1) - #define CLOCK_PLL_MUL (6) - /** @} */ - /** * @name Timer configuration * @{ diff --git a/boards/stm32f0discovery/Makefile.include b/boards/stm32f0discovery/Makefile.include index 8458a10af3..4bb429e4f1 100644 --- a/boards/stm32f0discovery/Makefile.include +++ b/boards/stm32f0discovery/Makefile.include @@ -1,3 +1,6 @@ +# we use shared STM32 configuration snippets +INCLUDES += -I$(RIOTBASE)/boards/common/stm32/include + # define the default port depending on the host OS PORT_LINUX ?= /dev/ttyUSB0 PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) diff --git a/boards/stm32f0discovery/include/periph_conf.h b/boards/stm32f0discovery/include/periph_conf.h index ca14edd96e..4a84bc62d1 100644 --- a/boards/stm32f0discovery/include/periph_conf.h +++ b/boards/stm32f0discovery/include/periph_conf.h @@ -20,39 +20,12 @@ #define PERIPH_CONF_H #include "periph_cpu.h" +#include "f0/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif -/** - * @name Clock settings - * - * @note This is auto-generated from - * `cpu/stm32_common/dist/clk_conf/clk_conf.c` - * @{ - */ -/* give the target core clock (HCLK) frequency [in Hz], - * maximum: 48MHz */ -#define CLOCK_CORECLOCK (48000000U) -/* 0: no external high speed crystal available - * else: actual crystal frequency [in Hz] */ -#define CLOCK_HSE (8000000U) -/* 0: no external low speed crystal available, - * 1: external crystal available (always 32.768kHz) */ -#define CLOCK_LSE (0) -/* peripheral clock setup */ -#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 -#define CLOCK_AHB (CLOCK_CORECLOCK / 1) -#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */ -#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) -#define CLOCK_APB2 (CLOCK_APB1) - -/* PLL factors */ -#define CLOCK_PLL_PREDIV (1) -#define CLOCK_PLL_MUL (6) -/** @} */ - /** * @name Timer configuration * @{