cpu, sam0_common: update vendor headers
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43
cpu/sam0_common/include/vendor/README.md
vendored
Normal file
43
cpu/sam0_common/include/vendor/README.md
vendored
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@ -0,0 +1,43 @@
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# CMSIS from Atmel Software Foundation (ASF)
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The include files in the directory tree are copied from ASF (verion 3.35.1).
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The directory tree was copied "as is" from ASF path `sam0/utils/cmsis/` and its
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structure is as follows:
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cmsis
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├── samd21
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│ ├── include
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│ │ ├── component
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│ │ ├── instance
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│ │ └── pio
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│ └── source
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│ ├── gcc
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│ └── iar
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.
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.
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.
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├── samr21
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│ ├── include
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│ │ ├── component
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│ │ ├── instance
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│ │ └── pio
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. └── source
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. ├── gcc
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. └── iar
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However, as only the header files in `include` and its subfolders are required,
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all `source` folders are removed.
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Be aware that if you want to make changes to any file in this tree that the
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changes will be lost when a new ASF release is going to be used.
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# Usage and porting for SAM based CPUs
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SAM based CPU should include `sam0.h` in this directory, which will resolve any
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CPU family specific includes required.
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Currently only SAMD21, SAML21, and SAMR21 based CPUs are supported, i.e., only
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their CMSIS header files are copied from the ASF. If other CPUs are needed copy
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CMSIS files from the ASF for the respective CPU family here and adapt `sam0.h`
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accordingly.
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15
cpu/sam0_common/include/vendor/sam0.h
vendored
15
cpu/sam0_common/include/vendor/sam0.h
vendored
@ -26,6 +26,12 @@
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extern "C" {
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#endif
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/* Workaround redefinition of LITTLE_ENDIAN macro (part1) */
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#ifdef LITTLE_ENDIAN
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#define __TMP_LITTLE_ENDIAN LITTLE_ENDIAN
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#undef LITTLE_ENDIAN
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#endif
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#if defined(CPU_MODEL_SAML21E18A)
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#include "vendor/saml21/include/saml21e18a.h"
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#elif defined(CPU_MODEL_SAML21G18A)
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@ -123,6 +129,15 @@ extern "C" {
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#error "Unsupported SAM0 variant."
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#endif
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/* Workaround redefinition of LITTLE_ENDIAN macro (part2) */
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#ifdef LITTLE_ENDIAN
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#undef LITTLE_ENDIAN
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#endif
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#ifdef __TMP_LITTLE_ENDIAN
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#define LITTLE_ENDIAN __TMP_LITTLE_ENDIAN
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#endif
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#ifdef __cplusplus
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}
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#endif
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46
cpu/sam0_common/include/vendor/samd21/README.md
vendored
46
cpu/sam0_common/include/vendor/samd21/README.md
vendored
@ -1,46 +0,0 @@
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# CMSIS from Atmel Software Foundation (ASF)
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The include files in the directory tree are copied from ASF. See
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https://spaces.atmel.com/gf/project/asf/frs/?action=FrsReleaseBrowse&frs_package_id=4
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(dd. 2016-07-15 ASF version 3.30 was used)
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The directory tree was copied "as is" and its structure is as follows:
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cmsis
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└── samd21
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├── include
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│ ├── component
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│ ├── instance
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│ └── pio
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└── source
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├── gcc
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└── iar
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There is only one include file (per CPU variant) that should be included in
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the source code. For SAMD21 that is cmsis/samd21/include/samd21.h. But
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that will only work if the proper define is set. The define is named after
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the variant, for example `__SAMD21J18A__`. This define must be set in the
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`Makefile.include` of the board.
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Be aware that if you want to make changes to any file in this tree that the
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changes will be lost when a new ASF release is going to be used.
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## Trailing White Space
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Because of the whitespace check (dist/tools/whitespacecheck/check.sh) all
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the trailing white space had to be removed. Please take this into account
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when comparing to the original ASF distribution.
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find include/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
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## LITTLE_ENDIAN
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These include files define `LITTLE_ENDIAN`. But we think this is wrong. It
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seems more logical to let the compiler decide in which mode the ARM code is
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to be translated. In include/machine/endian.h there is already a define of
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`LITTLE_ENDIAN` (and `BIG_ENDIAN`) for a different purpose.
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So, we decided to remove the define from the ASF CMSIS files. The command
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for it (running from this directory) is:
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find include/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +
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@ -3,7 +3,7 @@
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*
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* \brief Component description for AC
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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* Copyright (c) 2016 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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@ -40,9 +40,6 @@
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAMD21_AC_COMPONENT_
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#define _SAMD21_AC_COMPONENT_
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@ -79,7 +76,7 @@ typedef union {
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#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos)
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#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
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#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos)
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#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
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#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos))
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#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
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#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos)
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#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */
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@ -109,7 +106,7 @@ typedef union {
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#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
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#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
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#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos)
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#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
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#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
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#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */
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/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
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@ -146,19 +143,19 @@ typedef union {
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#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
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#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
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#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos)
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#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
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#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
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#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
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#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
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#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
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#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos)
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#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
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#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
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#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
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#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
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#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
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#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
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#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
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#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos)
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#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
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#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
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#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */
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/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
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@ -190,12 +187,12 @@ typedef union {
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#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
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#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
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#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos)
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#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
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#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
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#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
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#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
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#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
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#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos)
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#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
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#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
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#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */
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/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
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@ -227,29 +224,29 @@ typedef union {
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#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
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#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
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#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos)
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#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
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#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
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#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
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#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
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#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
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#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos)
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#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
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#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
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#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */
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/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
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uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
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uint8_t :2; /*!< bit: 2.. 3 Reserved */
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uint8_t WIN0:1; /*!< bit: 4 Window 0 */
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uint8_t :3; /*!< bit: 5.. 7 Reserved */
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__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
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__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
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__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
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__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
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__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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struct {
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uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
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uint8_t :2; /*!< bit: 2.. 3 Reserved */
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uint8_t WIN:1; /*!< bit: 4 Window x */
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uint8_t :3; /*!< bit: 5.. 7 Reserved */
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__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
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__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
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__I uint8_t WIN:1; /*!< bit: 4 Window x */
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__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
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} vec; /*!< Structure used for vec access */
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uint8_t reg; /*!< Type used for register access */
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} AC_INTFLAG_Type;
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@ -264,12 +261,12 @@ typedef union {
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#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
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#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
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#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos)
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#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
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#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
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#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
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#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
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#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
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#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos)
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#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
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#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
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#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */
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/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
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@ -299,10 +296,10 @@ typedef union {
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#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
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#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
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#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos)
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#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
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#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
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#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
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#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos)
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#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
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#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
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#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */
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#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */
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#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */
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@ -337,7 +334,7 @@ typedef union {
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#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
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#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
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#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos)
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#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
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#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
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#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
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#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos)
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#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */
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@ -369,10 +366,10 @@ typedef union {
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#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
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#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
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#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos)
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#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
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#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos))
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#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
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#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos)
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#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
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#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos))
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#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */
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#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */
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#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */
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@ -400,7 +397,7 @@ typedef union {
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#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos)
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#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
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#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos)
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#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
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#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
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#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */
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#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
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#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */
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@ -446,14 +443,14 @@ typedef union {
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#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos)
|
||||
#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
|
||||
#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
|
||||
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
|
||||
#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */
|
||||
#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */
|
||||
#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
|
||||
#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
|
||||
#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
|
||||
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
|
||||
#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
|
||||
#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
|
||||
#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
|
||||
@ -464,7 +461,7 @@ typedef union {
|
||||
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
|
||||
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
|
||||
#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
@ -483,7 +480,7 @@ typedef union {
|
||||
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
|
||||
#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos)
|
||||
#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
|
||||
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
|
||||
#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */
|
||||
#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */
|
||||
@ -496,7 +493,7 @@ typedef union {
|
||||
#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos)
|
||||
#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
|
||||
#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos)
|
||||
#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
|
||||
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
|
||||
#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
|
||||
#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
|
||||
@ -507,7 +504,7 @@ typedef union {
|
||||
#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos)
|
||||
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
|
||||
#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos)
|
||||
#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
|
||||
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
|
||||
#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */
|
||||
#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
|
||||
#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
|
||||
@ -532,7 +529,7 @@ typedef union {
|
||||
|
||||
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
|
||||
#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos)
|
||||
#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
|
||||
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
|
||||
#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */
|
||||
|
||||
/** \brief AC hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for ADC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_COMPONENT_
|
||||
#define _SAMD21_ADC_COMPONENT_
|
||||
@ -97,7 +94,7 @@ typedef union {
|
||||
|
||||
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
|
||||
#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos)
|
||||
#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
|
||||
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
|
||||
#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
|
||||
#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
|
||||
@ -129,7 +126,7 @@ typedef union {
|
||||
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
|
||||
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */
|
||||
#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */
|
||||
@ -154,7 +151,7 @@ typedef union {
|
||||
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
|
||||
#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos)
|
||||
#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
|
||||
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
|
||||
#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
|
||||
@ -173,7 +170,7 @@ typedef union {
|
||||
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
|
||||
#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos)
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
|
||||
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
|
||||
#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */
|
||||
|
||||
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
|
||||
@ -206,7 +203,7 @@ typedef union {
|
||||
#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos)
|
||||
#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
|
||||
#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
|
||||
#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
|
||||
#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */
|
||||
#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */
|
||||
#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */
|
||||
@ -217,7 +214,7 @@ typedef union {
|
||||
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
|
||||
#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
|
||||
#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos)
|
||||
#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
|
||||
#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
|
||||
#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
|
||||
#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
|
||||
@ -252,7 +249,7 @@ typedef union {
|
||||
|
||||
#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
|
||||
#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos)
|
||||
#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
|
||||
#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
|
||||
#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */
|
||||
#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
|
||||
#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
|
||||
@ -308,7 +305,7 @@ typedef union {
|
||||
|
||||
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
|
||||
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
@ -361,7 +358,7 @@ typedef union {
|
||||
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
|
||||
#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
|
||||
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
|
||||
#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
|
||||
@ -384,13 +381,13 @@ typedef union {
|
||||
#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
|
||||
#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
|
||||
#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos)
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
|
||||
#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
|
||||
#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos)
|
||||
#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
|
||||
#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
|
||||
#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */
|
||||
#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */
|
||||
#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */
|
||||
@ -489,13 +486,13 @@ typedef union {
|
||||
|
||||
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
||||
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
||||
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
|
||||
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
|
||||
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} ADC_INTFLAG_Type;
|
||||
@ -547,7 +544,7 @@ typedef union {
|
||||
|
||||
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
|
||||
#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos)
|
||||
#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
|
||||
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
|
||||
#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
|
||||
@ -565,7 +562,7 @@ typedef union {
|
||||
|
||||
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
|
||||
#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos)
|
||||
#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
|
||||
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
|
||||
#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */
|
||||
|
||||
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
|
||||
@ -583,7 +580,7 @@ typedef union {
|
||||
|
||||
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
|
||||
#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos)
|
||||
#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
|
||||
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
|
||||
#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */
|
||||
|
||||
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
|
||||
@ -602,7 +599,7 @@ typedef union {
|
||||
|
||||
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
|
||||
#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos)
|
||||
#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
|
||||
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
|
||||
#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
|
||||
@ -621,7 +618,7 @@ typedef union {
|
||||
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
|
||||
#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos)
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
|
||||
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
|
||||
#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */
|
||||
|
||||
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
|
||||
@ -641,10 +638,10 @@ typedef union {
|
||||
|
||||
#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
|
||||
#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos)
|
||||
#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
|
||||
#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
|
||||
#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
|
||||
#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos)
|
||||
#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
|
||||
#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
|
||||
#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */
|
||||
|
||||
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_COMPONENT_
|
||||
#define _SAMD21_DAC_COMPONENT_
|
||||
@ -111,7 +108,7 @@ typedef union {
|
||||
#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos)
|
||||
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
|
||||
#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
|
||||
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
|
||||
#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */
|
||||
#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */
|
||||
#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */
|
||||
@ -191,12 +188,12 @@ typedef union {
|
||||
|
||||
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTFLAG_Type;
|
||||
@ -246,7 +243,7 @@ typedef union {
|
||||
|
||||
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
|
||||
#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos)
|
||||
#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
|
||||
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
|
||||
#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */
|
||||
|
||||
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
|
||||
@ -264,7 +261,7 @@ typedef union {
|
||||
|
||||
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
|
||||
#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos)
|
||||
#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
|
||||
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
|
||||
#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */
|
||||
|
||||
/** \brief DAC hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for DMAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_COMPONENT_
|
||||
#define _SAMD21_DMAC_COMPONENT_
|
||||
@ -98,7 +95,7 @@ typedef union {
|
||||
#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos)
|
||||
#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */
|
||||
#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos)
|
||||
#define DMAC_CTRL_LVLEN(value) ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
|
||||
#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos))
|
||||
#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
|
||||
@ -120,7 +117,7 @@ typedef union {
|
||||
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos))
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */
|
||||
@ -129,14 +126,14 @@ typedef union {
|
||||
#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos))
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
|
||||
#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */
|
||||
#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos)
|
||||
#define DMAC_CRCCTRL_CRCSRC(value) ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
|
||||
#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos))
|
||||
#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */
|
||||
#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */
|
||||
#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
|
||||
@ -158,7 +155,7 @@ typedef union {
|
||||
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos)
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
|
||||
#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos))
|
||||
#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
|
||||
@ -176,7 +173,7 @@ typedef union {
|
||||
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
|
||||
#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos))
|
||||
#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */
|
||||
|
||||
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
|
||||
@ -236,7 +233,7 @@ typedef union {
|
||||
|
||||
#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */
|
||||
#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos)
|
||||
#define DMAC_QOSCTRL_WRBQOS(value) ((DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos))
|
||||
#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
@ -247,7 +244,7 @@ typedef union {
|
||||
#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos)
|
||||
#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */
|
||||
#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos)
|
||||
#define DMAC_QOSCTRL_FQOS(value) ((DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos))
|
||||
#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
@ -258,7 +255,7 @@ typedef union {
|
||||
#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos)
|
||||
#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */
|
||||
#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos)
|
||||
#define DMAC_QOSCTRL_DQOS(value) ((DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)))
|
||||
#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos))
|
||||
#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */
|
||||
#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */
|
||||
#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */
|
||||
@ -324,7 +321,7 @@ typedef union {
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos)
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
|
||||
#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos))
|
||||
#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */
|
||||
|
||||
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
|
||||
@ -353,22 +350,22 @@ typedef union {
|
||||
|
||||
#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
|
||||
#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos)
|
||||
#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
|
||||
#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos))
|
||||
#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
|
||||
#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos)
|
||||
#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */
|
||||
@ -396,7 +393,7 @@ typedef union {
|
||||
|
||||
#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */
|
||||
#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos)
|
||||
#define DMAC_INTPEND_ID(value) ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
|
||||
#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos))
|
||||
#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */
|
||||
#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos)
|
||||
#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */
|
||||
@ -466,7 +463,7 @@ typedef union {
|
||||
#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
|
||||
#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos)
|
||||
#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
|
||||
#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos))
|
||||
#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */
|
||||
|
||||
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
|
||||
@ -524,7 +521,7 @@ typedef union {
|
||||
#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */
|
||||
#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos)
|
||||
#define DMAC_BUSYCH_BUSYCH(value) ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
|
||||
#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos))
|
||||
#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */
|
||||
|
||||
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
|
||||
@ -582,7 +579,7 @@ typedef union {
|
||||
#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos)
|
||||
#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */
|
||||
#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos)
|
||||
#define DMAC_PENDCH_PENDCH(value) ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
|
||||
#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos))
|
||||
#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */
|
||||
|
||||
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
|
||||
@ -620,15 +617,15 @@ typedef union {
|
||||
#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos)
|
||||
#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
|
||||
#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos)
|
||||
#define DMAC_ACTIVE_LVLEX(value) ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
|
||||
#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos))
|
||||
#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */
|
||||
#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos)
|
||||
#define DMAC_ACTIVE_ID(value) ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
|
||||
#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos))
|
||||
#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */
|
||||
#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos)
|
||||
#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
|
||||
#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos)
|
||||
#define DMAC_ACTIVE_BTCNT(value) ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
|
||||
#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos))
|
||||
#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */
|
||||
|
||||
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
|
||||
@ -646,7 +643,7 @@ typedef union {
|
||||
|
||||
#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
|
||||
#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos)
|
||||
#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
|
||||
#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos))
|
||||
#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
|
||||
@ -664,7 +661,7 @@ typedef union {
|
||||
|
||||
#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
|
||||
#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos)
|
||||
#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
|
||||
#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos))
|
||||
#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
|
||||
@ -683,7 +680,7 @@ typedef union {
|
||||
|
||||
#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */
|
||||
#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos)
|
||||
#define DMAC_CHID_ID(value) ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
|
||||
#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos))
|
||||
#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */
|
||||
|
||||
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
|
||||
@ -731,7 +728,7 @@ typedef union {
|
||||
|
||||
#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */
|
||||
#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos)
|
||||
#define DMAC_CHCTRLB_EVACT(value) ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
|
||||
#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos))
|
||||
#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
|
||||
#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
|
||||
#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
|
||||
@ -752,7 +749,7 @@ typedef union {
|
||||
#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos)
|
||||
#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
|
||||
#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_LVL(value) ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
|
||||
#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos))
|
||||
#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */
|
||||
#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */
|
||||
@ -763,12 +760,12 @@ typedef union {
|
||||
#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
|
||||
#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
|
||||
#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos))
|
||||
#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
|
||||
#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */
|
||||
#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos)
|
||||
#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
|
||||
#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos))
|
||||
#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
|
||||
#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
|
||||
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
|
||||
@ -777,7 +774,7 @@ typedef union {
|
||||
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
|
||||
#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */
|
||||
#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos)
|
||||
#define DMAC_CHCTRLB_CMD(value) ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
|
||||
#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos))
|
||||
#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */
|
||||
#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
|
||||
#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */
|
||||
@ -836,12 +833,12 @@ typedef union {
|
||||
|
||||
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t TERR:1; /*!< bit: 0 Transfer Error */
|
||||
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
|
||||
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
__I uint8_t TERR:1; /*!< bit: 0 Transfer Error */
|
||||
__I uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
|
||||
__I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DMAC_CHINTFLAG_Type;
|
||||
@ -901,12 +898,13 @@ typedef union {
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */
|
||||
#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */
|
||||
|
||||
#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */
|
||||
#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos)
|
||||
#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */
|
||||
#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos)
|
||||
#define DMAC_BTCTRL_EVOSEL(value) ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
|
||||
#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos))
|
||||
#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */
|
||||
#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
|
||||
#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
|
||||
@ -915,7 +913,7 @@ typedef union {
|
||||
#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos)
|
||||
#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */
|
||||
#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos)
|
||||
#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
|
||||
#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos))
|
||||
#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */
|
||||
#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
|
||||
#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
|
||||
@ -926,7 +924,7 @@ typedef union {
|
||||
#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
|
||||
#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */
|
||||
#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos)
|
||||
#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
|
||||
#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos))
|
||||
#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */
|
||||
#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */
|
||||
#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */
|
||||
@ -945,15 +943,15 @@ typedef union {
|
||||
#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
|
||||
#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
|
||||
#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */
|
||||
#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos))
|
||||
#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 1 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X2_Val 0x1ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 2 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X4_Val 0x2ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 4 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X8_Val 0x3ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 8 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X16_Val 0x4ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 16 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X32_Val 0x5ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 32 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X64_Val 0x6ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 64 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X128_Val 0x7ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<<BEATSIZE) * 128 */
|
||||
#define DMAC_BTCTRL_STEPSIZE_X1 (DMAC_BTCTRL_STEPSIZE_X1_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE_X2 (DMAC_BTCTRL_STEPSIZE_X2_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
||||
#define DMAC_BTCTRL_STEPSIZE_X4 (DMAC_BTCTRL_STEPSIZE_X4_Val << DMAC_BTCTRL_STEPSIZE_Pos)
|
||||
@ -978,7 +976,7 @@ typedef union {
|
||||
|
||||
#define DMAC_BTCNT_BTCNT_Pos 0 /**< \brief (DMAC_BTCNT) Block Transfer Count */
|
||||
#define DMAC_BTCNT_BTCNT_Msk (0xFFFFul << DMAC_BTCNT_BTCNT_Pos)
|
||||
#define DMAC_BTCNT_BTCNT(value) ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
|
||||
#define DMAC_BTCNT_BTCNT(value) (DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos))
|
||||
#define DMAC_BTCNT_MASK 0xFFFFul /**< \brief (DMAC_BTCNT) MASK Register */
|
||||
|
||||
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
|
||||
@ -995,7 +993,7 @@ typedef union {
|
||||
|
||||
#define DMAC_SRCADDR_SRCADDR_Pos 0 /**< \brief (DMAC_SRCADDR) Transfer Source Address */
|
||||
#define DMAC_SRCADDR_SRCADDR_Msk (0xFFFFFFFFul << DMAC_SRCADDR_SRCADDR_Pos)
|
||||
#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
|
||||
#define DMAC_SRCADDR_SRCADDR(value) (DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos))
|
||||
#define DMAC_SRCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_SRCADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
|
||||
@ -1012,7 +1010,7 @@ typedef union {
|
||||
|
||||
#define DMAC_DSTADDR_DSTADDR_Pos 0 /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
|
||||
#define DMAC_DSTADDR_DSTADDR_Msk (0xFFFFFFFFul << DMAC_DSTADDR_DSTADDR_Pos)
|
||||
#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
|
||||
#define DMAC_DSTADDR_DSTADDR(value) (DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos))
|
||||
#define DMAC_DSTADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DSTADDR) MASK Register */
|
||||
|
||||
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
|
||||
@ -1029,7 +1027,7 @@ typedef union {
|
||||
|
||||
#define DMAC_DESCADDR_DESCADDR_Pos 0 /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
|
||||
#define DMAC_DESCADDR_DESCADDR_Msk (0xFFFFFFFFul << DMAC_DESCADDR_DESCADDR_Pos)
|
||||
#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
|
||||
#define DMAC_DESCADDR_DESCADDR(value) (DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos))
|
||||
#define DMAC_DESCADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_DESCADDR) MASK Register */
|
||||
|
||||
/** \brief DMAC APB hardware registers */
|
||||
@ -1081,6 +1079,7 @@ typedef struct {
|
||||
#endif
|
||||
;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SECTION_DMAC_DESCRIPTOR
|
||||
|
||||
/*@}*/
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for DSU
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_COMPONENT_
|
||||
#define _SAMD21_DSU_COMPONENT_
|
||||
@ -54,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define DSU_U2209
|
||||
#define REV_DSU 0x202
|
||||
#define REV_DSU 0x203
|
||||
|
||||
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -147,7 +144,7 @@ typedef union {
|
||||
#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
|
||||
#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
|
||||
#define DSU_STATUSB_DCCD_Msk (0x3ul << DSU_STATUSB_DCCD_Pos)
|
||||
#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
|
||||
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
|
||||
#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
|
||||
#define DSU_STATUSB_HPE (0x1ul << DSU_STATUSB_HPE_Pos)
|
||||
#define DSU_STATUSB_MASK 0x1Ful /**< \brief (DSU_STATUSB) MASK Register */
|
||||
@ -168,7 +165,7 @@ typedef union {
|
||||
|
||||
#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
|
||||
#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFul << DSU_ADDR_ADDR_Pos)
|
||||
#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
|
||||
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
|
||||
#define DSU_ADDR_MASK 0xFFFFFFFCul /**< \brief (DSU_ADDR) MASK Register */
|
||||
|
||||
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
|
||||
@ -187,7 +184,7 @@ typedef union {
|
||||
|
||||
#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
|
||||
#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFul << DSU_LENGTH_LENGTH_Pos)
|
||||
#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
|
||||
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
|
||||
#define DSU_LENGTH_MASK 0xFFFFFFFCul /**< \brief (DSU_LENGTH) MASK Register */
|
||||
|
||||
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
|
||||
@ -205,7 +202,7 @@ typedef union {
|
||||
|
||||
#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
|
||||
#define DSU_DATA_DATA_Msk (0xFFFFFFFFul << DSU_DATA_DATA_Pos)
|
||||
#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
|
||||
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
|
||||
#define DSU_DATA_MASK 0xFFFFFFFFul /**< \brief (DSU_DATA) MASK Register */
|
||||
|
||||
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
|
||||
@ -223,7 +220,7 @@ typedef union {
|
||||
|
||||
#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
|
||||
#define DSU_DCC_DATA_Msk (0xFFFFFFFFul << DSU_DCC_DATA_Pos)
|
||||
#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
|
||||
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
|
||||
#define DSU_DCC_MASK 0xFFFFFFFFul /**< \brief (DSU_DCC) MASK Register */
|
||||
|
||||
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
|
||||
@ -246,22 +243,22 @@ typedef union {
|
||||
|
||||
#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
|
||||
#define DSU_DID_DEVSEL_Msk (0xFFul << DSU_DID_DEVSEL_Pos)
|
||||
#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
|
||||
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
|
||||
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
|
||||
#define DSU_DID_REVISION_Msk (0xFul << DSU_DID_REVISION_Pos)
|
||||
#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
|
||||
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
|
||||
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
|
||||
#define DSU_DID_DIE_Msk (0xFul << DSU_DID_DIE_Pos)
|
||||
#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
|
||||
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
|
||||
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
|
||||
#define DSU_DID_SERIES_Msk (0x3Ful << DSU_DID_SERIES_Pos)
|
||||
#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
|
||||
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
|
||||
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
|
||||
#define DSU_DID_FAMILY_Msk (0x1Ful << DSU_DID_FAMILY_Pos)
|
||||
#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
|
||||
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
|
||||
#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
|
||||
#define DSU_DID_PROCESSOR_Msk (0xFul << DSU_DID_PROCESSOR_Pos)
|
||||
#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
|
||||
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
|
||||
#define DSU_DID_MASK 0xFFBFFFFFul /**< \brief (DSU_DID) MASK Register */
|
||||
|
||||
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
|
||||
@ -286,7 +283,7 @@ typedef union {
|
||||
#define DSU_ENTRY_FMT (0x1ul << DSU_ENTRY_FMT_Pos)
|
||||
#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
|
||||
#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFul << DSU_ENTRY_ADDOFF_Pos)
|
||||
#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
|
||||
#define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos))
|
||||
#define DSU_ENTRY_MASK 0xFFFFF003ul /**< \brief (DSU_ENTRY) MASK Register */
|
||||
|
||||
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
|
||||
@ -304,7 +301,7 @@ typedef union {
|
||||
|
||||
#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
|
||||
#define DSU_END_END_Msk (0xFFFFFFFFul << DSU_END_END_Pos)
|
||||
#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
|
||||
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
|
||||
#define DSU_END_MASK 0xFFFFFFFFul /**< \brief (DSU_END) MASK Register */
|
||||
|
||||
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
|
||||
@ -342,10 +339,10 @@ typedef union {
|
||||
|
||||
#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
|
||||
#define DSU_PID4_JEPCC_Msk (0xFul << DSU_PID4_JEPCC_Pos)
|
||||
#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
|
||||
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
|
||||
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
|
||||
#define DSU_PID4_FKBC_Msk (0xFul << DSU_PID4_FKBC_Pos)
|
||||
#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
|
||||
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
|
||||
#define DSU_PID4_MASK 0x000000FFul /**< \brief (DSU_PID4) MASK Register */
|
||||
|
||||
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
|
||||
@ -364,7 +361,7 @@ typedef union {
|
||||
|
||||
#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
|
||||
#define DSU_PID0_PARTNBL_Msk (0xFFul << DSU_PID0_PARTNBL_Pos)
|
||||
#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
|
||||
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
|
||||
#define DSU_PID0_MASK 0x000000FFul /**< \brief (DSU_PID0) MASK Register */
|
||||
|
||||
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
|
||||
@ -384,10 +381,10 @@ typedef union {
|
||||
|
||||
#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
|
||||
#define DSU_PID1_PARTNBH_Msk (0xFul << DSU_PID1_PARTNBH_Pos)
|
||||
#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
|
||||
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
|
||||
#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
|
||||
#define DSU_PID1_JEPIDCL_Msk (0xFul << DSU_PID1_JEPIDCL_Pos)
|
||||
#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
|
||||
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
|
||||
#define DSU_PID1_MASK 0x000000FFul /**< \brief (DSU_PID1) MASK Register */
|
||||
|
||||
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
|
||||
@ -408,12 +405,12 @@ typedef union {
|
||||
|
||||
#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
|
||||
#define DSU_PID2_JEPIDCH_Msk (0x7ul << DSU_PID2_JEPIDCH_Pos)
|
||||
#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
|
||||
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
|
||||
#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
|
||||
#define DSU_PID2_JEPU (0x1ul << DSU_PID2_JEPU_Pos)
|
||||
#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
|
||||
#define DSU_PID2_REVISION_Msk (0xFul << DSU_PID2_REVISION_Pos)
|
||||
#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
|
||||
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
|
||||
#define DSU_PID2_MASK 0x000000FFul /**< \brief (DSU_PID2) MASK Register */
|
||||
|
||||
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
|
||||
@ -433,10 +430,10 @@ typedef union {
|
||||
|
||||
#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
|
||||
#define DSU_PID3_CUSMOD_Msk (0xFul << DSU_PID3_CUSMOD_Pos)
|
||||
#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
|
||||
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
|
||||
#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
|
||||
#define DSU_PID3_REVAND_Msk (0xFul << DSU_PID3_REVAND_Pos)
|
||||
#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
|
||||
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
|
||||
#define DSU_PID3_MASK 0x000000FFul /**< \brief (DSU_PID3) MASK Register */
|
||||
|
||||
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
|
||||
@ -455,7 +452,7 @@ typedef union {
|
||||
|
||||
#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
|
||||
#define DSU_CID0_PREAMBLEB0_Msk (0xFFul << DSU_CID0_PREAMBLEB0_Pos)
|
||||
#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
|
||||
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
|
||||
#define DSU_CID0_MASK 0x000000FFul /**< \brief (DSU_CID0) MASK Register */
|
||||
|
||||
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
|
||||
@ -475,10 +472,10 @@ typedef union {
|
||||
|
||||
#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
|
||||
#define DSU_CID1_PREAMBLE_Msk (0xFul << DSU_CID1_PREAMBLE_Pos)
|
||||
#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
|
||||
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
|
||||
#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
|
||||
#define DSU_CID1_CCLASS_Msk (0xFul << DSU_CID1_CCLASS_Pos)
|
||||
#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
|
||||
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
|
||||
#define DSU_CID1_MASK 0x000000FFul /**< \brief (DSU_CID1) MASK Register */
|
||||
|
||||
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
|
||||
@ -497,7 +494,7 @@ typedef union {
|
||||
|
||||
#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
|
||||
#define DSU_CID2_PREAMBLEB2_Msk (0xFFul << DSU_CID2_PREAMBLEB2_Pos)
|
||||
#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
|
||||
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
|
||||
#define DSU_CID2_MASK 0x000000FFul /**< \brief (DSU_CID2) MASK Register */
|
||||
|
||||
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
|
||||
@ -516,7 +513,7 @@ typedef union {
|
||||
|
||||
#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
|
||||
#define DSU_CID3_PREAMBLEB3_Msk (0xFFul << DSU_CID3_PREAMBLEB3_Pos)
|
||||
#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
|
||||
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
|
||||
#define DSU_CID3_MASK 0x000000FFul /**< \brief (DSU_CID3) MASK Register */
|
||||
|
||||
/** \brief DSU hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for EIC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_COMPONENT_
|
||||
#define _SAMD21_EIC_COMPONENT_
|
||||
@ -112,7 +109,7 @@ typedef union {
|
||||
|
||||
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
|
||||
#define EIC_NMICTRL_NMISENSE_Msk (0x7ul << EIC_NMICTRL_NMISENSE_Pos)
|
||||
#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
|
||||
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
|
||||
#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0ul /**< \brief (EIC_NMICTRL) No detection */
|
||||
#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1ul /**< \brief (EIC_NMICTRL) Rising-edge detection */
|
||||
#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2ul /**< \brief (EIC_NMICTRL) Falling-edge detection */
|
||||
@ -214,7 +211,7 @@ typedef union {
|
||||
#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
|
||||
#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFul << EIC_EVCTRL_EXTINTEO_Pos)
|
||||
#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
|
||||
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
|
||||
#define EIC_EVCTRL_MASK 0x0000FFFFul /**< \brief (EIC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
|
||||
@ -284,7 +281,7 @@ typedef union {
|
||||
#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
|
||||
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
|
||||
#define EIC_INTENCLR_EXTINT_Msk (0xFFFFul << EIC_INTENCLR_EXTINT_Pos)
|
||||
#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
|
||||
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
|
||||
#define EIC_INTENCLR_MASK 0x0000FFFFul /**< \brief (EIC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
|
||||
@ -354,34 +351,34 @@ typedef union {
|
||||
#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
|
||||
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
|
||||
#define EIC_INTENSET_EXTINT_Msk (0xFFFFul << EIC_INTENSET_EXTINT_Pos)
|
||||
#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
|
||||
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
|
||||
#define EIC_INTENSET_MASK 0x0000FFFFul /**< \brief (EIC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
||||
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
|
||||
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
|
||||
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
|
||||
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
|
||||
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
|
||||
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
|
||||
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
|
||||
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
|
||||
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
|
||||
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
|
||||
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
|
||||
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
|
||||
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
|
||||
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
|
||||
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
__I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
|
||||
__I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
|
||||
__I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
|
||||
__I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
|
||||
__I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
|
||||
__I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
|
||||
__I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
|
||||
__I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
|
||||
__I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
|
||||
__I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
|
||||
__I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
|
||||
__I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
|
||||
__I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
|
||||
__I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
|
||||
__I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
|
||||
__I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
|
||||
__I uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
|
||||
uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
|
||||
__I uint32_t :16; /*!< bit: 16..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EIC_INTFLAG_Type;
|
||||
@ -424,7 +421,7 @@ typedef union {
|
||||
#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
|
||||
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
|
||||
#define EIC_INTFLAG_EXTINT_Msk (0xFFFFul << EIC_INTFLAG_EXTINT_Pos)
|
||||
#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
|
||||
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
|
||||
#define EIC_INTFLAG_MASK 0x0000FFFFul /**< \brief (EIC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
|
||||
@ -494,7 +491,7 @@ typedef union {
|
||||
#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
|
||||
#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFul << EIC_WAKEUP_WAKEUPEN_Pos)
|
||||
#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
|
||||
#define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos))
|
||||
#define EIC_WAKEUP_MASK 0x0000FFFFul /**< \brief (EIC_WAKEUP) MASK Register */
|
||||
|
||||
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
|
||||
@ -527,7 +524,7 @@ typedef union {
|
||||
|
||||
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
|
||||
#define EIC_CONFIG_SENSE0_Msk (0x7ul << EIC_CONFIG_SENSE0_Pos)
|
||||
#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
|
||||
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
|
||||
#define EIC_CONFIG_SENSE0_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE0_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising-edge detection */
|
||||
#define EIC_CONFIG_SENSE0_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling-edge detection */
|
||||
@ -544,7 +541,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN0 (0x1ul << EIC_CONFIG_FILTEN0_Pos)
|
||||
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
|
||||
#define EIC_CONFIG_SENSE1_Msk (0x7ul << EIC_CONFIG_SENSE1_Pos)
|
||||
#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
|
||||
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
|
||||
#define EIC_CONFIG_SENSE1_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE1_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE1_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -561,7 +558,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN1 (0x1ul << EIC_CONFIG_FILTEN1_Pos)
|
||||
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
|
||||
#define EIC_CONFIG_SENSE2_Msk (0x7ul << EIC_CONFIG_SENSE2_Pos)
|
||||
#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
|
||||
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
|
||||
#define EIC_CONFIG_SENSE2_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE2_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE2_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -578,7 +575,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN2 (0x1ul << EIC_CONFIG_FILTEN2_Pos)
|
||||
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
|
||||
#define EIC_CONFIG_SENSE3_Msk (0x7ul << EIC_CONFIG_SENSE3_Pos)
|
||||
#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
|
||||
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
|
||||
#define EIC_CONFIG_SENSE3_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE3_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE3_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -595,7 +592,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN3 (0x1ul << EIC_CONFIG_FILTEN3_Pos)
|
||||
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
|
||||
#define EIC_CONFIG_SENSE4_Msk (0x7ul << EIC_CONFIG_SENSE4_Pos)
|
||||
#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
|
||||
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
|
||||
#define EIC_CONFIG_SENSE4_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE4_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE4_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -612,7 +609,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN4 (0x1ul << EIC_CONFIG_FILTEN4_Pos)
|
||||
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
|
||||
#define EIC_CONFIG_SENSE5_Msk (0x7ul << EIC_CONFIG_SENSE5_Pos)
|
||||
#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
|
||||
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
|
||||
#define EIC_CONFIG_SENSE5_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE5_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE5_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -629,7 +626,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN5 (0x1ul << EIC_CONFIG_FILTEN5_Pos)
|
||||
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
|
||||
#define EIC_CONFIG_SENSE6_Msk (0x7ul << EIC_CONFIG_SENSE6_Pos)
|
||||
#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
|
||||
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
|
||||
#define EIC_CONFIG_SENSE6_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE6_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE6_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
@ -646,7 +643,7 @@ typedef union {
|
||||
#define EIC_CONFIG_FILTEN6 (0x1ul << EIC_CONFIG_FILTEN6_Pos)
|
||||
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
|
||||
#define EIC_CONFIG_SENSE7_Msk (0x7ul << EIC_CONFIG_SENSE7_Pos)
|
||||
#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
|
||||
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
|
||||
#define EIC_CONFIG_SENSE7_NONE_Val 0x0ul /**< \brief (EIC_CONFIG) No detection */
|
||||
#define EIC_CONFIG_SENSE7_RISE_Val 0x1ul /**< \brief (EIC_CONFIG) Rising edge detection */
|
||||
#define EIC_CONFIG_SENSE7_FALL_Val 0x2ul /**< \brief (EIC_CONFIG) Falling edge detection */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_COMPONENT_
|
||||
#define _SAMD21_EVSYS_COMPONENT_
|
||||
@ -101,15 +98,15 @@ typedef union {
|
||||
|
||||
#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
|
||||
#define EVSYS_CHANNEL_CHANNEL_Msk (0xFul << EVSYS_CHANNEL_CHANNEL_Pos)
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
|
||||
#define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
|
||||
#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
|
||||
#define EVSYS_CHANNEL_SWEVT (0x1ul << EVSYS_CHANNEL_SWEVT_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
|
||||
#define EVSYS_CHANNEL_EVGEN_Msk (0x7Ful << EVSYS_CHANNEL_EVGEN_Pos)
|
||||
#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
|
||||
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
|
||||
#define EVSYS_CHANNEL_PATH_Msk (0x3ul << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
|
||||
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
|
||||
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0ul /**< \brief (EVSYS_CHANNEL) Synchronous path */
|
||||
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Resynchronized path */
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Asynchronous path */
|
||||
@ -118,7 +115,7 @@ typedef union {
|
||||
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
|
||||
#define EVSYS_CHANNEL_EDGSEL_Msk (0x3ul << EVSYS_CHANNEL_EDGSEL_Pos)
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
|
||||
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
|
||||
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0ul /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1ul /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2ul /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
|
||||
@ -147,10 +144,10 @@ typedef union {
|
||||
|
||||
#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
|
||||
#define EVSYS_USER_USER_Msk (0x1Ful << EVSYS_USER_USER_Pos)
|
||||
#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
|
||||
#define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
|
||||
#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
|
||||
#define EVSYS_USER_CHANNEL_Msk (0x1Ful << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
|
||||
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
|
||||
#define EVSYS_USER_CHANNEL_0_Val 0x0ul /**< \brief (EVSYS_USER) No Channel Output Selected */
|
||||
#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
|
||||
#define EVSYS_USER_MASK 0x1F1Ful /**< \brief (EVSYS_USER) MASK Register */
|
||||
@ -219,7 +216,7 @@ typedef union {
|
||||
#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFul << EVSYS_CHSTATUS_USRRDY_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
|
||||
#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
|
||||
@ -238,7 +235,7 @@ typedef union {
|
||||
#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFul << EVSYS_CHSTATUS_CHBUSY_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
|
||||
#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
|
||||
#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
|
||||
@ -249,7 +246,7 @@ typedef union {
|
||||
#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
|
||||
#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFul << EVSYS_CHSTATUS_USRRDYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
|
||||
#define EVSYS_CHSTATUS_USRRDYp8(value) (EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
|
||||
@ -260,7 +257,7 @@ typedef union {
|
||||
#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFul << EVSYS_CHSTATUS_CHBUSYp8_Pos)
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
|
||||
#define EVSYS_CHSTATUS_CHBUSYp8(value) (EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos))
|
||||
#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFul /**< \brief (EVSYS_CHSTATUS) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
|
||||
@ -327,7 +324,7 @@ typedef union {
|
||||
#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
|
||||
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR_Msk (0xFFul << EVSYS_INTENCLR_OVR_Pos)
|
||||
#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
|
||||
#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
|
||||
#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
|
||||
#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
|
||||
@ -346,7 +343,7 @@ typedef union {
|
||||
#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
|
||||
#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD_Msk (0xFFul << EVSYS_INTENCLR_EVD_Pos)
|
||||
#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
|
||||
#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
|
||||
#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
|
||||
#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
|
||||
@ -357,7 +354,7 @@ typedef union {
|
||||
#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_OVRp8_Msk (0xFul << EVSYS_INTENCLR_OVRp8_Pos)
|
||||
#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
|
||||
#define EVSYS_INTENCLR_OVRp8(value) (EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos))
|
||||
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
|
||||
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
|
||||
@ -368,7 +365,7 @@ typedef union {
|
||||
#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENCLR_EVDp8_Msk (0xFul << EVSYS_INTENCLR_EVDp8_Pos)
|
||||
#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
|
||||
#define EVSYS_INTENCLR_EVDp8(value) (EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos))
|
||||
#define EVSYS_INTENCLR_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
|
||||
@ -435,7 +432,7 @@ typedef union {
|
||||
#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
|
||||
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR_Msk (0xFFul << EVSYS_INTENSET_OVR_Pos)
|
||||
#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
|
||||
#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
|
||||
#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
|
||||
#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
|
||||
@ -454,7 +451,7 @@ typedef union {
|
||||
#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
|
||||
#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD_Msk (0xFFul << EVSYS_INTENSET_EVD_Pos)
|
||||
#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
|
||||
#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
|
||||
#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
|
||||
#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
|
||||
@ -465,7 +462,7 @@ typedef union {
|
||||
#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
|
||||
#define EVSYS_INTENSET_OVRp8_Msk (0xFul << EVSYS_INTENSET_OVRp8_Pos)
|
||||
#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
|
||||
#define EVSYS_INTENSET_OVRp8(value) (EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos))
|
||||
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
|
||||
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
|
||||
@ -476,47 +473,47 @@ typedef union {
|
||||
#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
|
||||
#define EVSYS_INTENSET_EVDp8_Msk (0xFul << EVSYS_INTENSET_EVDp8_Pos)
|
||||
#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
|
||||
#define EVSYS_INTENSET_EVDp8(value) (EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos))
|
||||
#define EVSYS_INTENSET_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTENSET) MASK Register */
|
||||
|
||||
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
||||
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
||||
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
|
||||
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
|
||||
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
|
||||
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
|
||||
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
|
||||
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
|
||||
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
|
||||
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
|
||||
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
|
||||
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
|
||||
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
|
||||
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
|
||||
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
|
||||
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
|
||||
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
|
||||
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
|
||||
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
|
||||
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
|
||||
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
|
||||
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
|
||||
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
|
||||
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
|
||||
__I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
|
||||
__I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
|
||||
__I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
|
||||
__I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
|
||||
__I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
|
||||
__I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
|
||||
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
|
||||
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
|
||||
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
|
||||
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
|
||||
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
|
||||
uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
|
||||
uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
__I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
|
||||
__I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
|
||||
__I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
|
||||
__I uint32_t :4; /*!< bit: 20..23 Reserved */
|
||||
__I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
|
||||
__I uint32_t :4; /*!< bit: 28..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} EVSYS_INTFLAG_Type;
|
||||
@ -543,7 +540,7 @@ typedef union {
|
||||
#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
|
||||
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
|
||||
#define EVSYS_INTFLAG_OVR_Msk (0xFFul << EVSYS_INTFLAG_OVR_Pos)
|
||||
#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
|
||||
#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
|
||||
#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
|
||||
#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
|
||||
@ -562,7 +559,7 @@ typedef union {
|
||||
#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
|
||||
#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD_Msk (0xFFul << EVSYS_INTFLAG_EVD_Pos)
|
||||
#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
|
||||
#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
|
||||
#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
|
||||
#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
|
||||
@ -573,7 +570,7 @@ typedef union {
|
||||
#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
|
||||
#define EVSYS_INTFLAG_OVRp8_Msk (0xFul << EVSYS_INTFLAG_OVRp8_Pos)
|
||||
#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
|
||||
#define EVSYS_INTFLAG_OVRp8(value) (EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos))
|
||||
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
|
||||
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
|
||||
@ -584,7 +581,7 @@ typedef union {
|
||||
#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
|
||||
#define EVSYS_INTFLAG_EVDp8_Msk (0xFul << EVSYS_INTFLAG_EVDp8_Pos)
|
||||
#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
|
||||
#define EVSYS_INTFLAG_EVDp8(value) (EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos))
|
||||
#define EVSYS_INTFLAG_MASK 0x0F0FFFFFul /**< \brief (EVSYS_INTFLAG) MASK Register */
|
||||
|
||||
/** \brief EVSYS hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_COMPONENT_
|
||||
#define _SAMD21_GCLK_COMPONENT_
|
||||
@ -112,7 +109,7 @@ typedef union {
|
||||
|
||||
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
|
||||
#define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
|
||||
#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
|
||||
#define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */
|
||||
@ -189,7 +186,7 @@ typedef union {
|
||||
#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
|
||||
#define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
|
||||
#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
|
||||
@ -237,10 +234,10 @@ typedef union {
|
||||
|
||||
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
|
||||
#define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos)
|
||||
#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
|
||||
#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
|
||||
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
|
||||
#define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
|
||||
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
|
||||
#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
|
||||
@ -291,10 +288,10 @@ typedef union {
|
||||
|
||||
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
|
||||
#define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos)
|
||||
#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
|
||||
#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
|
||||
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
|
||||
#define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos)
|
||||
#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
|
||||
#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
|
||||
#define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */
|
||||
|
||||
/** \brief GCLK hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for HMATRIXB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_HMATRIXB_COMPONENT_
|
||||
#define _SAMD21_HMATRIXB_COMPONENT_
|
||||
@ -95,7 +92,7 @@ typedef union {
|
||||
|
||||
#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
|
||||
#define HMATRIXB_SFR_SFR_Msk (0xFFFFFFFFul << HMATRIXB_SFR_SFR_Pos)
|
||||
#define HMATRIXB_SFR_SFR(value) ((HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos)))
|
||||
#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
|
||||
#define HMATRIXB_SFR_MASK 0xFFFFFFFFul /**< \brief (HMATRIXB_SFR) MASK Register */
|
||||
|
||||
/** \brief HmatrixbPrs hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for I2S
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_COMPONENT_
|
||||
#define _SAMD21_I2S_COMPONENT_
|
||||
@ -91,14 +88,14 @@ typedef union {
|
||||
#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
|
||||
#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
|
||||
#define I2S_CTRLA_CKEN_Msk (0x3ul << I2S_CTRLA_CKEN_Pos)
|
||||
#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
|
||||
#define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos))
|
||||
#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
|
||||
#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
|
||||
#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
|
||||
#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
|
||||
#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
|
||||
#define I2S_CTRLA_SEREN_Msk (0x3ul << I2S_CTRLA_SEREN_Pos)
|
||||
#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
|
||||
#define I2S_CTRLA_SEREN(value) (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos))
|
||||
#define I2S_CTRLA_MASK 0x3Ful /**< \brief (I2S_CTRLA) MASK Register */
|
||||
|
||||
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
|
||||
@ -132,7 +129,7 @@ typedef union {
|
||||
|
||||
#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3ul << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
|
||||
#define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
|
||||
#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0ul /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1ul /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
|
||||
#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2ul /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
|
||||
@ -143,10 +140,10 @@ typedef union {
|
||||
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
|
||||
#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
|
||||
#define I2S_CLKCTRL_NBSLOTS_Msk (0x7ul << I2S_CLKCTRL_NBSLOTS_Pos)
|
||||
#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
|
||||
#define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
|
||||
#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
|
||||
#define I2S_CLKCTRL_FSWIDTH_Msk (0x3ul << I2S_CLKCTRL_FSWIDTH_Pos)
|
||||
#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
|
||||
#define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
|
||||
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
|
||||
#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
|
||||
#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2ul /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
|
||||
@ -185,10 +182,10 @@ typedef union {
|
||||
#define I2S_CLKCTRL_MCKEN (0x1ul << I2S_CLKCTRL_MCKEN_Pos)
|
||||
#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
|
||||
#define I2S_CLKCTRL_MCKDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKDIV_Pos)
|
||||
#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
|
||||
#define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
|
||||
#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
|
||||
#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Ful << I2S_CLKCTRL_MCKOUTDIV_Pos)
|
||||
#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
|
||||
#define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
|
||||
#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
|
||||
#define I2S_CLKCTRL_FSOUTINV (0x1ul << I2S_CLKCTRL_FSOUTINV_Pos)
|
||||
#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
|
||||
@ -237,28 +234,28 @@ typedef union {
|
||||
#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
|
||||
#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXRDY_Msk (0x3ul << I2S_INTENCLR_RXRDY_Pos)
|
||||
#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
|
||||
#define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos))
|
||||
#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
|
||||
#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
|
||||
#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
|
||||
#define I2S_INTENCLR_RXOR_Msk (0x3ul << I2S_INTENCLR_RXOR_Pos)
|
||||
#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
|
||||
#define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos))
|
||||
#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
|
||||
#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
|
||||
#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXRDY_Msk (0x3ul << I2S_INTENCLR_TXRDY_Pos)
|
||||
#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
|
||||
#define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos))
|
||||
#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
|
||||
#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
|
||||
#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
|
||||
#define I2S_INTENCLR_TXUR_Msk (0x3ul << I2S_INTENCLR_TXUR_Pos)
|
||||
#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
|
||||
#define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos))
|
||||
#define I2S_INTENCLR_MASK 0x3333ul /**< \brief (I2S_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
|
||||
@ -301,56 +298,56 @@ typedef union {
|
||||
#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
|
||||
#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
|
||||
#define I2S_INTENSET_RXRDY_Msk (0x3ul << I2S_INTENSET_RXRDY_Pos)
|
||||
#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
|
||||
#define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos))
|
||||
#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
|
||||
#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
|
||||
#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
|
||||
#define I2S_INTENSET_RXOR_Msk (0x3ul << I2S_INTENSET_RXOR_Pos)
|
||||
#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
|
||||
#define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos))
|
||||
#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
|
||||
#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
|
||||
#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
|
||||
#define I2S_INTENSET_TXRDY_Msk (0x3ul << I2S_INTENSET_TXRDY_Pos)
|
||||
#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
|
||||
#define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos))
|
||||
#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
|
||||
#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
|
||||
#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
|
||||
#define I2S_INTENSET_TXUR_Msk (0x3ul << I2S_INTENSET_TXUR_Pos)
|
||||
#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
|
||||
#define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos))
|
||||
#define I2S_INTENSET_MASK 0x3333ul /**< \brief (I2S_INTENSET) MASK Register */
|
||||
|
||||
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
|
||||
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
|
||||
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
|
||||
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
|
||||
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
__I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
|
||||
__I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
|
||||
__I uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
|
||||
__I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
|
||||
__I uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
|
||||
__I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
|
||||
__I uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
__I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
|
||||
__I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
|
||||
__I uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
|
||||
uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
|
||||
uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
|
||||
uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
__I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
|
||||
__I uint16_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
__I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
|
||||
__I uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
|
||||
__I uint16_t :2; /*!< bit: 10..11 Reserved */
|
||||
__I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
|
||||
__I uint16_t :2; /*!< bit: 14..15 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} I2S_INTFLAG_Type;
|
||||
@ -365,28 +362,28 @@ typedef union {
|
||||
#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
|
||||
#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
|
||||
#define I2S_INTFLAG_RXRDY_Msk (0x3ul << I2S_INTFLAG_RXRDY_Pos)
|
||||
#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
|
||||
#define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos))
|
||||
#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
|
||||
#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
|
||||
#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
|
||||
#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
|
||||
#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
|
||||
#define I2S_INTFLAG_RXOR_Msk (0x3ul << I2S_INTFLAG_RXOR_Pos)
|
||||
#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
|
||||
#define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos))
|
||||
#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
|
||||
#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
|
||||
#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
|
||||
#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
|
||||
#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
|
||||
#define I2S_INTFLAG_TXRDY_Msk (0x3ul << I2S_INTFLAG_TXRDY_Pos)
|
||||
#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
|
||||
#define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos))
|
||||
#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
|
||||
#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
|
||||
#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
|
||||
#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
|
||||
#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
|
||||
#define I2S_INTFLAG_TXUR_Msk (0x3ul << I2S_INTFLAG_TXUR_Pos)
|
||||
#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
|
||||
#define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos))
|
||||
#define I2S_INTFLAG_MASK 0x3333ul /**< \brief (I2S_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
|
||||
@ -429,21 +426,21 @@ typedef union {
|
||||
#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_CKEN_Msk (0x3ul << I2S_SYNCBUSY_CKEN_Pos)
|
||||
#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
|
||||
#define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos))
|
||||
#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
|
||||
#define I2S_SYNCBUSY_SEREN_Msk (0x3ul << I2S_SYNCBUSY_SEREN_Pos)
|
||||
#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
|
||||
#define I2S_SYNCBUSY_SEREN(value) (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos))
|
||||
#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
|
||||
#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
|
||||
#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
|
||||
#define I2S_SYNCBUSY_DATA_Msk (0x3ul << I2S_SYNCBUSY_DATA_Pos)
|
||||
#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
|
||||
#define I2S_SYNCBUSY_DATA(value) (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos))
|
||||
#define I2S_SYNCBUSY_MASK 0x033Ful /**< \brief (I2S_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
|
||||
@ -488,7 +485,7 @@ typedef union {
|
||||
|
||||
#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
|
||||
#define I2S_SERCTRL_SERMODE_Msk (0x3ul << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
|
||||
#define I2S_SERCTRL_SERMODE(value) (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
|
||||
#define I2S_SERCTRL_SERMODE_RX_Val 0x0ul /**< \brief (I2S_SERCTRL) Receive */
|
||||
#define I2S_SERCTRL_SERMODE_TX_Val 0x1ul /**< \brief (I2S_SERCTRL) Transmit */
|
||||
#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2ul /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
|
||||
@ -497,7 +494,7 @@ typedef union {
|
||||
#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
|
||||
#define I2S_SERCTRL_TXDEFAULT_Msk (0x3ul << I2S_SERCTRL_TXDEFAULT_Pos)
|
||||
#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
|
||||
#define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
|
||||
#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
|
||||
#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
|
||||
#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3ul /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
|
||||
@ -524,7 +521,7 @@ typedef union {
|
||||
#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
|
||||
#define I2S_SERCTRL_DATASIZE_Msk (0x7ul << I2S_SERCTRL_DATASIZE_Pos)
|
||||
#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
|
||||
#define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
|
||||
#define I2S_SERCTRL_DATASIZE_32_Val 0x0ul /**< \brief (I2S_SERCTRL) 32 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_24_Val 0x1ul /**< \brief (I2S_SERCTRL) 24 bits */
|
||||
#define I2S_SERCTRL_DATASIZE_20_Val 0x2ul /**< \brief (I2S_SERCTRL) 20 bits */
|
||||
@ -549,7 +546,7 @@ typedef union {
|
||||
#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
|
||||
#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
|
||||
#define I2S_SERCTRL_EXTEND_Msk (0x3ul << I2S_SERCTRL_EXTEND_Pos)
|
||||
#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
|
||||
#define I2S_SERCTRL_EXTEND(value) (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
|
||||
#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0ul /**< \brief (I2S_SERCTRL) Extend with zeroes */
|
||||
#define I2S_SERCTRL_EXTEND_ONE_Val 0x1ul /**< \brief (I2S_SERCTRL) Extend with ones */
|
||||
#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2ul /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
|
||||
@ -582,7 +579,7 @@ typedef union {
|
||||
#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
|
||||
#define I2S_SERCTRL_SLOTDIS_Msk (0xFFul << I2S_SERCTRL_SLOTDIS_Pos)
|
||||
#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
|
||||
#define I2S_SERCTRL_SLOTDIS(value) (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos))
|
||||
#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
|
||||
#define I2S_SERCTRL_MONO (0x1ul << I2S_SERCTRL_MONO_Pos)
|
||||
#define I2S_SERCTRL_MONO_STEREO_Val 0x0ul /**< \brief (I2S_SERCTRL) Normal mode */
|
||||
@ -614,7 +611,7 @@ typedef union {
|
||||
|
||||
#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
|
||||
#define I2S_DATA_DATA_Msk (0xFFFFFFFFul << I2S_DATA_DATA_Pos)
|
||||
#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
|
||||
#define I2S_DATA_DATA(value) (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
|
||||
#define I2S_DATA_MASK 0xFFFFFFFFul /**< \brief (I2S_DATA) MASK Register */
|
||||
|
||||
/** \brief I2S hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for MTB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_COMPONENT_
|
||||
#define _SAMD21_MTB_COMPONENT_
|
||||
@ -74,7 +71,7 @@ typedef union {
|
||||
#define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
|
||||
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
|
||||
#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
|
||||
#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
|
||||
#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
|
||||
#define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
|
||||
|
||||
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
|
||||
@ -99,7 +96,7 @@ typedef union {
|
||||
|
||||
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
|
||||
#define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
|
||||
#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
|
||||
#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
|
||||
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
|
||||
#define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
|
||||
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
|
||||
@ -136,7 +133,7 @@ typedef union {
|
||||
#define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
|
||||
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
|
||||
#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
|
||||
#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
|
||||
#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
|
||||
#define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
|
||||
|
||||
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_COMPONENT_
|
||||
#define _SAMD21_NVMCTRL_COMPONENT_
|
||||
@ -54,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define NVMCTRL_U2207
|
||||
#define REV_NVMCTRL 0x201
|
||||
#define REV_NVMCTRL 0x202
|
||||
|
||||
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -73,7 +70,7 @@ typedef union {
|
||||
|
||||
#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
|
||||
#define NVMCTRL_CTRLA_CMD_Msk (0x7Ful << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
|
||||
#define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
|
||||
#define NVMCTRL_CTRLA_CMD_ER_Val 0x2ul /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_WP_Val 0x4ul /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
|
||||
#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5ul /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
|
||||
@ -106,7 +103,7 @@ typedef union {
|
||||
#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
|
||||
#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
|
||||
#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFul << NVMCTRL_CTRLA_CMDEX_Pos)
|
||||
#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
|
||||
#define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
|
||||
#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5ul /**< \brief (NVMCTRL_CTRLA) Execution Key */
|
||||
#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
|
||||
#define NVMCTRL_CTRLA_MASK 0xFF7Ful /**< \brief (NVMCTRL_CTRLA) MASK Register */
|
||||
@ -134,7 +131,7 @@ typedef union {
|
||||
|
||||
#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
|
||||
#define NVMCTRL_CTRLB_RWS_Msk (0xFul << NVMCTRL_CTRLB_RWS_Pos)
|
||||
#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
|
||||
#define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
|
||||
#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
|
||||
#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
|
||||
#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
|
||||
@ -145,7 +142,7 @@ typedef union {
|
||||
#define NVMCTRL_CTRLB_MANW (0x1ul << NVMCTRL_CTRLB_MANW_Pos)
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3ul << NVMCTRL_CTRLB_SLEEPPRM_Pos)
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3ul /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
|
||||
@ -154,7 +151,7 @@ typedef union {
|
||||
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
|
||||
#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
|
||||
#define NVMCTRL_CTRLB_READMODE_Msk (0x3ul << NVMCTRL_CTRLB_READMODE_Pos)
|
||||
#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
|
||||
#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
|
||||
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0ul /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
|
||||
#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1ul /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
|
||||
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2ul /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
|
||||
@ -183,10 +180,10 @@ typedef union {
|
||||
|
||||
#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
|
||||
#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFul << NVMCTRL_PARAM_NVMP_Pos)
|
||||
#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
|
||||
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
|
||||
#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
|
||||
#define NVMCTRL_PARAM_PSZ_Msk (0x7ul << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
|
||||
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
|
||||
#define NVMCTRL_PARAM_PSZ_8_Val 0x0ul /**< \brief (NVMCTRL_PARAM) 8 bytes */
|
||||
#define NVMCTRL_PARAM_PSZ_16_Val 0x1ul /**< \brief (NVMCTRL_PARAM) 16 bytes */
|
||||
#define NVMCTRL_PARAM_PSZ_32_Val 0x2ul /**< \brief (NVMCTRL_PARAM) 32 bytes */
|
||||
@ -205,7 +202,7 @@ typedef union {
|
||||
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
|
||||
#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
|
||||
#define NVMCTRL_PARAM_RWWEEP_Msk (0xFFFul << NVMCTRL_PARAM_RWWEEP_Pos)
|
||||
#define NVMCTRL_PARAM_RWWEEP(value) ((NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos)))
|
||||
#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
|
||||
#define NVMCTRL_PARAM_MASK 0xFFF7FFFFul /**< \brief (NVMCTRL_PARAM) MASK Register */
|
||||
|
||||
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
|
||||
@ -252,11 +249,11 @@ typedef union {
|
||||
|
||||
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t READY:1; /*!< bit: 0 NVM Ready */
|
||||
uint8_t ERROR:1; /*!< bit: 1 Error */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
__I uint8_t READY:1; /*!< bit: 0 NVM Ready */
|
||||
__I uint8_t ERROR:1; /*!< bit: 1 Error */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} NVMCTRL_INTFLAG_Type;
|
||||
@ -321,7 +318,7 @@ typedef union {
|
||||
|
||||
#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
|
||||
#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFul << NVMCTRL_ADDR_ADDR_Pos)
|
||||
#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
|
||||
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
|
||||
#define NVMCTRL_ADDR_MASK 0x003FFFFFul /**< \brief (NVMCTRL_ADDR) MASK Register */
|
||||
|
||||
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
|
||||
@ -338,7 +335,7 @@ typedef union {
|
||||
|
||||
#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
|
||||
#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFul << NVMCTRL_LOCK_LOCK_Pos)
|
||||
#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
|
||||
#define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
|
||||
#define NVMCTRL_LOCK_MASK 0xFFFFul /**< \brief (NVMCTRL_LOCK) MASK Register */
|
||||
|
||||
/** \brief NVMCTRL APB hardware registers */
|
||||
@ -360,13 +357,21 @@ typedef struct {
|
||||
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
|
||||
} Nvmctrl;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SECTION_NVMCTRL_AUX3
|
||||
|
||||
#define SECTION_NVMCTRL_CAL
|
||||
|
||||
#define SECTION_NVMCTRL_LOCKBIT
|
||||
|
||||
#define SECTION_NVMCTRL_OTP1
|
||||
|
||||
#define SECTION_NVMCTRL_OTP2
|
||||
|
||||
#define SECTION_NVMCTRL_OTP4
|
||||
|
||||
#define SECTION_NVMCTRL_TEMP_LOG
|
||||
|
||||
#define SECTION_NVMCTRL_USER
|
||||
|
||||
/*@}*/
|
||||
@ -381,27 +386,27 @@ typedef struct {
|
||||
#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
|
||||
#define ADC_FUSES_BIASCAL_Msk (0x7ul << ADC_FUSES_BIASCAL_Pos)
|
||||
#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
|
||||
#define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos))
|
||||
|
||||
#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
|
||||
#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
|
||||
#define ADC_FUSES_LINEARITY_0_Msk (0x1Ful << ADC_FUSES_LINEARITY_0_Pos)
|
||||
#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
|
||||
#define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos))
|
||||
|
||||
#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
|
||||
#define ADC_FUSES_LINEARITY_1_Msk (0x7ul << ADC_FUSES_LINEARITY_1_Pos)
|
||||
#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
|
||||
#define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos))
|
||||
|
||||
#define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
|
||||
#define FUSES_BOD33USERLEVEL_Msk (0x3Ful << FUSES_BOD33USERLEVEL_Pos)
|
||||
#define FUSES_BOD33USERLEVEL(value) ((FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)))
|
||||
#define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos))
|
||||
|
||||
#define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
|
||||
#define FUSES_BOD33_ACTION_Msk (0x3ul << FUSES_BOD33_ACTION_Pos)
|
||||
#define FUSES_BOD33_ACTION(value) ((FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)))
|
||||
#define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos))
|
||||
|
||||
#define FUSES_BOD33_EN_ADDR NVMCTRL_USER
|
||||
#define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
|
||||
@ -414,57 +419,57 @@ typedef struct {
|
||||
#define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
|
||||
#define FUSES_DFLL48M_COARSE_CAL_Msk (0x3Ful << FUSES_DFLL48M_COARSE_CAL_Pos)
|
||||
#define FUSES_DFLL48M_COARSE_CAL(value) ((FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)))
|
||||
#define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos))
|
||||
|
||||
#define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8)
|
||||
#define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */
|
||||
#define FUSES_DFLL48M_FINE_CAL_Msk (0x3FFul << FUSES_DFLL48M_FINE_CAL_Pos)
|
||||
#define FUSES_DFLL48M_FINE_CAL(value) ((FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)))
|
||||
#define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos))
|
||||
|
||||
#define FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
|
||||
#define FUSES_HOT_ADC_VAL_Msk (0xFFFul << FUSES_HOT_ADC_VAL_Pos)
|
||||
#define FUSES_HOT_ADC_VAL(value) ((FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos)))
|
||||
#define FUSES_HOT_ADC_VAL(value) (FUSES_HOT_ADC_VAL_Msk & ((value) << FUSES_HOT_ADC_VAL_Pos))
|
||||
|
||||
#define FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
|
||||
#define FUSES_HOT_INT1V_VAL_Msk (0xFFul << FUSES_HOT_INT1V_VAL_Pos)
|
||||
#define FUSES_HOT_INT1V_VAL(value) ((FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos)))
|
||||
#define FUSES_HOT_INT1V_VAL(value) (FUSES_HOT_INT1V_VAL_Msk & ((value) << FUSES_HOT_INT1V_VAL_Pos))
|
||||
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
|
||||
#define FUSES_HOT_TEMP_VAL_DEC_Msk (0xFul << FUSES_HOT_TEMP_VAL_DEC_Pos)
|
||||
#define FUSES_HOT_TEMP_VAL_DEC(value) ((FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos)))
|
||||
#define FUSES_HOT_TEMP_VAL_DEC(value) (FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << FUSES_HOT_TEMP_VAL_DEC_Pos))
|
||||
|
||||
#define FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
|
||||
#define FUSES_HOT_TEMP_VAL_INT_Msk (0xFFul << FUSES_HOT_TEMP_VAL_INT_Pos)
|
||||
#define FUSES_HOT_TEMP_VAL_INT(value) ((FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos)))
|
||||
#define FUSES_HOT_TEMP_VAL_INT(value) (FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << FUSES_HOT_TEMP_VAL_INT_Pos))
|
||||
|
||||
#define FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
|
||||
#define FUSES_OSC32K_CAL_Msk (0x7Ful << FUSES_OSC32K_CAL_Pos)
|
||||
#define FUSES_OSC32K_CAL(value) ((FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos)))
|
||||
#define FUSES_OSC32K_CAL(value) (FUSES_OSC32K_CAL_Msk & ((value) << FUSES_OSC32K_CAL_Pos))
|
||||
|
||||
#define FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
#define FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
|
||||
#define FUSES_ROOM_ADC_VAL_Msk (0xFFFul << FUSES_ROOM_ADC_VAL_Pos)
|
||||
#define FUSES_ROOM_ADC_VAL(value) ((FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos)))
|
||||
#define FUSES_ROOM_ADC_VAL(value) (FUSES_ROOM_ADC_VAL_Msk & ((value) << FUSES_ROOM_ADC_VAL_Pos))
|
||||
|
||||
#define FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
|
||||
#define FUSES_ROOM_INT1V_VAL_Msk (0xFFul << FUSES_ROOM_INT1V_VAL_Pos)
|
||||
#define FUSES_ROOM_INT1V_VAL(value) ((FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos)))
|
||||
#define FUSES_ROOM_INT1V_VAL(value) (FUSES_ROOM_INT1V_VAL_Msk & ((value) << FUSES_ROOM_INT1V_VAL_Pos))
|
||||
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFul << FUSES_ROOM_TEMP_VAL_DEC_Pos)
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC(value) ((FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos)))
|
||||
#define FUSES_ROOM_TEMP_VAL_DEC(value) (FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << FUSES_ROOM_TEMP_VAL_DEC_Pos))
|
||||
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
|
||||
#define FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFul << FUSES_ROOM_TEMP_VAL_INT_Pos)
|
||||
#define FUSES_ROOM_TEMP_VAL_INT(value) ((FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos)))
|
||||
#define FUSES_ROOM_TEMP_VAL_INT(value) (FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << FUSES_ROOM_TEMP_VAL_INT_Pos))
|
||||
|
||||
#define FUSES_SERIAL_NUMBER_0_ADDR (NVMCTRL_AUX3 + 64)
|
||||
#define FUSES_SERIAL_NUMBER_0_Pos 0 /**< \brief (NVMCTRL_AUX3) Serial Number words 2-0 bits 31:0 */
|
||||
@ -489,12 +494,12 @@ typedef struct {
|
||||
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
|
||||
#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
|
||||
#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7ul << NVMCTRL_FUSES_BOOTPROT_Pos)
|
||||
#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
|
||||
#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
|
||||
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7ul << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
|
||||
#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
|
||||
|
||||
/* Compatible definition for previous driver (begin 1) */
|
||||
#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
@ -517,31 +522,10 @@ typedef struct {
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
|
||||
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
|
||||
/* Compatible definition for previous driver (end 1) */
|
||||
|
||||
#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
|
||||
#define NVMCTRL_FUSES_NVMP_Msk (0x1FFFul << NVMCTRL_FUSES_NVMP_Pos)
|
||||
#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
|
||||
#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFul << NVMCTRL_FUSES_NVM_LOCK_Pos)
|
||||
#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
|
||||
#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
|
||||
#define NVMCTRL_FUSES_PSZ_Msk (0xFul << NVMCTRL_FUSES_PSZ_Pos)
|
||||
#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFul << NVMCTRL_FUSES_REGION_LOCKS_Pos)
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
|
||||
|
||||
#define NVMCTRL_FUSES_RWWEEP_ADDR (NVMCTRL_OTP1 + 4)
|
||||
#define NVMCTRL_FUSES_RWWEEP_Pos 0 /**< \brief (NVMCTRL_OTP1) RWW EEPROM */
|
||||
#define NVMCTRL_FUSES_RWWEEP_Msk (0xFFul << NVMCTRL_FUSES_RWWEEP_Pos)
|
||||
#define NVMCTRL_FUSES_RWWEEP(value) ((NVMCTRL_FUSES_RWWEEP_Msk & ((value) << NVMCTRL_FUSES_RWWEEP_Pos)))
|
||||
#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
|
||||
|
||||
/* Compatible definition for previous driver (begin 2) */
|
||||
#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
|
||||
@ -592,21 +576,20 @@ typedef struct {
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
|
||||
#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
|
||||
/* Compatible definition for previous driver (end 2) */
|
||||
|
||||
#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
|
||||
#define USB_FUSES_TRANSN_Msk (0x1Ful << USB_FUSES_TRANSN_Pos)
|
||||
#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
|
||||
#define USB_FUSES_TRANSN(value) (USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos))
|
||||
|
||||
#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
|
||||
#define USB_FUSES_TRANSP_Msk (0x1Ful << USB_FUSES_TRANSP_Pos)
|
||||
#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
|
||||
#define USB_FUSES_TRANSP(value) (USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos))
|
||||
|
||||
#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
|
||||
#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
|
||||
#define USB_FUSES_TRIM_Msk (0x7ul << USB_FUSES_TRIM_Pos)
|
||||
#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
|
||||
#define USB_FUSES_TRIM(value) (USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos))
|
||||
|
||||
#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
|
||||
#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
|
||||
@ -619,12 +602,12 @@ typedef struct {
|
||||
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
|
||||
#define WDT_FUSES_EWOFFSET_Msk (0xFul << WDT_FUSES_EWOFFSET_Pos)
|
||||
#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
|
||||
#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
|
||||
|
||||
#define WDT_FUSES_PER_ADDR NVMCTRL_USER
|
||||
#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
|
||||
#define WDT_FUSES_PER_Msk (0xFul << WDT_FUSES_PER_Pos)
|
||||
#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
|
||||
#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
|
||||
|
||||
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
|
||||
@ -637,7 +620,7 @@ typedef struct {
|
||||
#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
|
||||
#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
|
||||
#define WDT_FUSES_WINDOW_1_Msk (0x7ul << WDT_FUSES_WINDOW_1_Pos)
|
||||
#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
|
||||
#define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for PAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC_COMPONENT_
|
||||
#define _SAMD21_PAC_COMPONENT_
|
||||
@ -72,7 +69,7 @@ typedef union {
|
||||
|
||||
#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
|
||||
#define PAC_WPCLR_WP_Msk (0x7FFFFFFFul << PAC_WPCLR_WP_Pos)
|
||||
#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
|
||||
#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
|
||||
#define PAC_WPCLR_MASK 0xFFFFFFFEul /**< \brief (PAC_WPCLR) MASK Register */
|
||||
|
||||
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
|
||||
@ -91,7 +88,7 @@ typedef union {
|
||||
|
||||
#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
|
||||
#define PAC_WPSET_WP_Msk (0x7FFFFFFFul << PAC_WPSET_WP_Pos)
|
||||
#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
|
||||
#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
|
||||
#define PAC_WPSET_MASK 0xFFFFFFFEul /**< \brief (PAC_WPSET) MASK Register */
|
||||
|
||||
/** \brief PAC hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for PM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_COMPONENT_
|
||||
#define _SAMD21_PM_COMPONENT_
|
||||
@ -54,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define PM_U2206
|
||||
#define REV_PM 0x211
|
||||
#define REV_PM 0x212
|
||||
|
||||
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -84,7 +81,7 @@ typedef union {
|
||||
|
||||
#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
|
||||
#define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos)
|
||||
#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
|
||||
#define PM_SLEEP_IDLE(value) (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
|
||||
#define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
|
||||
#define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
|
||||
#define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
|
||||
@ -127,7 +124,7 @@ typedef union {
|
||||
|
||||
#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
|
||||
#define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos)
|
||||
#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
|
||||
#define PM_CPUSEL_CPUDIV(value) (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
|
||||
#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */
|
||||
#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */
|
||||
#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */
|
||||
@ -162,7 +159,7 @@ typedef union {
|
||||
|
||||
#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
|
||||
#define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos)
|
||||
#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
|
||||
#define PM_APBASEL_APBADIV(value) (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
|
||||
#define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */
|
||||
#define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */
|
||||
#define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */
|
||||
@ -197,7 +194,7 @@ typedef union {
|
||||
|
||||
#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
|
||||
#define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos)
|
||||
#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
|
||||
#define PM_APBBSEL_APBBDIV(value) (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
|
||||
#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */
|
||||
#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */
|
||||
#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */
|
||||
@ -232,7 +229,7 @@ typedef union {
|
||||
|
||||
#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
|
||||
#define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos)
|
||||
#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
|
||||
#define PM_APBCSEL_APBCDIV(value) (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
|
||||
#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */
|
||||
#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */
|
||||
#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */
|
||||
@ -385,8 +382,7 @@ typedef union {
|
||||
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
|
||||
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
|
||||
uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
|
||||
uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
|
||||
uint32_t :9; /*!< bit: 23..31 Reserved */
|
||||
uint32_t :10; /*!< bit: 22..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PM_APBCMASK_Type;
|
||||
@ -439,9 +435,7 @@ typedef union {
|
||||
#define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos)
|
||||
#define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */
|
||||
#define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos)
|
||||
#define PM_APBCMASK_LINCTRL_Pos 22 /**< \brief (PM_APBCMASK) LINCTRL APB Clock Enable */
|
||||
#define PM_APBCMASK_LINCTRL (0x1ul << PM_APBCMASK_LINCTRL_Pos)
|
||||
#define PM_APBCMASK_MASK 0x007FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
|
||||
#define PM_APBCMASK_MASK 0x003FFFFFul /**< \brief (PM_APBCMASK) MASK Register */
|
||||
|
||||
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -481,10 +475,10 @@ typedef union {
|
||||
|
||||
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PM_INTFLAG_Type;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for PORT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_COMPONENT_
|
||||
#define _SAMD21_PORT_COMPONENT_
|
||||
@ -71,7 +68,7 @@ typedef union {
|
||||
|
||||
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
|
||||
#define PORT_DIR_DIR_Msk (0xFFFFFFFFul << PORT_DIR_DIR_Pos)
|
||||
#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
|
||||
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
|
||||
#define PORT_DIR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
|
||||
@ -89,7 +86,7 @@ typedef union {
|
||||
|
||||
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
|
||||
#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFul << PORT_DIRCLR_DIRCLR_Pos)
|
||||
#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
|
||||
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
|
||||
#define PORT_DIRCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
|
||||
@ -107,7 +104,7 @@ typedef union {
|
||||
|
||||
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
|
||||
#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFul << PORT_DIRSET_DIRSET_Pos)
|
||||
#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
|
||||
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
|
||||
#define PORT_DIRSET_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRSET) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
|
||||
@ -125,7 +122,7 @@ typedef union {
|
||||
|
||||
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
|
||||
#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFul << PORT_DIRTGL_DIRTGL_Pos)
|
||||
#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
|
||||
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
|
||||
#define PORT_DIRTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_DIRTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
|
||||
@ -143,7 +140,7 @@ typedef union {
|
||||
|
||||
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
|
||||
#define PORT_OUT_OUT_Msk (0xFFFFFFFFul << PORT_OUT_OUT_Pos)
|
||||
#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
|
||||
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
|
||||
#define PORT_OUT_MASK 0xFFFFFFFFul /**< \brief (PORT_OUT) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
|
||||
@ -161,7 +158,7 @@ typedef union {
|
||||
|
||||
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
|
||||
#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFul << PORT_OUTCLR_OUTCLR_Pos)
|
||||
#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
|
||||
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
|
||||
#define PORT_OUTCLR_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
|
||||
@ -179,7 +176,7 @@ typedef union {
|
||||
|
||||
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
|
||||
#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFul << PORT_OUTSET_OUTSET_Pos)
|
||||
#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
|
||||
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
|
||||
#define PORT_OUTSET_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTSET) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
|
||||
@ -197,7 +194,7 @@ typedef union {
|
||||
|
||||
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFul << PORT_OUTTGL_OUTTGL_Pos)
|
||||
#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
|
||||
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
|
||||
#define PORT_OUTTGL_MASK 0xFFFFFFFFul /**< \brief (PORT_OUTTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
|
||||
@ -215,7 +212,7 @@ typedef union {
|
||||
|
||||
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
|
||||
#define PORT_IN_IN_Msk (0xFFFFFFFFul << PORT_IN_IN_Pos)
|
||||
#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
|
||||
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
|
||||
#define PORT_IN_MASK 0xFFFFFFFFul /**< \brief (PORT_IN) MASK Register */
|
||||
|
||||
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
|
||||
@ -233,7 +230,7 @@ typedef union {
|
||||
|
||||
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
|
||||
#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFul << PORT_CTRL_SAMPLING_Pos)
|
||||
#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
|
||||
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
|
||||
#define PORT_CTRL_MASK 0xFFFFFFFFul /**< \brief (PORT_CTRL) MASK Register */
|
||||
|
||||
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
|
||||
@ -262,7 +259,7 @@ typedef union {
|
||||
|
||||
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
|
||||
#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFul << PORT_WRCONFIG_PINMASK_Pos)
|
||||
#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
|
||||
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
|
||||
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
|
||||
#define PORT_WRCONFIG_PMUXEN (0x1ul << PORT_WRCONFIG_PMUXEN_Pos)
|
||||
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
|
||||
@ -273,7 +270,7 @@ typedef union {
|
||||
#define PORT_WRCONFIG_DRVSTR (0x1ul << PORT_WRCONFIG_DRVSTR_Pos)
|
||||
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
|
||||
#define PORT_WRCONFIG_PMUX_Msk (0xFul << PORT_WRCONFIG_PMUX_Pos)
|
||||
#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
|
||||
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
|
||||
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
|
||||
#define PORT_WRCONFIG_WRPMUX (0x1ul << PORT_WRCONFIG_WRPMUX_Pos)
|
||||
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
|
||||
@ -298,7 +295,7 @@ typedef union {
|
||||
|
||||
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
|
||||
#define PORT_PMUX_PMUXE_Msk (0xFul << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
|
||||
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
|
||||
#define PORT_PMUX_PMUXE_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXE_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXE_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
@ -317,7 +314,7 @@ typedef union {
|
||||
#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
|
||||
#define PORT_PMUX_PMUXO_Msk (0xFul << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
|
||||
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
|
||||
#define PORT_PMUX_PMUXO_A_Val 0x0ul /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXO_B_Val 0x1ul /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXO_C_Val 0x2ul /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
@ -391,7 +388,6 @@ typedef struct {
|
||||
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
|
||||
} Port;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#define SECTION_PORT_IOBUS
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for RTC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_COMPONENT_
|
||||
#define _SAMD21_RTC_COMPONENT_
|
||||
@ -81,7 +78,7 @@ typedef union {
|
||||
#define RTC_MODE0_CTRL_ENABLE (0x1ul << RTC_MODE0_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */
|
||||
#define RTC_MODE0_CTRL_MODE_Msk (0x3ul << RTC_MODE0_CTRL_MODE_Pos)
|
||||
#define RTC_MODE0_CTRL_MODE(value) ((RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos))
|
||||
#define RTC_MODE0_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE0_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE0_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */
|
||||
@ -92,7 +89,7 @@ typedef union {
|
||||
#define RTC_MODE0_CTRL_MATCHCLR (0x1ul << RTC_MODE0_CTRL_MATCHCLR_Pos)
|
||||
#define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_Msk (0xFul << RTC_MODE0_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE0_CTRL_PRESCALER(value) ((RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE0_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
@ -141,7 +138,7 @@ typedef union {
|
||||
#define RTC_MODE1_CTRL_ENABLE (0x1ul << RTC_MODE1_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */
|
||||
#define RTC_MODE1_CTRL_MODE_Msk (0x3ul << RTC_MODE1_CTRL_MODE_Pos)
|
||||
#define RTC_MODE1_CTRL_MODE(value) ((RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos))
|
||||
#define RTC_MODE1_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE1_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE1_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */
|
||||
@ -150,7 +147,7 @@ typedef union {
|
||||
#define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos)
|
||||
#define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_Msk (0xFul << RTC_MODE1_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE1_CTRL_PRESCALER(value) ((RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE1_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
@ -201,7 +198,7 @@ typedef union {
|
||||
#define RTC_MODE2_CTRL_ENABLE (0x1ul << RTC_MODE2_CTRL_ENABLE_Pos)
|
||||
#define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */
|
||||
#define RTC_MODE2_CTRL_MODE_Msk (0x3ul << RTC_MODE2_CTRL_MODE_Pos)
|
||||
#define RTC_MODE2_CTRL_MODE(value) ((RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)))
|
||||
#define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos))
|
||||
#define RTC_MODE2_CTRL_MODE_COUNT32_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */
|
||||
#define RTC_MODE2_CTRL_MODE_COUNT16_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */
|
||||
#define RTC_MODE2_CTRL_MODE_CLOCK_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */
|
||||
@ -214,7 +211,7 @@ typedef union {
|
||||
#define RTC_MODE2_CTRL_MATCHCLR (0x1ul << RTC_MODE2_CTRL_MATCHCLR_Pos)
|
||||
#define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_Msk (0xFul << RTC_MODE2_CTRL_PRESCALER_Pos)
|
||||
#define RTC_MODE2_CTRL_PRESCALER(value) ((RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)))
|
||||
#define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos))
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV1_Val 0x0ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV2_Val 0x1ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */
|
||||
#define RTC_MODE2_CTRL_PRESCALER_DIV4_Val 0x2ul /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */
|
||||
@ -257,7 +254,7 @@ typedef union {
|
||||
|
||||
#define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */
|
||||
#define RTC_READREQ_ADDR_Msk (0x3Ful << RTC_READREQ_ADDR_Pos)
|
||||
#define RTC_READREQ_ADDR(value) ((RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)))
|
||||
#define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos))
|
||||
#define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */
|
||||
#define RTC_READREQ_RCONT (0x1ul << RTC_READREQ_RCONT_Pos)
|
||||
#define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */
|
||||
@ -310,12 +307,12 @@ typedef union {
|
||||
#define RTC_MODE0_EVCTRL_PEREO7 (1 << RTC_MODE0_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE0_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_PEREO(value) ((RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_CMPEO0 (1 << RTC_MODE0_EVCTRL_CMPEO0_Pos)
|
||||
#define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_CMPEO_Msk (0x1ul << RTC_MODE0_EVCTRL_CMPEO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_CMPEO(value) ((RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)))
|
||||
#define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos))
|
||||
#define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE0_EVCTRL_OVFEO (0x1ul << RTC_MODE0_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE0_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE0_EVCTRL) MASK Register */
|
||||
@ -367,14 +364,14 @@ typedef union {
|
||||
#define RTC_MODE1_EVCTRL_PEREO7 (1 << RTC_MODE1_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE1_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_PEREO(value) ((RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO0 (1 << RTC_MODE1_EVCTRL_CMPEO0_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO1 (1 << RTC_MODE1_EVCTRL_CMPEO1_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_CMPEO_Msk (0x3ul << RTC_MODE1_EVCTRL_CMPEO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_CMPEO(value) ((RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)))
|
||||
#define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos))
|
||||
#define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE1_EVCTRL_OVFEO (0x1ul << RTC_MODE1_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE1_EVCTRL_MASK 0x83FFul /**< \brief (RTC_MODE1_EVCTRL) MASK Register */
|
||||
@ -425,12 +422,12 @@ typedef union {
|
||||
#define RTC_MODE2_EVCTRL_PEREO7 (1 << RTC_MODE2_EVCTRL_PEREO7_Pos)
|
||||
#define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_PEREO_Msk (0xFFul << RTC_MODE2_EVCTRL_PEREO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_PEREO(value) ((RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)))
|
||||
#define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos))
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO0 (1 << RTC_MODE2_EVCTRL_ALARMEO0_Pos)
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO_Msk (0x1ul << RTC_MODE2_EVCTRL_ALARMEO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO(value) ((RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)))
|
||||
#define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos))
|
||||
#define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */
|
||||
#define RTC_MODE2_EVCTRL_OVFEO (0x1ul << RTC_MODE2_EVCTRL_OVFEO_Pos)
|
||||
#define RTC_MODE2_EVCTRL_MASK 0x81FFul /**< \brief (RTC_MODE2_EVCTRL) MASK Register */
|
||||
@ -459,7 +456,7 @@ typedef union {
|
||||
#define RTC_MODE0_INTENCLR_CMP0 (1 << RTC_MODE0_INTENCLR_CMP0_Pos)
|
||||
#define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */
|
||||
#define RTC_MODE0_INTENCLR_CMP_Msk (0x1ul << RTC_MODE0_INTENCLR_CMP_Pos)
|
||||
#define RTC_MODE0_INTENCLR_CMP(value) ((RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)))
|
||||
#define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos))
|
||||
#define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE0_INTENCLR_SYNCRDY (0x1ul << RTC_MODE0_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */
|
||||
@ -493,7 +490,7 @@ typedef union {
|
||||
#define RTC_MODE1_INTENCLR_CMP1 (1 << RTC_MODE1_INTENCLR_CMP1_Pos)
|
||||
#define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */
|
||||
#define RTC_MODE1_INTENCLR_CMP_Msk (0x3ul << RTC_MODE1_INTENCLR_CMP_Pos)
|
||||
#define RTC_MODE1_INTENCLR_CMP(value) ((RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)))
|
||||
#define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos))
|
||||
#define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE1_INTENCLR_SYNCRDY (0x1ul << RTC_MODE1_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */
|
||||
@ -524,7 +521,7 @@ typedef union {
|
||||
#define RTC_MODE2_INTENCLR_ALARM0 (1 << RTC_MODE2_INTENCLR_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */
|
||||
#define RTC_MODE2_INTENCLR_ALARM_Msk (0x1ul << RTC_MODE2_INTENCLR_ALARM_Pos)
|
||||
#define RTC_MODE2_INTENCLR_ALARM(value) ((RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos))
|
||||
#define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE2_INTENCLR_SYNCRDY (0x1ul << RTC_MODE2_INTENCLR_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */
|
||||
@ -555,7 +552,7 @@ typedef union {
|
||||
#define RTC_MODE0_INTENSET_CMP0 (1 << RTC_MODE0_INTENSET_CMP0_Pos)
|
||||
#define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */
|
||||
#define RTC_MODE0_INTENSET_CMP_Msk (0x1ul << RTC_MODE0_INTENSET_CMP_Pos)
|
||||
#define RTC_MODE0_INTENSET_CMP(value) ((RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)))
|
||||
#define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos))
|
||||
#define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE0_INTENSET_SYNCRDY (0x1ul << RTC_MODE0_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */
|
||||
@ -589,7 +586,7 @@ typedef union {
|
||||
#define RTC_MODE1_INTENSET_CMP1 (1 << RTC_MODE1_INTENSET_CMP1_Pos)
|
||||
#define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */
|
||||
#define RTC_MODE1_INTENSET_CMP_Msk (0x3ul << RTC_MODE1_INTENSET_CMP_Pos)
|
||||
#define RTC_MODE1_INTENSET_CMP(value) ((RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)))
|
||||
#define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos))
|
||||
#define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE1_INTENSET_SYNCRDY (0x1ul << RTC_MODE1_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */
|
||||
@ -620,7 +617,7 @@ typedef union {
|
||||
#define RTC_MODE2_INTENSET_ALARM0 (1 << RTC_MODE2_INTENSET_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */
|
||||
#define RTC_MODE2_INTENSET_ALARM_Msk (0x1ul << RTC_MODE2_INTENSET_ALARM_Pos)
|
||||
#define RTC_MODE2_INTENSET_ALARM(value) ((RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos))
|
||||
#define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define RTC_MODE2_INTENSET_SYNCRDY (0x1ul << RTC_MODE2_INTENSET_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */
|
||||
@ -629,16 +626,16 @@ typedef union {
|
||||
|
||||
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t CMP:1; /*!< bit: 0 Compare x */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t CMP:1; /*!< bit: 0 Compare x */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE0_INTFLAG_Type;
|
||||
@ -651,7 +648,7 @@ typedef union {
|
||||
#define RTC_MODE0_INTFLAG_CMP0 (1 << RTC_MODE0_INTFLAG_CMP0_Pos)
|
||||
#define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */
|
||||
#define RTC_MODE0_INTFLAG_CMP_Msk (0x1ul << RTC_MODE0_INTFLAG_CMP_Pos)
|
||||
#define RTC_MODE0_INTFLAG_CMP(value) ((RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)))
|
||||
#define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos))
|
||||
#define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE0_INTFLAG_SYNCRDY (0x1ul << RTC_MODE0_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */
|
||||
@ -660,17 +657,17 @@ typedef union {
|
||||
|
||||
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
|
||||
uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
|
||||
__I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
|
||||
__I uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
__I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE1_INTFLAG_Type;
|
||||
@ -685,7 +682,7 @@ typedef union {
|
||||
#define RTC_MODE1_INTFLAG_CMP1 (1 << RTC_MODE1_INTFLAG_CMP1_Pos)
|
||||
#define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */
|
||||
#define RTC_MODE1_INTFLAG_CMP_Msk (0x3ul << RTC_MODE1_INTFLAG_CMP_Pos)
|
||||
#define RTC_MODE1_INTFLAG_CMP(value) ((RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)))
|
||||
#define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos))
|
||||
#define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE1_INTFLAG_SYNCRDY (0x1ul << RTC_MODE1_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */
|
||||
@ -694,16 +691,16 @@ typedef union {
|
||||
|
||||
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
|
||||
uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
__I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
|
||||
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
|
||||
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} RTC_MODE2_INTFLAG_Type;
|
||||
@ -716,7 +713,7 @@ typedef union {
|
||||
#define RTC_MODE2_INTFLAG_ALARM0 (1 << RTC_MODE2_INTFLAG_ALARM0_Pos)
|
||||
#define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */
|
||||
#define RTC_MODE2_INTFLAG_ALARM_Msk (0x1ul << RTC_MODE2_INTFLAG_ALARM_Pos)
|
||||
#define RTC_MODE2_INTFLAG_ALARM(value) ((RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)))
|
||||
#define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos))
|
||||
#define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */
|
||||
#define RTC_MODE2_INTFLAG_SYNCRDY (0x1ul << RTC_MODE2_INTFLAG_SYNCRDY_Pos)
|
||||
#define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */
|
||||
@ -775,7 +772,7 @@ typedef union {
|
||||
|
||||
#define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */
|
||||
#define RTC_FREQCORR_VALUE_Msk (0x7Ful << RTC_FREQCORR_VALUE_Pos)
|
||||
#define RTC_FREQCORR_VALUE(value) ((RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)))
|
||||
#define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos))
|
||||
#define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */
|
||||
#define RTC_FREQCORR_SIGN (0x1ul << RTC_FREQCORR_SIGN_Pos)
|
||||
#define RTC_FREQCORR_MASK 0xFFul /**< \brief (RTC_FREQCORR) MASK Register */
|
||||
@ -795,7 +792,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */
|
||||
#define RTC_MODE0_COUNT_COUNT_Msk (0xFFFFFFFFul << RTC_MODE0_COUNT_COUNT_Pos)
|
||||
#define RTC_MODE0_COUNT_COUNT(value) ((RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)))
|
||||
#define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos))
|
||||
#define RTC_MODE0_COUNT_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COUNT) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
|
||||
@ -813,7 +810,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */
|
||||
#define RTC_MODE1_COUNT_COUNT_Msk (0xFFFFul << RTC_MODE1_COUNT_COUNT_Pos)
|
||||
#define RTC_MODE1_COUNT_COUNT(value) ((RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)))
|
||||
#define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos))
|
||||
#define RTC_MODE1_COUNT_MASK 0xFFFFul /**< \brief (RTC_MODE1_COUNT) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
|
||||
@ -836,24 +833,26 @@ typedef union {
|
||||
|
||||
#define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */
|
||||
#define RTC_MODE2_CLOCK_SECOND_Msk (0x3Ful << RTC_MODE2_CLOCK_SECOND_Pos)
|
||||
#define RTC_MODE2_CLOCK_SECOND(value) ((RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)))
|
||||
#define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos))
|
||||
#define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */
|
||||
#define RTC_MODE2_CLOCK_MINUTE_Msk (0x3Ful << RTC_MODE2_CLOCK_MINUTE_Pos)
|
||||
#define RTC_MODE2_CLOCK_MINUTE(value) ((RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)))
|
||||
#define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos))
|
||||
#define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR_Msk (0x1Ful << RTC_MODE2_CLOCK_HOUR_Pos)
|
||||
#define RTC_MODE2_CLOCK_HOUR(value) ((RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)))
|
||||
#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos))
|
||||
#define RTC_MODE2_CLOCK_HOUR_AM_Val 0x0ul /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_CLOCK) PM when CLKREP in 12-hour */
|
||||
#define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
||||
#define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos)
|
||||
#define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */
|
||||
#define RTC_MODE2_CLOCK_DAY_Msk (0x1Ful << RTC_MODE2_CLOCK_DAY_Pos)
|
||||
#define RTC_MODE2_CLOCK_DAY(value) ((RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)))
|
||||
#define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos))
|
||||
#define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */
|
||||
#define RTC_MODE2_CLOCK_MONTH_Msk (0xFul << RTC_MODE2_CLOCK_MONTH_Pos)
|
||||
#define RTC_MODE2_CLOCK_MONTH(value) ((RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)))
|
||||
#define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos))
|
||||
#define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */
|
||||
#define RTC_MODE2_CLOCK_YEAR_Msk (0x3Ful << RTC_MODE2_CLOCK_YEAR_Pos)
|
||||
#define RTC_MODE2_CLOCK_YEAR(value) ((RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)))
|
||||
#define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos))
|
||||
#define RTC_MODE2_CLOCK_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_CLOCK) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
|
||||
@ -871,7 +870,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */
|
||||
#define RTC_MODE1_PER_PER_Msk (0xFFFFul << RTC_MODE1_PER_PER_Pos)
|
||||
#define RTC_MODE1_PER_PER(value) ((RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)))
|
||||
#define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos))
|
||||
#define RTC_MODE1_PER_MASK 0xFFFFul /**< \brief (RTC_MODE1_PER) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
|
||||
@ -889,7 +888,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */
|
||||
#define RTC_MODE0_COMP_COMP_Msk (0xFFFFFFFFul << RTC_MODE0_COMP_COMP_Pos)
|
||||
#define RTC_MODE0_COMP_COMP(value) ((RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)))
|
||||
#define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos))
|
||||
#define RTC_MODE0_COMP_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE0_COMP) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
|
||||
@ -907,7 +906,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */
|
||||
#define RTC_MODE1_COMP_COMP_Msk (0xFFFFul << RTC_MODE1_COMP_COMP_Pos)
|
||||
#define RTC_MODE1_COMP_COMP(value) ((RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)))
|
||||
#define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos))
|
||||
#define RTC_MODE1_COMP_MASK 0xFFFFul /**< \brief (RTC_MODE1_COMP) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
|
||||
@ -930,22 +929,26 @@ typedef union {
|
||||
|
||||
#define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */
|
||||
#define RTC_MODE2_ALARM_SECOND_Msk (0x3Ful << RTC_MODE2_ALARM_SECOND_Pos)
|
||||
#define RTC_MODE2_ALARM_SECOND(value) ((RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)))
|
||||
#define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos))
|
||||
#define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */
|
||||
#define RTC_MODE2_ALARM_MINUTE_Msk (0x3Ful << RTC_MODE2_ALARM_MINUTE_Pos)
|
||||
#define RTC_MODE2_ALARM_MINUTE(value) ((RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)))
|
||||
#define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos))
|
||||
#define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */
|
||||
#define RTC_MODE2_ALARM_HOUR_Msk (0x1Ful << RTC_MODE2_ALARM_HOUR_Pos)
|
||||
#define RTC_MODE2_ALARM_HOUR(value) ((RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)))
|
||||
#define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos))
|
||||
#define RTC_MODE2_ALARM_HOUR_AM_Val 0x0ul /**< \brief (RTC_MODE2_ALARM) Morning hour */
|
||||
#define RTC_MODE2_ALARM_HOUR_PM_Val 0x10ul /**< \brief (RTC_MODE2_ALARM) Afternoon hour */
|
||||
#define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos)
|
||||
#define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos)
|
||||
#define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */
|
||||
#define RTC_MODE2_ALARM_DAY_Msk (0x1Ful << RTC_MODE2_ALARM_DAY_Pos)
|
||||
#define RTC_MODE2_ALARM_DAY(value) ((RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)))
|
||||
#define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos))
|
||||
#define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */
|
||||
#define RTC_MODE2_ALARM_MONTH_Msk (0xFul << RTC_MODE2_ALARM_MONTH_Pos)
|
||||
#define RTC_MODE2_ALARM_MONTH(value) ((RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)))
|
||||
#define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos))
|
||||
#define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */
|
||||
#define RTC_MODE2_ALARM_YEAR_Msk (0x3Ful << RTC_MODE2_ALARM_YEAR_Pos)
|
||||
#define RTC_MODE2_ALARM_YEAR(value) ((RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)))
|
||||
#define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos))
|
||||
#define RTC_MODE2_ALARM_MASK 0xFFFFFFFFul /**< \brief (RTC_MODE2_ALARM) MASK Register */
|
||||
|
||||
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
|
||||
@ -964,7 +967,7 @@ typedef union {
|
||||
|
||||
#define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */
|
||||
#define RTC_MODE2_MASK_SEL_Msk (0x7ul << RTC_MODE2_MASK_SEL_Pos)
|
||||
#define RTC_MODE2_MASK_SEL(value) ((RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)))
|
||||
#define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos))
|
||||
#define RTC_MODE2_MASK_SEL_OFF_Val 0x0ul /**< \brief (RTC_MODE2_MASK) Alarm Disabled */
|
||||
#define RTC_MODE2_MASK_SEL_SS_Val 0x1ul /**< \brief (RTC_MODE2_MASK) Match seconds only */
|
||||
#define RTC_MODE2_MASK_SEL_MMSS_Val 0x2ul /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for SERCOM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM_COMPONENT_
|
||||
#define _SAMD21_SERCOM_COMPONENT_
|
||||
@ -54,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define SERCOM_U2201
|
||||
#define REV_SERCOM 0x201
|
||||
#define REV_SERCOM 0x220
|
||||
|
||||
/* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -91,7 +88,7 @@ typedef union {
|
||||
#define SERCOM_I2CM_CTRLA_ENABLE (0x1ul << SERCOM_I2CM_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CM_CTRLA_MODE_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MODE(value) ((SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */
|
||||
@ -110,19 +107,19 @@ typedef union {
|
||||
#define SERCOM_I2CM_CTRLA_PINOUT (0x1ul << SERCOM_I2CM_CTRLA_PINOUT_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD(value) ((SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CM_CTRLA_MEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CM_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */
|
||||
#define SERCOM_I2CM_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CM_CTRLA_SPEED_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_SPEED(value) ((SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */
|
||||
#define SERCOM_I2CM_CTRLA_SCLSM (0x1ul << SERCOM_I2CM_CTRLA_SCLSM_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT_Msk (0x3ul << SERCOM_I2CM_CTRLA_INACTOUT_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT(value) ((SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)))
|
||||
#define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
|
||||
#define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */
|
||||
#define SERCOM_I2CM_CTRLA_LOWTOUTEN (0x1ul << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLA_MASK 0x7BF1009Ful /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */
|
||||
@ -162,7 +159,7 @@ typedef union {
|
||||
#define SERCOM_I2CS_CTRLA_ENABLE (0x1ul << SERCOM_I2CS_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_Msk (0x7ul << SERCOM_I2CS_CTRLA_MODE_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_MODE(value) ((SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */
|
||||
@ -181,12 +178,12 @@ typedef union {
|
||||
#define SERCOM_I2CS_CTRLA_PINOUT (0x1ul << SERCOM_I2CS_CTRLA_PINOUT_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (0x3ul << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD(value) ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */
|
||||
#define SERCOM_I2CS_CTRLA_SEXTTOEN (0x1ul << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */
|
||||
#define SERCOM_I2CS_CTRLA_SPEED_Msk (0x3ul << SERCOM_I2CS_CTRLA_SPEED_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_SPEED(value) ((SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)))
|
||||
#define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
|
||||
#define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */
|
||||
#define SERCOM_I2CS_CTRLA_SCLSM (0x1ul << SERCOM_I2CS_CTRLA_SCLSM_Pos)
|
||||
#define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */
|
||||
@ -227,7 +224,7 @@ typedef union {
|
||||
#define SERCOM_SPI_CTRLA_ENABLE (0x1ul << SERCOM_SPI_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */
|
||||
#define SERCOM_SPI_CTRLA_MODE_Msk (0x7ul << SERCOM_SPI_CTRLA_MODE_Pos)
|
||||
#define SERCOM_SPI_CTRLA_MODE(value) ((SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos))
|
||||
#define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */
|
||||
@ -246,13 +243,13 @@ typedef union {
|
||||
#define SERCOM_SPI_CTRLA_IBON (0x1ul << SERCOM_SPI_CTRLA_IBON_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */
|
||||
#define SERCOM_SPI_CTRLA_DOPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DOPO_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DOPO(value) ((SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos))
|
||||
#define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */
|
||||
#define SERCOM_SPI_CTRLA_DIPO_Msk (0x3ul << SERCOM_SPI_CTRLA_DIPO_Pos)
|
||||
#define SERCOM_SPI_CTRLA_DIPO(value) ((SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos))
|
||||
#define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */
|
||||
#define SERCOM_SPI_CTRLA_FORM_Msk (0xFul << SERCOM_SPI_CTRLA_FORM_Pos)
|
||||
#define SERCOM_SPI_CTRLA_FORM(value) ((SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)))
|
||||
#define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos))
|
||||
#define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */
|
||||
#define SERCOM_SPI_CTRLA_CPHA (0x1ul << SERCOM_SPI_CTRLA_CPHA_Pos)
|
||||
#define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */
|
||||
@ -296,7 +293,7 @@ typedef union {
|
||||
#define SERCOM_USART_CTRLA_ENABLE (0x1ul << SERCOM_USART_CTRLA_ENABLE_Pos)
|
||||
#define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */
|
||||
#define SERCOM_USART_CTRLA_MODE_Msk (0x7ul << SERCOM_USART_CTRLA_MODE_Pos)
|
||||
#define SERCOM_USART_CTRLA_MODE(value) ((SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)))
|
||||
#define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos))
|
||||
#define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val 0x0ul /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */
|
||||
#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val 0x1ul /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */
|
||||
#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val 0x2ul /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */
|
||||
@ -315,19 +312,19 @@ typedef union {
|
||||
#define SERCOM_USART_CTRLA_IBON (0x1ul << SERCOM_USART_CTRLA_IBON_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */
|
||||
#define SERCOM_USART_CTRLA_SAMPR_Msk (0x7ul << SERCOM_USART_CTRLA_SAMPR_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPR(value) ((SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)))
|
||||
#define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos))
|
||||
#define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */
|
||||
#define SERCOM_USART_CTRLA_TXPO_Msk (0x3ul << SERCOM_USART_CTRLA_TXPO_Pos)
|
||||
#define SERCOM_USART_CTRLA_TXPO(value) ((SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)))
|
||||
#define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos))
|
||||
#define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */
|
||||
#define SERCOM_USART_CTRLA_RXPO_Msk (0x3ul << SERCOM_USART_CTRLA_RXPO_Pos)
|
||||
#define SERCOM_USART_CTRLA_RXPO(value) ((SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)))
|
||||
#define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos))
|
||||
#define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */
|
||||
#define SERCOM_USART_CTRLA_SAMPA_Msk (0x3ul << SERCOM_USART_CTRLA_SAMPA_Pos)
|
||||
#define SERCOM_USART_CTRLA_SAMPA(value) ((SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)))
|
||||
#define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos))
|
||||
#define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */
|
||||
#define SERCOM_USART_CTRLA_FORM_Msk (0xFul << SERCOM_USART_CTRLA_FORM_Pos)
|
||||
#define SERCOM_USART_CTRLA_FORM(value) ((SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)))
|
||||
#define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos))
|
||||
#define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */
|
||||
#define SERCOM_USART_CTRLA_CMODE (0x1ul << SERCOM_USART_CTRLA_CMODE_Pos)
|
||||
#define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */
|
||||
@ -361,7 +358,7 @@ typedef union {
|
||||
#define SERCOM_I2CM_CTRLB_QCEN (0x1ul << SERCOM_I2CM_CTRLB_QCEN_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */
|
||||
#define SERCOM_I2CM_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CM_CTRLB_CMD_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_CMD(value) ((SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)))
|
||||
#define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
|
||||
#define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */
|
||||
#define SERCOM_I2CM_CTRLB_ACKACT (0x1ul << SERCOM_I2CM_CTRLB_ACKACT_Pos)
|
||||
#define SERCOM_I2CM_CTRLB_MASK 0x00070300ul /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */
|
||||
@ -395,10 +392,10 @@ typedef union {
|
||||
#define SERCOM_I2CS_CTRLB_AACKEN (0x1ul << SERCOM_I2CS_CTRLB_AACKEN_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */
|
||||
#define SERCOM_I2CS_CTRLB_AMODE_Msk (0x3ul << SERCOM_I2CS_CTRLB_AMODE_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_AMODE(value) ((SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)))
|
||||
#define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
|
||||
#define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */
|
||||
#define SERCOM_I2CS_CTRLB_CMD_Msk (0x3ul << SERCOM_I2CS_CTRLB_CMD_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_CMD(value) ((SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)))
|
||||
#define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
|
||||
#define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */
|
||||
#define SERCOM_I2CS_CTRLB_ACKACT (0x1ul << SERCOM_I2CS_CTRLB_ACKACT_Pos)
|
||||
#define SERCOM_I2CS_CTRLB_MASK 0x0007C700ul /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */
|
||||
@ -428,7 +425,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_SPI_CTRLB_CHSIZE_Pos)
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE(value) ((SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)))
|
||||
#define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos))
|
||||
#define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */
|
||||
#define SERCOM_SPI_CTRLB_PLOADEN (0x1ul << SERCOM_SPI_CTRLB_PLOADEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */
|
||||
@ -437,7 +434,7 @@ typedef union {
|
||||
#define SERCOM_SPI_CTRLB_MSSEN (0x1ul << SERCOM_SPI_CTRLB_MSSEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */
|
||||
#define SERCOM_SPI_CTRLB_AMODE_Msk (0x3ul << SERCOM_SPI_CTRLB_AMODE_Pos)
|
||||
#define SERCOM_SPI_CTRLB_AMODE(value) ((SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)))
|
||||
#define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos))
|
||||
#define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */
|
||||
#define SERCOM_SPI_CTRLB_RXEN (0x1ul << SERCOM_SPI_CTRLB_RXEN_Pos)
|
||||
#define SERCOM_SPI_CTRLB_MASK 0x0002E247ul /**< \brief (SERCOM_SPI_CTRLB) MASK Register */
|
||||
@ -469,7 +466,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */
|
||||
#define SERCOM_USART_CTRLB_CHSIZE_Msk (0x7ul << SERCOM_USART_CTRLB_CHSIZE_Pos)
|
||||
#define SERCOM_USART_CTRLB_CHSIZE(value) ((SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)))
|
||||
#define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos))
|
||||
#define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */
|
||||
#define SERCOM_USART_CTRLB_SBMODE (0x1ul << SERCOM_USART_CTRLB_SBMODE_Pos)
|
||||
#define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */
|
||||
@ -504,16 +501,16 @@ typedef union {
|
||||
|
||||
#define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */
|
||||
#define SERCOM_I2CM_BAUD_BAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUD_Pos)
|
||||
#define SERCOM_I2CM_BAUD_BAUD(value) ((SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_BAUDLOW_Pos)
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW(value) ((SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUD_Pos)
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD(value) ((SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (0xFFul << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) ((SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)))
|
||||
#define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
|
||||
#define SERCOM_I2CM_BAUD_MASK 0xFFFFFFFFul /**< \brief (SERCOM_I2CM_BAUD) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */
|
||||
@ -531,7 +528,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */
|
||||
#define SERCOM_SPI_BAUD_BAUD_Msk (0xFFul << SERCOM_SPI_BAUD_BAUD_Pos)
|
||||
#define SERCOM_SPI_BAUD_BAUD(value) ((SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos))
|
||||
#define SERCOM_SPI_BAUD_MASK 0xFFul /**< \brief (SERCOM_SPI_BAUD) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */
|
||||
@ -560,31 +557,31 @@ typedef union {
|
||||
|
||||
#define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_BAUD(value) ((SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD) MASK Register */
|
||||
|
||||
// FRAC mode
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD(value) ((SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */
|
||||
#define SERCOM_USART_BAUD_FRAC_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRAC_FP_Pos)
|
||||
#define SERCOM_USART_BAUD_FRAC_FP(value) ((SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
|
||||
#define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
|
||||
|
||||
// FRACFP mode
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD(value) ((SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP_Msk (0x7ul << SERCOM_USART_BAUD_FRACFP_FP_Pos)
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP(value) ((SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)))
|
||||
#define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
|
||||
#define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
|
||||
|
||||
// USARTFP mode
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD(value) ((SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)))
|
||||
#define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
|
||||
#define SERCOM_USART_BAUD_USARTFP_MASK 0xFFFFul /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */
|
||||
@ -602,7 +599,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */
|
||||
#define SERCOM_USART_RXPL_RXPL_Msk (0xFFul << SERCOM_USART_RXPL_RXPL_Pos)
|
||||
#define SERCOM_USART_RXPL_RXPL(value) ((SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)))
|
||||
#define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos))
|
||||
#define SERCOM_USART_RXPL_MASK 0xFFul /**< \brief (SERCOM_USART_RXPL) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */
|
||||
@ -841,12 +838,12 @@ typedef union {
|
||||
|
||||
/* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
|
||||
uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
|
||||
uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */
|
||||
__I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */
|
||||
__I uint8_t :5; /*!< bit: 2.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_I2CM_INTFLAG_Type;
|
||||
@ -865,13 +862,13 @@ typedef union {
|
||||
|
||||
/* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
|
||||
uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
|
||||
uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
|
||||
uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */
|
||||
__I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */
|
||||
__I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */
|
||||
__I uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_I2CS_INTFLAG_Type;
|
||||
@ -892,14 +889,14 @@ typedef union {
|
||||
|
||||
/* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
|
||||
uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
__I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
__I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
__I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */
|
||||
__I uint8_t :3; /*!< bit: 4.. 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_SPI_INTFLAG_Type;
|
||||
@ -922,16 +919,16 @@ typedef union {
|
||||
|
||||
/* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
|
||||
uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
|
||||
uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
|
||||
uint8_t :1; /*!< bit: 6 Reserved */
|
||||
uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
__I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */
|
||||
__I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */
|
||||
__I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */
|
||||
__I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */
|
||||
__I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */
|
||||
__I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */
|
||||
__I uint8_t :1; /*!< bit: 6 Reserved */
|
||||
__I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} SERCOM_USART_INTFLAG_Type;
|
||||
@ -987,7 +984,7 @@ typedef union {
|
||||
#define SERCOM_I2CM_STATUS_RXNACK (0x1ul << SERCOM_I2CM_STATUS_RXNACK_Pos)
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE_Msk (0x3ul << SERCOM_I2CM_STATUS_BUSSTATE_Pos)
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE(value) ((SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)))
|
||||
#define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
|
||||
#define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */
|
||||
#define SERCOM_I2CM_STATUS_LOWTOUT (0x1ul << SERCOM_I2CM_STATUS_LOWTOUT_Pos)
|
||||
#define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */
|
||||
@ -1096,7 +1093,7 @@ typedef union {
|
||||
#define SERCOM_USART_STATUS_COLL (0x1ul << SERCOM_USART_STATUS_COLL_Pos)
|
||||
#define SERCOM_USART_STATUS_MASK 0x003Ful /**< \brief (SERCOM_USART_STATUS) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */
|
||||
/* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
@ -1109,8 +1106,8 @@ typedef union {
|
||||
} SERCOM_I2CM_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */
|
||||
#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */
|
||||
#define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */
|
||||
#define SERCOM_I2CM_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */
|
||||
|
||||
#define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */
|
||||
#define SERCOM_I2CM_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)
|
||||
@ -1120,7 +1117,7 @@ typedef union {
|
||||
#define SERCOM_I2CM_SYNCBUSY_SYSOP (0x1ul << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)
|
||||
#define SERCOM_I2CM_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */
|
||||
/* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
@ -1132,8 +1129,8 @@ typedef union {
|
||||
} SERCOM_I2CS_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */
|
||||
#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */
|
||||
#define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */
|
||||
#define SERCOM_I2CS_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */
|
||||
|
||||
#define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */
|
||||
#define SERCOM_I2CS_SYNCBUSY_SWRST (0x1ul << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)
|
||||
@ -1141,7 +1138,7 @@ typedef union {
|
||||
#define SERCOM_I2CS_SYNCBUSY_ENABLE (0x1ul << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)
|
||||
#define SERCOM_I2CS_SYNCBUSY_MASK 0x00000003ul /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */
|
||||
/* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
@ -1154,8 +1151,8 @@ typedef union {
|
||||
} SERCOM_SPI_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */
|
||||
#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */
|
||||
#define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */
|
||||
#define SERCOM_SPI_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */
|
||||
|
||||
#define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */
|
||||
#define SERCOM_SPI_SYNCBUSY_SWRST (0x1ul << SERCOM_SPI_SYNCBUSY_SWRST_Pos)
|
||||
@ -1165,7 +1162,7 @@ typedef union {
|
||||
#define SERCOM_SPI_SYNCBUSY_CTRLB (0x1ul << SERCOM_SPI_SYNCBUSY_CTRLB_Pos)
|
||||
#define SERCOM_SPI_SYNCBUSY_MASK 0x00000007ul /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */
|
||||
/* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
@ -1178,8 +1175,8 @@ typedef union {
|
||||
} SERCOM_USART_SYNCBUSY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */
|
||||
#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */
|
||||
#define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */
|
||||
#define SERCOM_USART_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */
|
||||
|
||||
#define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */
|
||||
#define SERCOM_USART_SYNCBUSY_SWRST (0x1ul << SERCOM_USART_SYNCBUSY_SWRST_Pos)
|
||||
@ -1210,7 +1207,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */
|
||||
#define SERCOM_I2CM_ADDR_ADDR_Msk (0x7FFul << SERCOM_I2CM_ADDR_ADDR_Pos)
|
||||
#define SERCOM_I2CM_ADDR_ADDR(value) ((SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
|
||||
#define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */
|
||||
#define SERCOM_I2CM_ADDR_LENEN (0x1ul << SERCOM_I2CM_ADDR_LENEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */
|
||||
@ -1219,7 +1216,7 @@ typedef union {
|
||||
#define SERCOM_I2CM_ADDR_TENBITEN (0x1ul << SERCOM_I2CM_ADDR_TENBITEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */
|
||||
#define SERCOM_I2CM_ADDR_LEN_Msk (0xFFul << SERCOM_I2CM_ADDR_LEN_Pos)
|
||||
#define SERCOM_I2CM_ADDR_LEN(value) ((SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)))
|
||||
#define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
|
||||
#define SERCOM_I2CM_ADDR_MASK 0x00FFE7FFul /**< \brief (SERCOM_I2CM_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */
|
||||
@ -1245,12 +1242,12 @@ typedef union {
|
||||
#define SERCOM_I2CS_ADDR_GENCEN (0x1ul << SERCOM_I2CS_ADDR_GENCEN_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */
|
||||
#define SERCOM_I2CS_ADDR_ADDR_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDR_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDR(value) ((SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
|
||||
#define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */
|
||||
#define SERCOM_I2CS_ADDR_TENBITEN (0x1ul << SERCOM_I2CS_ADDR_TENBITEN_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK_Msk (0x3FFul << SERCOM_I2CS_ADDR_ADDRMASK_Pos)
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK(value) ((SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)))
|
||||
#define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
|
||||
#define SERCOM_I2CS_ADDR_MASK 0x07FE87FFul /**< \brief (SERCOM_I2CS_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */
|
||||
@ -1271,10 +1268,10 @@ typedef union {
|
||||
|
||||
#define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */
|
||||
#define SERCOM_SPI_ADDR_ADDR_Msk (0xFFul << SERCOM_SPI_ADDR_ADDR_Pos)
|
||||
#define SERCOM_SPI_ADDR_ADDR(value) ((SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)))
|
||||
#define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos))
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK_Msk (0xFFul << SERCOM_SPI_ADDR_ADDRMASK_Pos)
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK(value) ((SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)))
|
||||
#define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos))
|
||||
#define SERCOM_SPI_ADDR_MASK 0x00FF00FFul /**< \brief (SERCOM_SPI_ADDR) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */
|
||||
@ -1292,7 +1289,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */
|
||||
#define SERCOM_I2CM_DATA_DATA_Msk (0xFFul << SERCOM_I2CM_DATA_DATA_Pos)
|
||||
#define SERCOM_I2CM_DATA_DATA(value) ((SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)))
|
||||
#define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
|
||||
#define SERCOM_I2CM_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CM_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */
|
||||
@ -1310,7 +1307,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */
|
||||
#define SERCOM_I2CS_DATA_DATA_Msk (0xFFul << SERCOM_I2CS_DATA_DATA_Pos)
|
||||
#define SERCOM_I2CS_DATA_DATA(value) ((SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)))
|
||||
#define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
|
||||
#define SERCOM_I2CS_DATA_MASK 0xFFul /**< \brief (SERCOM_I2CS_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */
|
||||
@ -1329,7 +1326,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */
|
||||
#define SERCOM_SPI_DATA_DATA_Msk (0x1FFul << SERCOM_SPI_DATA_DATA_Pos)
|
||||
#define SERCOM_SPI_DATA_DATA(value) ((SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)))
|
||||
#define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos))
|
||||
#define SERCOM_SPI_DATA_MASK 0x000001FFul /**< \brief (SERCOM_SPI_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */
|
||||
@ -1348,7 +1345,7 @@ typedef union {
|
||||
|
||||
#define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */
|
||||
#define SERCOM_USART_DATA_DATA_Msk (0x1FFul << SERCOM_USART_DATA_DATA_Pos)
|
||||
#define SERCOM_USART_DATA_DATA(value) ((SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)))
|
||||
#define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos))
|
||||
#define SERCOM_USART_DATA_MASK 0x01FFul /**< \brief (SERCOM_USART_DATA) MASK Register */
|
||||
|
||||
/* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */
|
||||
@ -1420,7 +1417,7 @@ typedef struct { /* I2C Master Mode */
|
||||
__IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved5[0x1];
|
||||
__IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */
|
||||
__I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */
|
||||
__I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */
|
||||
RoReg8 Reserved6[0x4];
|
||||
__IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */
|
||||
__IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */
|
||||
@ -1442,7 +1439,7 @@ typedef struct { /* I2C Slave Mode */
|
||||
__IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved4[0x1];
|
||||
__IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */
|
||||
__I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */
|
||||
__I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */
|
||||
RoReg8 Reserved5[0x4];
|
||||
__IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */
|
||||
__IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */
|
||||
@ -1464,7 +1461,7 @@ typedef struct { /* SPI Mode */
|
||||
__IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved5[0x1];
|
||||
__IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */
|
||||
__I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */
|
||||
__I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */
|
||||
RoReg8 Reserved6[0x4];
|
||||
__IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */
|
||||
__IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */
|
||||
@ -1489,7 +1486,7 @@ typedef struct { /* USART Mode */
|
||||
__IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */
|
||||
RoReg8 Reserved5[0x1];
|
||||
__IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */
|
||||
__I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */
|
||||
__I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */
|
||||
RoReg8 Reserved6[0x8];
|
||||
__IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */
|
||||
RoReg8 Reserved7[0x6];
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_COMPONENT_
|
||||
#define _SAMD21_SYSCTRL_COMPONENT_
|
||||
@ -180,25 +177,25 @@ typedef union {
|
||||
|
||||
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
|
||||
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
|
||||
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
|
||||
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
|
||||
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
|
||||
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
|
||||
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
|
||||
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
|
||||
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
|
||||
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
|
||||
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
|
||||
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
|
||||
uint32_t :3; /*!< bit: 12..14 Reserved */
|
||||
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
|
||||
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
|
||||
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
|
||||
uint32_t :14; /*!< bit: 18..31 Reserved */
|
||||
__I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
|
||||
__I uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
|
||||
__I uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
|
||||
__I uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
|
||||
__I uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
|
||||
__I uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
|
||||
__I uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
|
||||
__I uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
|
||||
__I uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
|
||||
__I uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
|
||||
__I uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
|
||||
__I uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
|
||||
__I uint32_t :3; /*!< bit: 12..14 Reserved */
|
||||
__I uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
|
||||
__I uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
|
||||
__I uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
|
||||
__I uint32_t :14; /*!< bit: 18..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} SYSCTRL_INTFLAG_Type;
|
||||
@ -331,7 +328,7 @@ typedef union {
|
||||
#define SYSCTRL_XOSC_ONDEMAND (0x1ul << SYSCTRL_XOSC_ONDEMAND_Pos)
|
||||
#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
|
||||
#define SYSCTRL_XOSC_GAIN_Msk (0x7ul << SYSCTRL_XOSC_GAIN_Pos)
|
||||
#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
|
||||
#define SYSCTRL_XOSC_GAIN(value) (SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos))
|
||||
#define SYSCTRL_XOSC_GAIN_0_Val 0x0ul /**< \brief (SYSCTRL_XOSC) 2MHz */
|
||||
#define SYSCTRL_XOSC_GAIN_1_Val 0x1ul /**< \brief (SYSCTRL_XOSC) 4MHz */
|
||||
#define SYSCTRL_XOSC_GAIN_2_Val 0x2ul /**< \brief (SYSCTRL_XOSC) 8MHz */
|
||||
@ -346,7 +343,7 @@ typedef union {
|
||||
#define SYSCTRL_XOSC_AMPGC (0x1ul << SYSCTRL_XOSC_AMPGC_Pos)
|
||||
#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
|
||||
#define SYSCTRL_XOSC_STARTUP_Msk (0xFul << SYSCTRL_XOSC_STARTUP_Pos)
|
||||
#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
|
||||
#define SYSCTRL_XOSC_STARTUP(value) (SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos))
|
||||
#define SYSCTRL_XOSC_MASK 0xFFC6ul /**< \brief (SYSCTRL_XOSC) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
|
||||
@ -389,7 +386,7 @@ typedef union {
|
||||
#define SYSCTRL_XOSC32K_ONDEMAND (0x1ul << SYSCTRL_XOSC32K_ONDEMAND_Pos)
|
||||
#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
|
||||
#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7ul << SYSCTRL_XOSC32K_STARTUP_Pos)
|
||||
#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
|
||||
#define SYSCTRL_XOSC32K_STARTUP(value) (SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos))
|
||||
#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
|
||||
#define SYSCTRL_XOSC32K_WRTLOCK (0x1ul << SYSCTRL_XOSC32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_XOSC32K_MASK 0x17FEul /**< \brief (SYSCTRL_XOSC32K) MASK Register */
|
||||
@ -431,12 +428,12 @@ typedef union {
|
||||
#define SYSCTRL_OSC32K_ONDEMAND (0x1ul << SYSCTRL_OSC32K_ONDEMAND_Pos)
|
||||
#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
|
||||
#define SYSCTRL_OSC32K_STARTUP_Msk (0x7ul << SYSCTRL_OSC32K_STARTUP_Pos)
|
||||
#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
|
||||
#define SYSCTRL_OSC32K_STARTUP(value) (SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos))
|
||||
#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
|
||||
#define SYSCTRL_OSC32K_WRTLOCK (0x1ul << SYSCTRL_OSC32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
|
||||
#define SYSCTRL_OSC32K_CALIB_Msk (0x7Ful << SYSCTRL_OSC32K_CALIB_Pos)
|
||||
#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
|
||||
#define SYSCTRL_OSC32K_CALIB(value) (SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos))
|
||||
#define SYSCTRL_OSC32K_MASK 0x007F17CEul /**< \brief (SYSCTRL_OSC32K) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
|
||||
@ -456,7 +453,7 @@ typedef union {
|
||||
|
||||
#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
|
||||
#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Ful << SYSCTRL_OSCULP32K_CALIB_Pos)
|
||||
#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
|
||||
#define SYSCTRL_OSCULP32K_CALIB(value) (SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos))
|
||||
#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
|
||||
#define SYSCTRL_OSCULP32K_WRTLOCK (0x1ul << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
|
||||
#define SYSCTRL_OSCULP32K_MASK 0x9Ful /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
|
||||
@ -491,7 +488,7 @@ typedef union {
|
||||
#define SYSCTRL_OSC8M_ONDEMAND (0x1ul << SYSCTRL_OSC8M_ONDEMAND_Pos)
|
||||
#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
|
||||
#define SYSCTRL_OSC8M_PRESC_Msk (0x3ul << SYSCTRL_OSC8M_PRESC_Pos)
|
||||
#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
|
||||
#define SYSCTRL_OSC8M_PRESC(value) (SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos))
|
||||
#define SYSCTRL_OSC8M_PRESC_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 1 */
|
||||
#define SYSCTRL_OSC8M_PRESC_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 2 */
|
||||
#define SYSCTRL_OSC8M_PRESC_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 4 */
|
||||
@ -502,10 +499,10 @@ typedef union {
|
||||
#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
|
||||
#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
|
||||
#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFul << SYSCTRL_OSC8M_CALIB_Pos)
|
||||
#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
|
||||
#define SYSCTRL_OSC8M_CALIB(value) (SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos))
|
||||
#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
|
||||
#define SYSCTRL_OSC8M_FRANGE_Msk (0x3ul << SYSCTRL_OSC8M_FRANGE_Pos)
|
||||
#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
|
||||
#define SYSCTRL_OSC8M_FRANGE(value) (SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos))
|
||||
#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0ul /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
|
||||
#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1ul /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
|
||||
#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2ul /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
|
||||
@ -582,13 +579,13 @@ typedef union {
|
||||
|
||||
#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
|
||||
#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFul << SYSCTRL_DFLLVAL_FINE_Pos)
|
||||
#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_FINE(value) (SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos))
|
||||
#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
|
||||
#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Ful << SYSCTRL_DFLLVAL_COARSE_Pos)
|
||||
#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_COARSE(value) (SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos))
|
||||
#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
|
||||
#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFul << SYSCTRL_DFLLVAL_DIFF_Pos)
|
||||
#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
|
||||
#define SYSCTRL_DFLLVAL_DIFF(value) (SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos))
|
||||
#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
|
||||
@ -608,13 +605,13 @@ typedef union {
|
||||
|
||||
#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
|
||||
#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFul << SYSCTRL_DFLLMUL_MUL_Pos)
|
||||
#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_MUL(value) (SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos))
|
||||
#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
|
||||
#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFul << SYSCTRL_DFLLMUL_FSTEP_Pos)
|
||||
#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_FSTEP(value) (SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos))
|
||||
#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
|
||||
#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Ful << SYSCTRL_DFLLMUL_CSTEP_Pos)
|
||||
#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
|
||||
#define SYSCTRL_DFLLMUL_CSTEP(value) (SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos))
|
||||
#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFul /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
|
||||
@ -666,7 +663,7 @@ typedef union {
|
||||
#define SYSCTRL_BOD33_HYST (0x1ul << SYSCTRL_BOD33_HYST_Pos)
|
||||
#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
|
||||
#define SYSCTRL_BOD33_ACTION_Msk (0x3ul << SYSCTRL_BOD33_ACTION_Pos)
|
||||
#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
|
||||
#define SYSCTRL_BOD33_ACTION(value) (SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos))
|
||||
#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SYSCTRL_BOD33) No action */
|
||||
#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
|
||||
#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2ul /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
|
||||
@ -681,7 +678,7 @@ typedef union {
|
||||
#define SYSCTRL_BOD33_CEN (0x1ul << SYSCTRL_BOD33_CEN_Pos)
|
||||
#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
|
||||
#define SYSCTRL_BOD33_PSEL_Msk (0xFul << SYSCTRL_BOD33_PSEL_Pos)
|
||||
#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
|
||||
#define SYSCTRL_BOD33_PSEL(value) (SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos))
|
||||
#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
|
||||
#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
|
||||
#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
|
||||
@ -716,7 +713,7 @@ typedef union {
|
||||
#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
|
||||
#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
|
||||
#define SYSCTRL_BOD33_LEVEL_Msk (0x3Ful << SYSCTRL_BOD33_LEVEL_Pos)
|
||||
#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
|
||||
#define SYSCTRL_BOD33_LEVEL(value) (SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos))
|
||||
#define SYSCTRL_BOD33_MASK 0x003FF35Eul /**< \brief (SYSCTRL_BOD33) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
|
||||
@ -766,7 +763,7 @@ typedef union {
|
||||
#define SYSCTRL_VREF_BGOUTEN (0x1ul << SYSCTRL_VREF_BGOUTEN_Pos)
|
||||
#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
|
||||
#define SYSCTRL_VREF_CALIB_Msk (0x7FFul << SYSCTRL_VREF_CALIB_Pos)
|
||||
#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
|
||||
#define SYSCTRL_VREF_CALIB(value) (SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos))
|
||||
#define SYSCTRL_VREF_MASK 0x07FF0006ul /**< \brief (SYSCTRL_VREF) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
|
||||
@ -812,10 +809,10 @@ typedef union {
|
||||
|
||||
#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
|
||||
#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFul << SYSCTRL_DPLLRATIO_LDR_Pos)
|
||||
#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
|
||||
#define SYSCTRL_DPLLRATIO_LDR(value) (SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos))
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFul << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
|
||||
#define SYSCTRL_DPLLRATIO_LDRFRAC(value) (SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos))
|
||||
#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFul /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
|
||||
@ -843,7 +840,7 @@ typedef union {
|
||||
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3ul << SYSCTRL_DPLLCTRLB_FILTER_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER(value) (SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
|
||||
#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
|
||||
@ -858,7 +855,7 @@ typedef union {
|
||||
#define SYSCTRL_DPLLCTRLB_WUF (0x1ul << SYSCTRL_DPLLCTRLB_WUF_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3ul << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK(value) (SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1ul /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2ul /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
|
||||
@ -867,7 +864,7 @@ typedef union {
|
||||
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7ul << SYSCTRL_DPLLCTRLB_LTIME_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME(value) (SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0ul /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
|
||||
#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5ul /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
|
||||
@ -882,7 +879,7 @@ typedef union {
|
||||
#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1ul << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
|
||||
#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFul << SYSCTRL_DPLLCTRLB_DIV_Pos)
|
||||
#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
|
||||
#define SYSCTRL_DPLLCTRLB_DIV(value) (SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos))
|
||||
#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Ful /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
|
||||
|
||||
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for TC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC_COMPONENT_
|
||||
#define _SAMD21_TC_COMPONENT_
|
||||
@ -84,7 +81,7 @@ typedef union {
|
||||
#define TC_CTRLA_ENABLE (0x1ul << TC_CTRLA_ENABLE_Pos)
|
||||
#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
|
||||
#define TC_CTRLA_MODE_Msk (0x3ul << TC_CTRLA_MODE_Pos)
|
||||
#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
|
||||
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
|
||||
#define TC_CTRLA_MODE_COUNT16_Val 0x0ul /**< \brief (TC_CTRLA) Counter in 16-bit mode */
|
||||
#define TC_CTRLA_MODE_COUNT8_Val 0x1ul /**< \brief (TC_CTRLA) Counter in 8-bit mode */
|
||||
#define TC_CTRLA_MODE_COUNT32_Val 0x2ul /**< \brief (TC_CTRLA) Counter in 32-bit mode */
|
||||
@ -93,7 +90,7 @@ typedef union {
|
||||
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
|
||||
#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
|
||||
#define TC_CTRLA_WAVEGEN_Msk (0x3ul << TC_CTRLA_WAVEGEN_Pos)
|
||||
#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
|
||||
#define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
|
||||
#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TC_CTRLA) */
|
||||
#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TC_CTRLA) */
|
||||
#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TC_CTRLA) */
|
||||
@ -104,7 +101,7 @@ typedef union {
|
||||
#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
|
||||
#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
|
||||
#define TC_CTRLA_PRESCALER_Msk (0x7ul << TC_CTRLA_PRESCALER_Pos)
|
||||
#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
|
||||
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
|
||||
#define TC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
|
||||
#define TC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
|
||||
#define TC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
|
||||
@ -125,7 +122,7 @@ typedef union {
|
||||
#define TC_CTRLA_RUNSTDBY (0x1ul << TC_CTRLA_RUNSTDBY_Pos)
|
||||
#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
|
||||
#define TC_CTRLA_PRESCSYNC_Msk (0x3ul << TC_CTRLA_PRESCSYNC_Pos)
|
||||
#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
|
||||
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
|
||||
#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
|
||||
#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
|
||||
#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
|
||||
@ -152,7 +149,7 @@ typedef union {
|
||||
|
||||
#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
|
||||
#define TC_READREQ_ADDR_Msk (0x1Ful << TC_READREQ_ADDR_Pos)
|
||||
#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
|
||||
#define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
|
||||
#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
|
||||
#define TC_READREQ_RCONT (0x1ul << TC_READREQ_RCONT_Pos)
|
||||
#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
|
||||
@ -182,7 +179,7 @@ typedef union {
|
||||
#define TC_CTRLBCLR_ONESHOT (0x1ul << TC_CTRLBCLR_ONESHOT_Pos)
|
||||
#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
|
||||
#define TC_CTRLBCLR_CMD_Msk (0x3ul << TC_CTRLBCLR_CMD_Pos)
|
||||
#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
|
||||
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
|
||||
#define TC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBCLR) No action */
|
||||
#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
|
||||
#define TC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBCLR) Force a stop */
|
||||
@ -214,7 +211,7 @@ typedef union {
|
||||
#define TC_CTRLBSET_ONESHOT (0x1ul << TC_CTRLBSET_ONESHOT_Pos)
|
||||
#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
|
||||
#define TC_CTRLBSET_CMD_Msk (0x3ul << TC_CTRLBSET_CMD_Pos)
|
||||
#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
|
||||
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
|
||||
#define TC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TC_CTRLBSET) No action */
|
||||
#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
|
||||
#define TC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TC_CTRLBSET) Force a stop */
|
||||
@ -253,14 +250,14 @@ typedef union {
|
||||
#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
|
||||
#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
|
||||
#define TC_CTRLC_INVEN_Msk (0x3ul << TC_CTRLC_INVEN_Pos)
|
||||
#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
|
||||
#define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos))
|
||||
#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
|
||||
#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
|
||||
#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
|
||||
#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
|
||||
#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
|
||||
#define TC_CTRLC_CPTEN_Msk (0x3ul << TC_CTRLC_CPTEN_Pos)
|
||||
#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
|
||||
#define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos))
|
||||
#define TC_CTRLC_MASK 0x33ul /**< \brief (TC_CTRLC) MASK Register */
|
||||
|
||||
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
|
||||
@ -310,7 +307,7 @@ typedef union {
|
||||
|
||||
#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
|
||||
#define TC_EVCTRL_EVACT_Msk (0x7ul << TC_EVCTRL_EVACT_Pos)
|
||||
#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
|
||||
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
|
||||
#define TC_EVCTRL_EVACT_OFF_Val 0x0ul /**< \brief (TC_EVCTRL) Event action disabled */
|
||||
#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1ul /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
|
||||
#define TC_EVCTRL_EVACT_COUNT_Val 0x2ul /**< \brief (TC_EVCTRL) Count on event */
|
||||
@ -335,7 +332,7 @@ typedef union {
|
||||
#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
|
||||
#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
||||
#define TC_EVCTRL_MCEO_Msk (0x3ul << TC_EVCTRL_MCEO_Pos)
|
||||
#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
|
||||
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
|
||||
#define TC_EVCTRL_MASK 0x3137ul /**< \brief (TC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
|
||||
@ -374,7 +371,7 @@ typedef union {
|
||||
#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
|
||||
#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
||||
#define TC_INTENCLR_MC_Msk (0x3ul << TC_INTENCLR_MC_Pos)
|
||||
#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
|
||||
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
|
||||
#define TC_INTENCLR_MASK 0x3Bul /**< \brief (TC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
|
||||
@ -413,25 +410,25 @@ typedef union {
|
||||
#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
|
||||
#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
||||
#define TC_INTENSET_MC_Msk (0x3ul << TC_INTENSET_MC_Pos)
|
||||
#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
|
||||
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
|
||||
#define TC_INTENSET_MASK 0x3Bul /**< \brief (TC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t OVF:1; /*!< bit: 0 Overflow */
|
||||
uint8_t ERR:1; /*!< bit: 1 Error */
|
||||
uint8_t :1; /*!< bit: 2 Reserved */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
|
||||
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint8_t OVF:1; /*!< bit: 0 Overflow */
|
||||
__I uint8_t ERR:1; /*!< bit: 1 Error */
|
||||
__I uint8_t :1; /*!< bit: 2 Reserved */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
|
||||
__I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
|
||||
__I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
|
||||
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint8_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
__I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
|
||||
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} TC_INTFLAG_Type;
|
||||
@ -452,7 +449,7 @@ typedef union {
|
||||
#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
|
||||
#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
|
||||
#define TC_INTFLAG_MC_Msk (0x3ul << TC_INTFLAG_MC_Pos)
|
||||
#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
|
||||
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
|
||||
#define TC_INTFLAG_MASK 0x3Bul /**< \brief (TC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
|
||||
@ -495,7 +492,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
|
||||
#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFul << TC_COUNT16_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT16_COUNT_MASK 0xFFFFul /**< \brief (TC_COUNT16_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
|
||||
@ -513,7 +510,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
|
||||
#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFul << TC_COUNT32_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
|
||||
@ -531,7 +528,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
|
||||
#define TC_COUNT8_COUNT_COUNT_Msk (0xFFul << TC_COUNT8_COUNT_COUNT_Pos)
|
||||
#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
|
||||
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
|
||||
#define TC_COUNT8_COUNT_MASK 0xFFul /**< \brief (TC_COUNT8_COUNT) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
|
||||
@ -549,7 +546,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
|
||||
#define TC_COUNT8_PER_PER_Msk (0xFFul << TC_COUNT8_PER_PER_Pos)
|
||||
#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
|
||||
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
|
||||
#define TC_COUNT8_PER_MASK 0xFFul /**< \brief (TC_COUNT8_PER) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
|
||||
@ -567,7 +564,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
|
||||
#define TC_COUNT16_CC_CC_Msk (0xFFFFul << TC_COUNT16_CC_CC_Pos)
|
||||
#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
|
||||
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
|
||||
#define TC_COUNT16_CC_MASK 0xFFFFul /**< \brief (TC_COUNT16_CC) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
|
||||
@ -585,7 +582,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
|
||||
#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFul << TC_COUNT32_CC_CC_Pos)
|
||||
#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
|
||||
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
|
||||
#define TC_COUNT32_CC_MASK 0xFFFFFFFFul /**< \brief (TC_COUNT32_CC) MASK Register */
|
||||
|
||||
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
|
||||
@ -603,7 +600,7 @@ typedef union {
|
||||
|
||||
#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
|
||||
#define TC_COUNT8_CC_CC_Msk (0xFFul << TC_COUNT8_CC_CC_Pos)
|
||||
#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
|
||||
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
|
||||
#define TC_COUNT8_CC_MASK 0xFFul /**< \brief (TC_COUNT8_CC) MASK Register */
|
||||
|
||||
/** \brief TC_COUNT8 hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for TCC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC_COMPONENT_
|
||||
#define _SAMD21_TCC_COMPONENT_
|
||||
@ -54,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define TCC_U2213
|
||||
#define REV_TCC 0x121
|
||||
#define REV_TCC 0x122
|
||||
|
||||
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -94,7 +91,7 @@ typedef union {
|
||||
#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
|
||||
#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
|
||||
#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
|
||||
#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
|
||||
@ -105,7 +102,7 @@ typedef union {
|
||||
#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
|
||||
#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
|
||||
#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
|
||||
#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
|
||||
#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
|
||||
#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
|
||||
#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
|
||||
@ -126,7 +123,7 @@ typedef union {
|
||||
#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
|
||||
#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
|
||||
#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
|
||||
#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
|
||||
#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
|
||||
#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
|
||||
@ -145,7 +142,7 @@ typedef union {
|
||||
#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
|
||||
#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
|
||||
#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
|
||||
#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
|
||||
#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
|
||||
#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
|
||||
@ -173,7 +170,7 @@ typedef union {
|
||||
#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
|
||||
#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
|
||||
#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
|
||||
@ -184,7 +181,7 @@ typedef union {
|
||||
#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
|
||||
#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
|
||||
#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
|
||||
#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
|
||||
#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
|
||||
@ -222,7 +219,7 @@ typedef union {
|
||||
#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
|
||||
#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
|
||||
#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
|
||||
@ -233,7 +230,7 @@ typedef union {
|
||||
#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
|
||||
#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
|
||||
#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
|
||||
#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
|
||||
#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
|
||||
@ -312,7 +309,7 @@ typedef union {
|
||||
#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
|
||||
#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
|
||||
#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
|
||||
#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
|
||||
#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
|
||||
#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
|
||||
#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
|
||||
#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
|
||||
@ -329,7 +326,7 @@ typedef union {
|
||||
#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
|
||||
#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
|
||||
#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
|
||||
#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
|
||||
#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
|
||||
#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
|
||||
@ -359,7 +356,7 @@ typedef union {
|
||||
|
||||
#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
|
||||
#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
|
||||
#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
|
||||
#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
|
||||
#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
|
||||
#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
|
||||
@ -374,12 +371,12 @@ typedef union {
|
||||
#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
|
||||
#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
|
||||
#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
|
||||
#define TCC_FCTRLA_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLA) No blanking applied */
|
||||
#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
|
||||
#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos)
|
||||
@ -387,7 +384,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
|
||||
#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
|
||||
#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
|
||||
#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
|
||||
#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
|
||||
#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
|
||||
#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
|
||||
@ -398,7 +395,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
|
||||
#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
|
||||
#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
|
||||
#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
|
||||
@ -409,7 +406,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
|
||||
#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
|
||||
#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
|
||||
@ -417,6 +414,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLA) Minimum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLA) Maximum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */
|
||||
#define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
@ -424,12 +422,13 @@ typedef union {
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
|
||||
#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
|
||||
#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
|
||||
@ -459,7 +458,7 @@ typedef union {
|
||||
|
||||
#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
|
||||
#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
|
||||
#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
|
||||
#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
|
||||
#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
|
||||
#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
|
||||
@ -474,12 +473,12 @@ typedef union {
|
||||
#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
|
||||
#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
|
||||
#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
|
||||
#define TCC_FCTRLB_BLANK_NONE_Val 0x0ul /**< \brief (TCC_FCTRLB) No blanking applied */
|
||||
#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
|
||||
#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_BOTH_Val 0x3ul /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos)
|
||||
@ -487,7 +486,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
|
||||
#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
|
||||
#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
|
||||
#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
|
||||
#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
|
||||
#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
|
||||
#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
|
||||
@ -498,7 +497,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
|
||||
#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
|
||||
#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
|
||||
#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
|
||||
@ -509,7 +508,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
|
||||
#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
|
||||
#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
|
||||
@ -517,6 +516,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMIN_Val 0x4ul /**< \brief (TCC_FCTRLB) Minimum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMAX_Val 0x5ul /**< \brief (TCC_FCTRLB) Maximum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_DERIV0_Val 0x6ul /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMARK_Val 0x7ul /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */
|
||||
#define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
@ -524,12 +524,13 @@ typedef union {
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
|
||||
#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
|
||||
#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
|
||||
|
||||
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
|
||||
@ -560,7 +561,7 @@ typedef union {
|
||||
|
||||
#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
|
||||
#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
|
||||
#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
|
||||
#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
|
||||
#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
|
||||
#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
|
||||
@ -571,13 +572,13 @@ typedef union {
|
||||
#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
|
||||
#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
|
||||
#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
|
||||
#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
|
||||
#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
|
||||
#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
|
||||
#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
|
||||
#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
|
||||
#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
|
||||
#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
|
||||
@ -642,7 +643,7 @@ typedef union {
|
||||
#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
|
||||
#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
|
||||
#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
|
||||
#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
|
||||
#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
|
||||
#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
|
||||
#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
|
||||
#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
|
||||
@ -661,7 +662,7 @@ typedef union {
|
||||
#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
|
||||
#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
|
||||
#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
|
||||
#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
|
||||
#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
|
||||
#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
|
||||
#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
|
||||
#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
|
||||
@ -680,13 +681,13 @@ typedef union {
|
||||
#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
|
||||
#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
|
||||
#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
|
||||
#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
|
||||
#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
|
||||
#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
|
||||
@ -755,13 +756,14 @@ typedef union {
|
||||
|
||||
#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
|
||||
#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
|
||||
#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
|
||||
#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
|
||||
#define TCC_EVCTRL_EVACT0_START_Val 0x3ul /**< \brief (TCC_EVCTRL) Start counter on event */
|
||||
#define TCC_EVCTRL_EVACT0_INC_Val 0x4ul /**< \brief (TCC_EVCTRL) Increment counter on event */
|
||||
#define TCC_EVCTRL_EVACT0_COUNT_Val 0x5ul /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */
|
||||
#define TCC_EVCTRL_EVACT0_STAMP_Val 0x6ul /**< \brief (TCC_EVCTRL) Stamp capture */
|
||||
#define TCC_EVCTRL_EVACT0_FAULT_Val 0x7ul /**< \brief (TCC_EVCTRL) Non-recoverable fault */
|
||||
#define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
@ -769,10 +771,11 @@ typedef union {
|
||||
#define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
|
||||
#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
|
||||
#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
|
||||
#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
|
||||
@ -791,7 +794,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
|
||||
#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
|
||||
#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
|
||||
#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
|
||||
#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
|
||||
#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
|
||||
@ -812,14 +815,14 @@ typedef union {
|
||||
#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
|
||||
#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
|
||||
#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
|
||||
#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
|
||||
#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
|
||||
#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
|
||||
#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
|
||||
#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
|
||||
#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
|
||||
#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
|
||||
@ -830,7 +833,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
|
||||
#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
|
||||
#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
|
||||
#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
|
||||
#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
|
||||
@ -841,7 +844,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
|
||||
#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
|
||||
#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
|
||||
#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
|
||||
#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
|
||||
@ -852,7 +855,8 @@ typedef union {
|
||||
uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
|
||||
uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
|
||||
uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
|
||||
uint32_t :7; /*!< bit: 4..10 Reserved */
|
||||
uint32_t :6; /*!< bit: 4.. 9 Reserved */
|
||||
uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
|
||||
uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
|
||||
uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
|
||||
uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
|
||||
@ -884,6 +888,8 @@ typedef union {
|
||||
#define TCC_INTENCLR_CNT (0x1ul << TCC_INTENCLR_CNT_Pos)
|
||||
#define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */
|
||||
#define TCC_INTENCLR_ERR (0x1ul << TCC_INTENCLR_ERR_Pos)
|
||||
#define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */
|
||||
#define TCC_INTENCLR_UFS (0x1ul << TCC_INTENCLR_UFS_Pos)
|
||||
#define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */
|
||||
#define TCC_INTENCLR_DFS (0x1ul << TCC_INTENCLR_DFS_Pos)
|
||||
#define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */
|
||||
@ -904,8 +910,8 @@ typedef union {
|
||||
#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
|
||||
#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
|
||||
#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
|
||||
#define TCC_INTENCLR_MASK 0x000FF80Ful /**< \brief (TCC_INTENCLR) MASK Register */
|
||||
#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
|
||||
#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -915,7 +921,8 @@ typedef union {
|
||||
uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */
|
||||
uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */
|
||||
uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */
|
||||
uint32_t :7; /*!< bit: 4..10 Reserved */
|
||||
uint32_t :6; /*!< bit: 4.. 9 Reserved */
|
||||
uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */
|
||||
uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */
|
||||
uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */
|
||||
uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */
|
||||
@ -947,6 +954,8 @@ typedef union {
|
||||
#define TCC_INTENSET_CNT (0x1ul << TCC_INTENSET_CNT_Pos)
|
||||
#define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */
|
||||
#define TCC_INTENSET_ERR (0x1ul << TCC_INTENSET_ERR_Pos)
|
||||
#define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */
|
||||
#define TCC_INTENSET_UFS (0x1ul << TCC_INTENSET_UFS_Pos)
|
||||
#define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */
|
||||
#define TCC_INTENSET_DFS (0x1ul << TCC_INTENSET_DFS_Pos)
|
||||
#define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */
|
||||
@ -967,33 +976,34 @@ typedef union {
|
||||
#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
|
||||
#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
|
||||
#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
|
||||
#define TCC_INTENSET_MASK 0x000FF80Ful /**< \brief (TCC_INTENSET) MASK Register */
|
||||
#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
|
||||
#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
uint32_t :7; /*!< bit: 4..10 Reserved */
|
||||
uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
__I uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
__I uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
__I uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
__I uint32_t :6; /*!< bit: 4.. 9 Reserved */
|
||||
__I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
|
||||
__I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
__I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
__I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
__I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
__I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
__I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
__I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
__I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
__I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
__I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} TCC_INTFLAG_Type;
|
||||
@ -1010,6 +1020,8 @@ typedef union {
|
||||
#define TCC_INTFLAG_CNT (0x1ul << TCC_INTFLAG_CNT_Pos)
|
||||
#define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */
|
||||
#define TCC_INTFLAG_ERR (0x1ul << TCC_INTFLAG_ERR_Pos)
|
||||
#define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */
|
||||
#define TCC_INTFLAG_UFS (0x1ul << TCC_INTFLAG_UFS_Pos)
|
||||
#define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */
|
||||
#define TCC_INTFLAG_DFS (0x1ul << TCC_INTFLAG_DFS_Pos)
|
||||
#define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */
|
||||
@ -1030,8 +1042,8 @@ typedef union {
|
||||
#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
|
||||
#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
|
||||
#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
|
||||
#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
|
||||
#define TCC_INTFLAG_MASK 0x000FF80Ful /**< \brief (TCC_INTFLAG) MASK Register */
|
||||
#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
|
||||
#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -1039,7 +1051,7 @@ typedef union {
|
||||
struct {
|
||||
uint32_t STOP:1; /*!< bit: 0 Stop */
|
||||
uint32_t IDX:1; /*!< bit: 1 Ramp */
|
||||
uint32_t :1; /*!< bit: 2 Reserved */
|
||||
uint32_t UFS:1; /*!< bit: 2 Non-Recoverable Update Fault State */
|
||||
uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */
|
||||
uint32_t SLAVE:1; /*!< bit: 4 Slave */
|
||||
uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */
|
||||
@ -1082,6 +1094,8 @@ typedef union {
|
||||
#define TCC_STATUS_STOP (0x1ul << TCC_STATUS_STOP_Pos)
|
||||
#define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */
|
||||
#define TCC_STATUS_IDX (0x1ul << TCC_STATUS_IDX_Pos)
|
||||
#define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-Recoverable Update Fault State */
|
||||
#define TCC_STATUS_UFS (0x1ul << TCC_STATUS_UFS_Pos)
|
||||
#define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */
|
||||
#define TCC_STATUS_DFS (0x1ul << TCC_STATUS_DFS_Pos)
|
||||
#define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */
|
||||
@ -1118,7 +1132,7 @@ typedef union {
|
||||
#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
|
||||
#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
|
||||
#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
|
||||
#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
|
||||
#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
|
||||
#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
|
||||
#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
|
||||
#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
|
||||
@ -1129,8 +1143,8 @@ typedef union {
|
||||
#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
|
||||
#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
|
||||
#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
|
||||
#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
|
||||
#define TCC_STATUS_MASK 0x0F0FFFFBul /**< \brief (TCC_STATUS) MASK Register */
|
||||
#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
|
||||
#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
|
||||
|
||||
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -1164,24 +1178,24 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
|
||||
#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
|
||||
#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
|
||||
#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
|
||||
|
||||
#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
|
||||
#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
|
||||
#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
|
||||
#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
|
||||
#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
|
||||
|
||||
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
|
||||
@ -1234,7 +1248,7 @@ typedef union {
|
||||
#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
|
||||
#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
|
||||
#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
|
||||
#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
|
||||
#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
|
||||
#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
|
||||
#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
|
||||
#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
|
||||
@ -1253,7 +1267,7 @@ typedef union {
|
||||
#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
|
||||
#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
|
||||
#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
|
||||
#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
|
||||
#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
|
||||
#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
|
||||
@ -1299,7 +1313,7 @@ typedef union {
|
||||
|
||||
#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
|
||||
#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
|
||||
#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
|
||||
#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
|
||||
#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
|
||||
#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
|
||||
@ -1316,13 +1330,15 @@ typedef union {
|
||||
#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
|
||||
#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
|
||||
#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
|
||||
#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVE) Critical RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */
|
||||
#define TCC_WAVE_CIPEREN (0x1ul << TCC_WAVE_CIPEREN_Pos)
|
||||
#define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */
|
||||
@ -1335,7 +1351,7 @@ typedef union {
|
||||
#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
|
||||
#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
|
||||
#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
|
||||
#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
|
||||
#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
|
||||
#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
|
||||
#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
|
||||
#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
|
||||
@ -1346,7 +1362,7 @@ typedef union {
|
||||
#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
|
||||
#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
|
||||
#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
|
||||
#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
|
||||
#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
|
||||
#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
|
||||
#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
|
||||
#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
|
||||
@ -1357,7 +1373,7 @@ typedef union {
|
||||
#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
|
||||
#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
|
||||
#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
|
||||
#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
|
||||
#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
|
||||
#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
|
||||
|
||||
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
|
||||
@ -1392,33 +1408,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
|
||||
#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
|
||||
#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)))
|
||||
#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
|
||||
#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
|
||||
#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
|
||||
#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)))
|
||||
#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
|
||||
#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
|
||||
#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
|
||||
#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)))
|
||||
#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
|
||||
#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
|
||||
#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
|
||||
#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
|
||||
#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
|
||||
#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
|
||||
|
||||
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
|
||||
@ -1453,33 +1469,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
|
||||
#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)))
|
||||
#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
|
||||
#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
|
||||
#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)))
|
||||
#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
|
||||
#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
|
||||
#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)))
|
||||
#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
|
||||
#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
|
||||
#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
|
||||
#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
|
||||
#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
|
||||
#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
|
||||
|
||||
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
|
||||
@ -1532,7 +1548,7 @@ typedef union {
|
||||
#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
|
||||
#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
|
||||
#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
|
||||
#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
|
||||
#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
|
||||
#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
|
||||
#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
|
||||
#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
|
||||
@ -1551,7 +1567,7 @@ typedef union {
|
||||
#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
|
||||
#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
|
||||
#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
|
||||
#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
|
||||
#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
|
||||
#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
|
||||
@ -1597,7 +1613,7 @@ typedef union {
|
||||
|
||||
#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
|
||||
#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
|
||||
#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
|
||||
#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
|
||||
@ -1614,13 +1630,15 @@ typedef union {
|
||||
#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
|
||||
#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
|
||||
#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
|
||||
#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2C_Val 0x3ul /**< \brief (TCC_WAVEB) Critical RAMP2 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_RAMP2C (TCC_WAVEB_RAMPB_RAMP2C_Val << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */
|
||||
#define TCC_WAVEB_CIPERENB (0x1ul << TCC_WAVEB_CIPERENB_Pos)
|
||||
#define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */
|
||||
@ -1633,7 +1651,7 @@ typedef union {
|
||||
#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
|
||||
#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
|
||||
#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
|
||||
#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
|
||||
#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
|
||||
#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
|
||||
#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
|
||||
@ -1644,7 +1662,7 @@ typedef union {
|
||||
#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
|
||||
#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
|
||||
#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
|
||||
#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
|
||||
#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
|
||||
#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
|
||||
#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
|
||||
@ -1655,7 +1673,7 @@ typedef union {
|
||||
#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
|
||||
#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
|
||||
#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
|
||||
#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
|
||||
#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
|
||||
#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
|
||||
|
||||
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
|
||||
@ -1690,33 +1708,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
|
||||
#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
|
||||
#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)))
|
||||
#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
|
||||
#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
|
||||
#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
|
||||
#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)))
|
||||
#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
|
||||
#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
|
||||
#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
|
||||
#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)))
|
||||
#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
|
||||
#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
|
||||
#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
|
||||
#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
|
||||
#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
|
||||
#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
|
||||
|
||||
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
|
||||
@ -1751,33 +1769,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
|
||||
#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)))
|
||||
#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
|
||||
#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
|
||||
#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)))
|
||||
#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
|
||||
#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
|
||||
#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)))
|
||||
#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
|
||||
#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
|
||||
#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
|
||||
#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
|
||||
#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
|
||||
|
||||
/** \brief TCC hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for TCC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -51,7 +51,7 @@
|
||||
/*@{*/
|
||||
|
||||
#define TCC_U2213
|
||||
#define REV_TCC 0x121
|
||||
#define REV_TCC 0x122
|
||||
|
||||
/* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -91,7 +91,7 @@ typedef union {
|
||||
#define TCC_CTRLA_ENABLE (0x1ul << TCC_CTRLA_ENABLE_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */
|
||||
#define TCC_CTRLA_RESOLUTION_Msk (0x3ul << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_RESOLUTION(value) ((TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)))
|
||||
#define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos))
|
||||
#define TCC_CTRLA_RESOLUTION_NONE_Val 0x0ul /**< \brief (TCC_CTRLA) Dithering is disabled */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH4_Val 0x1ul /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */
|
||||
#define TCC_CTRLA_RESOLUTION_DITH5_Val 0x2ul /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */
|
||||
@ -102,7 +102,7 @@ typedef union {
|
||||
#define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos)
|
||||
#define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */
|
||||
#define TCC_CTRLA_PRESCALER_Msk (0x7ul << TCC_CTRLA_PRESCALER_Pos)
|
||||
#define TCC_CTRLA_PRESCALER(value) ((TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)))
|
||||
#define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos))
|
||||
#define TCC_CTRLA_PRESCALER_DIV1_Val 0x0ul /**< \brief (TCC_CTRLA) No division */
|
||||
#define TCC_CTRLA_PRESCALER_DIV2_Val 0x1ul /**< \brief (TCC_CTRLA) Divide by 2 */
|
||||
#define TCC_CTRLA_PRESCALER_DIV4_Val 0x2ul /**< \brief (TCC_CTRLA) Divide by 4 */
|
||||
@ -123,7 +123,7 @@ typedef union {
|
||||
#define TCC_CTRLA_RUNSTDBY (0x1ul << TCC_CTRLA_RUNSTDBY_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */
|
||||
#define TCC_CTRLA_PRESCSYNC_Msk (0x3ul << TCC_CTRLA_PRESCSYNC_Pos)
|
||||
#define TCC_CTRLA_PRESCSYNC(value) ((TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)))
|
||||
#define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos))
|
||||
#define TCC_CTRLA_PRESCSYNC_GCLK_Val 0x0ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */
|
||||
#define TCC_CTRLA_PRESCSYNC_PRESC_Val 0x1ul /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */
|
||||
#define TCC_CTRLA_PRESCSYNC_RESYNC_Val 0x2ul /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */
|
||||
@ -142,7 +142,7 @@ typedef union {
|
||||
#define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos)
|
||||
#define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */
|
||||
#define TCC_CTRLA_CPTEN_Msk (0xFul << TCC_CTRLA_CPTEN_Pos)
|
||||
#define TCC_CTRLA_CPTEN(value) ((TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)))
|
||||
#define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos))
|
||||
#define TCC_CTRLA_MASK 0x0F007F63ul /**< \brief (TCC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */
|
||||
@ -170,7 +170,7 @@ typedef union {
|
||||
#define TCC_CTRLBCLR_ONESHOT (0x1ul << TCC_CTRLBCLR_ONESHOT_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */
|
||||
#define TCC_CTRLBCLR_IDXCMD_Msk (0x3ul << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) ((TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos))
|
||||
#define TCC_CTRLBCLR_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBCLR_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBCLR_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */
|
||||
@ -181,7 +181,7 @@ typedef union {
|
||||
#define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */
|
||||
#define TCC_CTRLBCLR_CMD_Msk (0x7ul << TCC_CTRLBCLR_CMD_Pos)
|
||||
#define TCC_CTRLBCLR_CMD(value) ((TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)))
|
||||
#define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos))
|
||||
#define TCC_CTRLBCLR_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBCLR) No action */
|
||||
#define TCC_CTRLBCLR_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBCLR_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBCLR) Force stop */
|
||||
@ -219,7 +219,7 @@ typedef union {
|
||||
#define TCC_CTRLBSET_ONESHOT (0x1ul << TCC_CTRLBSET_ONESHOT_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */
|
||||
#define TCC_CTRLBSET_IDXCMD_Msk (0x3ul << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_IDXCMD(value) ((TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)))
|
||||
#define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos))
|
||||
#define TCC_CTRLBSET_IDXCMD_DISABLE_Val 0x0ul /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */
|
||||
#define TCC_CTRLBSET_IDXCMD_SET_Val 0x1ul /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */
|
||||
#define TCC_CTRLBSET_IDXCMD_CLEAR_Val 0x2ul /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */
|
||||
@ -230,7 +230,7 @@ typedef union {
|
||||
#define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */
|
||||
#define TCC_CTRLBSET_CMD_Msk (0x7ul << TCC_CTRLBSET_CMD_Pos)
|
||||
#define TCC_CTRLBSET_CMD(value) ((TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)))
|
||||
#define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos))
|
||||
#define TCC_CTRLBSET_CMD_NONE_Val 0x0ul /**< \brief (TCC_CTRLBSET) No action */
|
||||
#define TCC_CTRLBSET_CMD_RETRIGGER_Val 0x1ul /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */
|
||||
#define TCC_CTRLBSET_CMD_STOP_Val 0x2ul /**< \brief (TCC_CTRLBSET) Force stop */
|
||||
@ -309,7 +309,7 @@ typedef union {
|
||||
#define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos)
|
||||
#define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */
|
||||
#define TCC_SYNCBUSY_CC_Msk (0xFul << TCC_SYNCBUSY_CC_Pos)
|
||||
#define TCC_SYNCBUSY_CC(value) ((TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)))
|
||||
#define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos))
|
||||
#define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */
|
||||
#define TCC_SYNCBUSY_PATTB (0x1ul << TCC_SYNCBUSY_PATTB_Pos)
|
||||
#define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */
|
||||
@ -326,7 +326,7 @@ typedef union {
|
||||
#define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos)
|
||||
#define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */
|
||||
#define TCC_SYNCBUSY_CCB_Msk (0xFul << TCC_SYNCBUSY_CCB_Pos)
|
||||
#define TCC_SYNCBUSY_CCB(value) ((TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)))
|
||||
#define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos))
|
||||
#define TCC_SYNCBUSY_MASK 0x007F0FFFul /**< \brief (TCC_SYNCBUSY) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */
|
||||
@ -356,7 +356,7 @@ typedef union {
|
||||
|
||||
#define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */
|
||||
#define TCC_FCTRLA_SRC_Msk (0x3ul << TCC_FCTRLA_SRC_Pos)
|
||||
#define TCC_FCTRLA_SRC(value) ((TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)))
|
||||
#define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos))
|
||||
#define TCC_FCTRLA_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Fault input disabled */
|
||||
#define TCC_FCTRLA_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLA_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */
|
||||
@ -371,7 +371,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_QUAL (0x1ul << TCC_FCTRLA_QUAL_Pos)
|
||||
#define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */
|
||||
#define TCC_FCTRLA_BLANK_Msk (0x3ul << TCC_FCTRLA_BLANK_Pos)
|
||||
#define TCC_FCTRLA_BLANK(value) ((TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)))
|
||||
#define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos))
|
||||
#define TCC_FCTRLA_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLA) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLA_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLA_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */
|
||||
@ -384,7 +384,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_RESTART (0x1ul << TCC_FCTRLA_RESTART_Pos)
|
||||
#define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */
|
||||
#define TCC_FCTRLA_HALT_Msk (0x3ul << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_HALT(value) ((TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)))
|
||||
#define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos))
|
||||
#define TCC_FCTRLA_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) Halt action disabled */
|
||||
#define TCC_FCTRLA_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLA) Hardware halt action */
|
||||
#define TCC_FCTRLA_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLA) Software halt action */
|
||||
@ -395,7 +395,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos)
|
||||
#define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */
|
||||
#define TCC_FCTRLA_CHSEL_Msk (0x3ul << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CHSEL(value) ((TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)))
|
||||
#define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos))
|
||||
#define TCC_FCTRLA_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLA_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLA_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */
|
||||
@ -406,7 +406,7 @@ typedef union {
|
||||
#define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */
|
||||
#define TCC_FCTRLA_CAPTURE_Msk (0x7ul << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_CAPTURE(value) ((TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos))
|
||||
#define TCC_FCTRLA_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLA) No capture */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLA) Capture on fault */
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLA) Minimum capture */
|
||||
@ -425,10 +425,10 @@ typedef union {
|
||||
#define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */
|
||||
#define TCC_FCTRLA_BLANKVAL_Msk (0xFFul << TCC_FCTRLA_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLA_BLANKVAL(value) ((TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */
|
||||
#define TCC_FCTRLA_FILTERVAL_Msk (0xFul << TCC_FCTRLA_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLA_FILTERVAL(value) ((TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLA_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLA) MASK Register */
|
||||
|
||||
/* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */
|
||||
@ -458,7 +458,7 @@ typedef union {
|
||||
|
||||
#define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */
|
||||
#define TCC_FCTRLB_SRC_Msk (0x3ul << TCC_FCTRLB_SRC_Pos)
|
||||
#define TCC_FCTRLB_SRC(value) ((TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)))
|
||||
#define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos))
|
||||
#define TCC_FCTRLB_SRC_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Fault input disabled */
|
||||
#define TCC_FCTRLB_SRC_ENABLE_Val 0x1ul /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */
|
||||
#define TCC_FCTRLB_SRC_INVERT_Val 0x2ul /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */
|
||||
@ -473,7 +473,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_QUAL (0x1ul << TCC_FCTRLB_QUAL_Pos)
|
||||
#define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */
|
||||
#define TCC_FCTRLB_BLANK_Msk (0x3ul << TCC_FCTRLB_BLANK_Pos)
|
||||
#define TCC_FCTRLB_BLANK(value) ((TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)))
|
||||
#define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos))
|
||||
#define TCC_FCTRLB_BLANK_START_Val 0x0ul /**< \brief (TCC_FCTRLB) Blanking applied from start of ramp */
|
||||
#define TCC_FCTRLB_BLANK_RISE_Val 0x1ul /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */
|
||||
#define TCC_FCTRLB_BLANK_FALL_Val 0x2ul /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */
|
||||
@ -486,7 +486,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_RESTART (0x1ul << TCC_FCTRLB_RESTART_Pos)
|
||||
#define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */
|
||||
#define TCC_FCTRLB_HALT_Msk (0x3ul << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_HALT(value) ((TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)))
|
||||
#define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos))
|
||||
#define TCC_FCTRLB_HALT_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) Halt action disabled */
|
||||
#define TCC_FCTRLB_HALT_HW_Val 0x1ul /**< \brief (TCC_FCTRLB) Hardware halt action */
|
||||
#define TCC_FCTRLB_HALT_SW_Val 0x2ul /**< \brief (TCC_FCTRLB) Software halt action */
|
||||
@ -497,7 +497,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos)
|
||||
#define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */
|
||||
#define TCC_FCTRLB_CHSEL_Msk (0x3ul << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CHSEL(value) ((TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)))
|
||||
#define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos))
|
||||
#define TCC_FCTRLB_CHSEL_CC0_Val 0x0ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */
|
||||
#define TCC_FCTRLB_CHSEL_CC1_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */
|
||||
#define TCC_FCTRLB_CHSEL_CC2_Val 0x2ul /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */
|
||||
@ -508,7 +508,7 @@ typedef union {
|
||||
#define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */
|
||||
#define TCC_FCTRLB_CAPTURE_Msk (0x7ul << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_CAPTURE(value) ((TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)))
|
||||
#define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos))
|
||||
#define TCC_FCTRLB_CAPTURE_DISABLE_Val 0x0ul /**< \brief (TCC_FCTRLB) No capture */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPT_Val 0x1ul /**< \brief (TCC_FCTRLB) Capture on fault */
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMIN_Val 0x2ul /**< \brief (TCC_FCTRLB) Minimum capture */
|
||||
@ -527,10 +527,10 @@ typedef union {
|
||||
#define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */
|
||||
#define TCC_FCTRLB_BLANKVAL_Msk (0xFFul << TCC_FCTRLB_BLANKVAL_Pos)
|
||||
#define TCC_FCTRLB_BLANKVAL(value) ((TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)))
|
||||
#define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos))
|
||||
#define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */
|
||||
#define TCC_FCTRLB_FILTERVAL_Msk (0xFul << TCC_FCTRLB_FILTERVAL_Pos)
|
||||
#define TCC_FCTRLB_FILTERVAL(value) ((TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)))
|
||||
#define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos))
|
||||
#define TCC_FCTRLB_MASK 0x0FFF7FFBul /**< \brief (TCC_FCTRLB) MASK Register */
|
||||
|
||||
/* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */
|
||||
@ -561,7 +561,7 @@ typedef union {
|
||||
|
||||
#define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */
|
||||
#define TCC_WEXCTRL_OTMX_Msk (0x3ul << TCC_WEXCTRL_OTMX_Pos)
|
||||
#define TCC_WEXCTRL_OTMX(value) ((TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)))
|
||||
#define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos))
|
||||
#define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */
|
||||
#define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */
|
||||
@ -572,13 +572,13 @@ typedef union {
|
||||
#define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */
|
||||
#define TCC_WEXCTRL_DTIEN_Msk (0xFul << TCC_WEXCTRL_DTIEN_Pos)
|
||||
#define TCC_WEXCTRL_DTIEN(value) ((TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)))
|
||||
#define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos))
|
||||
#define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTLS_Msk (0xFFul << TCC_WEXCTRL_DTLS_Pos)
|
||||
#define TCC_WEXCTRL_DTLS(value) ((TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)))
|
||||
#define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos))
|
||||
#define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */
|
||||
#define TCC_WEXCTRL_DTHS_Msk (0xFFul << TCC_WEXCTRL_DTHS_Pos)
|
||||
#define TCC_WEXCTRL_DTHS(value) ((TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)))
|
||||
#define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos))
|
||||
#define TCC_WEXCTRL_MASK 0xFFFF0F03ul /**< \brief (TCC_WEXCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */
|
||||
@ -643,7 +643,7 @@ typedef union {
|
||||
#define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos)
|
||||
#define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */
|
||||
#define TCC_DRVCTRL_NRE_Msk (0xFFul << TCC_DRVCTRL_NRE_Pos)
|
||||
#define TCC_DRVCTRL_NRE(value) ((TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)))
|
||||
#define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos))
|
||||
#define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */
|
||||
#define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos)
|
||||
#define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */
|
||||
@ -662,7 +662,7 @@ typedef union {
|
||||
#define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos)
|
||||
#define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */
|
||||
#define TCC_DRVCTRL_NRV_Msk (0xFFul << TCC_DRVCTRL_NRV_Pos)
|
||||
#define TCC_DRVCTRL_NRV(value) ((TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)))
|
||||
#define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos))
|
||||
#define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */
|
||||
#define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos)
|
||||
#define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */
|
||||
@ -681,13 +681,13 @@ typedef union {
|
||||
#define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos)
|
||||
#define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */
|
||||
#define TCC_DRVCTRL_INVEN_Msk (0xFFul << TCC_DRVCTRL_INVEN_Pos)
|
||||
#define TCC_DRVCTRL_INVEN(value) ((TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)))
|
||||
#define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL0_Msk (0xFul << TCC_DRVCTRL_FILTERVAL0_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) ((TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos))
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */
|
||||
#define TCC_DRVCTRL_FILTERVAL1_Msk (0xFul << TCC_DRVCTRL_FILTERVAL1_Pos)
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) ((TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)))
|
||||
#define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos))
|
||||
#define TCC_DRVCTRL_MASK 0xFFFFFFFFul /**< \brief (TCC_DRVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */
|
||||
@ -756,7 +756,7 @@ typedef union {
|
||||
|
||||
#define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */
|
||||
#define TCC_EVCTRL_EVACT0_Msk (0x7ul << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT0(value) ((TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)))
|
||||
#define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos))
|
||||
#define TCC_EVCTRL_EVACT0_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT0_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT0_COUNTEV_Val 0x2ul /**< \brief (TCC_EVCTRL) Count on event */
|
||||
@ -775,7 +775,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos)
|
||||
#define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */
|
||||
#define TCC_EVCTRL_EVACT1_Msk (0x7ul << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_EVACT1(value) ((TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)))
|
||||
#define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos))
|
||||
#define TCC_EVCTRL_EVACT1_OFF_Val 0x0ul /**< \brief (TCC_EVCTRL) Event action disabled */
|
||||
#define TCC_EVCTRL_EVACT1_RETRIGGER_Val 0x1ul /**< \brief (TCC_EVCTRL) Re-trigger counter on event */
|
||||
#define TCC_EVCTRL_EVACT1_DIR_Val 0x2ul /**< \brief (TCC_EVCTRL) Direction control */
|
||||
@ -794,7 +794,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */
|
||||
#define TCC_EVCTRL_CNTSEL_Msk (0x3ul << TCC_EVCTRL_CNTSEL_Pos)
|
||||
#define TCC_EVCTRL_CNTSEL(value) ((TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)))
|
||||
#define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos))
|
||||
#define TCC_EVCTRL_CNTSEL_START_Val 0x0ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */
|
||||
#define TCC_EVCTRL_CNTSEL_END_Val 0x1ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */
|
||||
#define TCC_EVCTRL_CNTSEL_BETWEEN_Val 0x2ul /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */
|
||||
@ -815,14 +815,14 @@ typedef union {
|
||||
#define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos)
|
||||
#define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCINV_Msk (0x3ul << TCC_EVCTRL_TCINV_Pos)
|
||||
#define TCC_EVCTRL_TCINV(value) ((TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)))
|
||||
#define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos))
|
||||
#define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos)
|
||||
#define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */
|
||||
#define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos)
|
||||
#define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */
|
||||
#define TCC_EVCTRL_TCEI_Msk (0x3ul << TCC_EVCTRL_TCEI_Pos)
|
||||
#define TCC_EVCTRL_TCEI(value) ((TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)))
|
||||
#define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos)
|
||||
#define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */
|
||||
@ -833,7 +833,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos)
|
||||
#define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */
|
||||
#define TCC_EVCTRL_MCEI_Msk (0xFul << TCC_EVCTRL_MCEI_Pos)
|
||||
#define TCC_EVCTRL_MCEI(value) ((TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)))
|
||||
#define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos))
|
||||
#define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos)
|
||||
#define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
|
||||
@ -844,7 +844,7 @@ typedef union {
|
||||
#define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos)
|
||||
#define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */
|
||||
#define TCC_EVCTRL_MCEO_Msk (0xFul << TCC_EVCTRL_MCEO_Pos)
|
||||
#define TCC_EVCTRL_MCEO(value) ((TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)))
|
||||
#define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos))
|
||||
#define TCC_EVCTRL_MASK 0x0F0FF7FFul /**< \brief (TCC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */
|
||||
@ -910,7 +910,7 @@ typedef union {
|
||||
#define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos)
|
||||
#define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENCLR_MC_Msk (0xFul << TCC_INTENCLR_MC_Pos)
|
||||
#define TCC_INTENCLR_MC(value) ((TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)))
|
||||
#define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos))
|
||||
#define TCC_INTENCLR_MASK 0x000FFC0Ful /**< \brief (TCC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */
|
||||
@ -976,34 +976,34 @@ typedef union {
|
||||
#define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos)
|
||||
#define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */
|
||||
#define TCC_INTENSET_MC_Msk (0xFul << TCC_INTENSET_MC_Pos)
|
||||
#define TCC_INTENSET_MC(value) ((TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)))
|
||||
#define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos))
|
||||
#define TCC_INTENSET_MASK 0x000FFC0Ful /**< \brief (TCC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
uint32_t :6; /*!< bit: 4.. 9 Reserved */
|
||||
uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
|
||||
uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t OVF:1; /*!< bit: 0 Overflow */
|
||||
__I uint32_t TRG:1; /*!< bit: 1 Retrigger */
|
||||
__I uint32_t CNT:1; /*!< bit: 2 Counter */
|
||||
__I uint32_t ERR:1; /*!< bit: 3 Error */
|
||||
__I uint32_t :6; /*!< bit: 4.. 9 Reserved */
|
||||
__I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
|
||||
__I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
|
||||
__I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
|
||||
__I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
|
||||
__I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
|
||||
__I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */
|
||||
__I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */
|
||||
__I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */
|
||||
__I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */
|
||||
__I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
__I uint32_t :16; /*!< bit: 0..15 Reserved */
|
||||
__I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */
|
||||
__I uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} TCC_INTFLAG_Type;
|
||||
@ -1042,7 +1042,7 @@ typedef union {
|
||||
#define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos)
|
||||
#define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */
|
||||
#define TCC_INTFLAG_MC_Msk (0xFul << TCC_INTFLAG_MC_Pos)
|
||||
#define TCC_INTFLAG_MC(value) ((TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)))
|
||||
#define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos))
|
||||
#define TCC_INTFLAG_MASK 0x000FFC0Ful /**< \brief (TCC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */
|
||||
@ -1132,7 +1132,7 @@ typedef union {
|
||||
#define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos)
|
||||
#define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */
|
||||
#define TCC_STATUS_CCBV_Msk (0xFul << TCC_STATUS_CCBV_Pos)
|
||||
#define TCC_STATUS_CCBV(value) ((TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)))
|
||||
#define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos))
|
||||
#define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */
|
||||
#define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos)
|
||||
#define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */
|
||||
@ -1143,7 +1143,7 @@ typedef union {
|
||||
#define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos)
|
||||
#define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */
|
||||
#define TCC_STATUS_CMP_Msk (0xFul << TCC_STATUS_CMP_Pos)
|
||||
#define TCC_STATUS_CMP(value) ((TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)))
|
||||
#define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos))
|
||||
#define TCC_STATUS_MASK 0x0F0FFFFFul /**< \brief (TCC_STATUS) MASK Register */
|
||||
|
||||
/* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
|
||||
@ -1178,24 +1178,24 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */
|
||||
#define TCC_COUNT_DITH4_COUNT_Msk (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH4_COUNT(value) ((TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH4_MASK 0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */
|
||||
#define TCC_COUNT_DITH5_COUNT_Msk (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH5_COUNT(value) ((TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH5_MASK 0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */
|
||||
#define TCC_COUNT_DITH6_COUNT_Msk (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
|
||||
#define TCC_COUNT_DITH6_COUNT(value) ((TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)))
|
||||
#define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
|
||||
#define TCC_COUNT_DITH6_MASK 0x00FFFFC0ul /**< \brief (TCC_COUNT_DITH6) MASK Register */
|
||||
|
||||
#define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */
|
||||
#define TCC_COUNT_COUNT_Msk (0xFFFFFFul << TCC_COUNT_COUNT_Pos)
|
||||
#define TCC_COUNT_COUNT(value) ((TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)))
|
||||
#define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos))
|
||||
#define TCC_COUNT_MASK 0x00FFFFFFul /**< \brief (TCC_COUNT) MASK Register */
|
||||
|
||||
/* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */
|
||||
@ -1248,7 +1248,7 @@ typedef union {
|
||||
#define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos)
|
||||
#define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */
|
||||
#define TCC_PATT_PGE_Msk (0xFFul << TCC_PATT_PGE_Pos)
|
||||
#define TCC_PATT_PGE(value) ((TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)))
|
||||
#define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos))
|
||||
#define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */
|
||||
#define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos)
|
||||
#define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */
|
||||
@ -1267,7 +1267,7 @@ typedef union {
|
||||
#define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos)
|
||||
#define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */
|
||||
#define TCC_PATT_PGV_Msk (0xFFul << TCC_PATT_PGV_Pos)
|
||||
#define TCC_PATT_PGV(value) ((TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)))
|
||||
#define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos))
|
||||
#define TCC_PATT_MASK 0xFFFFul /**< \brief (TCC_PATT) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */
|
||||
@ -1313,7 +1313,7 @@ typedef union {
|
||||
|
||||
#define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */
|
||||
#define TCC_WAVE_WAVEGEN_Msk (0x7ul << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_WAVEGEN(value) ((TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)))
|
||||
#define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos))
|
||||
#define TCC_WAVE_WAVEGEN_NFRQ_Val 0x0ul /**< \brief (TCC_WAVE) Normal frequency */
|
||||
#define TCC_WAVE_WAVEGEN_MFRQ_Val 0x1ul /**< \brief (TCC_WAVE) Match frequency */
|
||||
#define TCC_WAVE_WAVEGEN_NPWM_Val 0x2ul /**< \brief (TCC_WAVE) Normal PWM */
|
||||
@ -1330,7 +1330,7 @@ typedef union {
|
||||
#define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos)
|
||||
#define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */
|
||||
#define TCC_WAVE_RAMP_Msk (0x3ul << TCC_WAVE_RAMP_Pos)
|
||||
#define TCC_WAVE_RAMP(value) ((TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)))
|
||||
#define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos))
|
||||
#define TCC_WAVE_RAMP_RAMP1_Val 0x0ul /**< \brief (TCC_WAVE) RAMP1 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVE) Alternative RAMP2 operation */
|
||||
#define TCC_WAVE_RAMP_RAMP2_Val 0x2ul /**< \brief (TCC_WAVE) RAMP2 operation */
|
||||
@ -1351,7 +1351,7 @@ typedef union {
|
||||
#define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos)
|
||||
#define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */
|
||||
#define TCC_WAVE_CICCEN_Msk (0xFul << TCC_WAVE_CICCEN_Pos)
|
||||
#define TCC_WAVE_CICCEN(value) ((TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)))
|
||||
#define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos))
|
||||
#define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */
|
||||
#define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos)
|
||||
#define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */
|
||||
@ -1362,7 +1362,7 @@ typedef union {
|
||||
#define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos)
|
||||
#define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */
|
||||
#define TCC_WAVE_POL_Msk (0xFul << TCC_WAVE_POL_Pos)
|
||||
#define TCC_WAVE_POL(value) ((TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)))
|
||||
#define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos))
|
||||
#define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */
|
||||
#define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos)
|
||||
#define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */
|
||||
@ -1373,7 +1373,7 @@ typedef union {
|
||||
#define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos)
|
||||
#define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */
|
||||
#define TCC_WAVE_SWAP_Msk (0xFul << TCC_WAVE_SWAP_Pos)
|
||||
#define TCC_WAVE_SWAP(value) ((TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)))
|
||||
#define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos))
|
||||
#define TCC_WAVE_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVE) MASK Register */
|
||||
|
||||
/* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
|
||||
@ -1408,33 +1408,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH4_DITHERCY_Msk (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH4_DITHERCY(value) ((TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */
|
||||
#define TCC_PER_DITH4_PER_Msk (0xFFFFFul << TCC_PER_DITH4_PER_Pos)
|
||||
#define TCC_PER_DITH4_PER(value) ((TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)))
|
||||
#define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
|
||||
#define TCC_PER_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH5_DITHERCY_Msk (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH5_DITHERCY(value) ((TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */
|
||||
#define TCC_PER_DITH5_PER_Msk (0x7FFFFul << TCC_PER_DITH5_PER_Pos)
|
||||
#define TCC_PER_DITH5_PER(value) ((TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)))
|
||||
#define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
|
||||
#define TCC_PER_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
|
||||
#define TCC_PER_DITH6_DITHERCY_Msk (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
|
||||
#define TCC_PER_DITH6_DITHERCY(value) ((TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
|
||||
#define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */
|
||||
#define TCC_PER_DITH6_PER_Msk (0x3FFFFul << TCC_PER_DITH6_PER_Pos)
|
||||
#define TCC_PER_DITH6_PER(value) ((TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)))
|
||||
#define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos))
|
||||
#define TCC_PER_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PER_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */
|
||||
#define TCC_PER_PER_Msk (0xFFFFFFul << TCC_PER_PER_Pos)
|
||||
#define TCC_PER_PER(value) ((TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)))
|
||||
#define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos))
|
||||
#define TCC_PER_MASK 0x00FFFFFFul /**< \brief (TCC_PER) MASK Register */
|
||||
|
||||
/* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
|
||||
@ -1469,33 +1469,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH4_DITHERCY_Msk (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH4_DITHERCY(value) ((TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH4_CC_Msk (0xFFFFFul << TCC_CC_DITH4_CC_Pos)
|
||||
#define TCC_CC_DITH4_CC(value) ((TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)))
|
||||
#define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
|
||||
#define TCC_CC_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH5_DITHERCY_Msk (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH5_DITHERCY(value) ((TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH5_CC_Msk (0x7FFFFul << TCC_CC_DITH5_CC_Pos)
|
||||
#define TCC_CC_DITH5_CC(value) ((TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)))
|
||||
#define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
|
||||
#define TCC_CC_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
|
||||
#define TCC_CC_DITH6_DITHERCY_Msk (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
|
||||
#define TCC_CC_DITH6_DITHERCY(value) ((TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)))
|
||||
#define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
|
||||
#define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */
|
||||
#define TCC_CC_DITH6_CC_Msk (0x3FFFFul << TCC_CC_DITH6_CC_Pos)
|
||||
#define TCC_CC_DITH6_CC(value) ((TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)))
|
||||
#define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos))
|
||||
#define TCC_CC_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CC_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */
|
||||
#define TCC_CC_CC_Msk (0xFFFFFFul << TCC_CC_CC_Pos)
|
||||
#define TCC_CC_CC(value) ((TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)))
|
||||
#define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos))
|
||||
#define TCC_CC_MASK 0x00FFFFFFul /**< \brief (TCC_CC) MASK Register */
|
||||
|
||||
/* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */
|
||||
@ -1548,7 +1548,7 @@ typedef union {
|
||||
#define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos)
|
||||
#define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */
|
||||
#define TCC_PATTB_PGEB_Msk (0xFFul << TCC_PATTB_PGEB_Pos)
|
||||
#define TCC_PATTB_PGEB(value) ((TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)))
|
||||
#define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos))
|
||||
#define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */
|
||||
#define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos)
|
||||
#define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */
|
||||
@ -1567,7 +1567,7 @@ typedef union {
|
||||
#define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos)
|
||||
#define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */
|
||||
#define TCC_PATTB_PGVB_Msk (0xFFul << TCC_PATTB_PGVB_Pos)
|
||||
#define TCC_PATTB_PGVB(value) ((TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)))
|
||||
#define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos))
|
||||
#define TCC_PATTB_MASK 0xFFFFul /**< \brief (TCC_PATTB) MASK Register */
|
||||
|
||||
/* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */
|
||||
@ -1613,7 +1613,7 @@ typedef union {
|
||||
|
||||
#define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */
|
||||
#define TCC_WAVEB_WAVEGENB_Msk (0x7ul << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_WAVEGENB(value) ((TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)))
|
||||
#define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos))
|
||||
#define TCC_WAVEB_WAVEGENB_NFRQ_Val 0x0ul /**< \brief (TCC_WAVEB) Normal frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_MFRQ_Val 0x1ul /**< \brief (TCC_WAVEB) Match frequency */
|
||||
#define TCC_WAVEB_WAVEGENB_NPWM_Val 0x2ul /**< \brief (TCC_WAVEB) Normal PWM */
|
||||
@ -1630,7 +1630,7 @@ typedef union {
|
||||
#define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos)
|
||||
#define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */
|
||||
#define TCC_WAVEB_RAMPB_Msk (0x3ul << TCC_WAVEB_RAMPB_Pos)
|
||||
#define TCC_WAVEB_RAMPB(value) ((TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)))
|
||||
#define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos))
|
||||
#define TCC_WAVEB_RAMPB_RAMP1_Val 0x0ul /**< \brief (TCC_WAVEB) RAMP1 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2A_Val 0x1ul /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */
|
||||
#define TCC_WAVEB_RAMPB_RAMP2_Val 0x2ul /**< \brief (TCC_WAVEB) RAMP2 operation */
|
||||
@ -1651,7 +1651,7 @@ typedef union {
|
||||
#define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos)
|
||||
#define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */
|
||||
#define TCC_WAVEB_CICCENB_Msk (0xFul << TCC_WAVEB_CICCENB_Pos)
|
||||
#define TCC_WAVEB_CICCENB(value) ((TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)))
|
||||
#define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos))
|
||||
#define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos)
|
||||
#define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */
|
||||
@ -1662,7 +1662,7 @@ typedef union {
|
||||
#define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos)
|
||||
#define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */
|
||||
#define TCC_WAVEB_POLB_Msk (0xFul << TCC_WAVEB_POLB_Pos)
|
||||
#define TCC_WAVEB_POLB(value) ((TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)))
|
||||
#define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos))
|
||||
#define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */
|
||||
#define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos)
|
||||
#define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */
|
||||
@ -1673,7 +1673,7 @@ typedef union {
|
||||
#define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos)
|
||||
#define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */
|
||||
#define TCC_WAVEB_SWAPB_Msk (0xFul << TCC_WAVEB_SWAPB_Pos)
|
||||
#define TCC_WAVEB_SWAPB(value) ((TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)))
|
||||
#define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos))
|
||||
#define TCC_WAVEB_MASK 0x0F0F0FB7ul /**< \brief (TCC_WAVEB) MASK Register */
|
||||
|
||||
/* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
|
||||
@ -1708,33 +1708,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) ((TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */
|
||||
#define TCC_PERB_DITH4_PERB_Msk (0xFFFFFul << TCC_PERB_DITH4_PERB_Pos)
|
||||
#define TCC_PERB_DITH4_PERB(value) ((TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)))
|
||||
#define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
|
||||
#define TCC_PERB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) ((TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */
|
||||
#define TCC_PERB_DITH5_PERB_Msk (0x7FFFFul << TCC_PERB_DITH5_PERB_Pos)
|
||||
#define TCC_PERB_DITH5_PERB(value) ((TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)))
|
||||
#define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
|
||||
#define TCC_PERB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) ((TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */
|
||||
#define TCC_PERB_DITH6_PERB_Msk (0x3FFFFul << TCC_PERB_DITH6_PERB_Pos)
|
||||
#define TCC_PERB_DITH6_PERB(value) ((TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)))
|
||||
#define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos))
|
||||
#define TCC_PERB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_PERB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */
|
||||
#define TCC_PERB_PERB_Msk (0xFFFFFFul << TCC_PERB_PERB_Pos)
|
||||
#define TCC_PERB_PERB(value) ((TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)))
|
||||
#define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos))
|
||||
#define TCC_PERB_MASK 0x00FFFFFFul /**< \brief (TCC_PERB) MASK Register */
|
||||
|
||||
/* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
|
||||
@ -1769,33 +1769,33 @@ typedef union {
|
||||
// DITH4 mode
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) ((TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH4_CCB_Msk (0xFFFFFul << TCC_CCB_DITH4_CCB_Pos)
|
||||
#define TCC_CCB_DITH4_CCB(value) ((TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)))
|
||||
#define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
|
||||
#define TCC_CCB_DITH4_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
|
||||
|
||||
// DITH5 mode
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) ((TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH5_CCB_Msk (0x7FFFFul << TCC_CCB_DITH5_CCB_Pos)
|
||||
#define TCC_CCB_DITH5_CCB(value) ((TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)))
|
||||
#define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
|
||||
#define TCC_CCB_DITH5_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
|
||||
|
||||
// DITH6 mode
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
|
||||
#define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) ((TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)))
|
||||
#define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
|
||||
#define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_DITH6_CCB_Msk (0x3FFFFul << TCC_CCB_DITH6_CCB_Pos)
|
||||
#define TCC_CCB_DITH6_CCB(value) ((TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)))
|
||||
#define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos))
|
||||
#define TCC_CCB_DITH6_MASK 0x00FFFFFFul /**< \brief (TCC_CCB_DITH6) MASK Register */
|
||||
|
||||
#define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */
|
||||
#define TCC_CCB_CCB_Msk (0xFFFFFFul << TCC_CCB_CCB_Pos)
|
||||
#define TCC_CCB_CCB(value) ((TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)))
|
||||
#define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos))
|
||||
#define TCC_CCB_MASK 0x00FFFFFFul /**< \brief (TCC_CCB) MASK Register */
|
||||
|
||||
/** \brief TCC hardware registers */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for USB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_USB_COMPONENT_
|
||||
#define _SAMD21_USB_COMPONENT_
|
||||
@ -125,7 +122,7 @@ typedef union {
|
||||
|
||||
#define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */
|
||||
#define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos)
|
||||
#define USB_QOSCTRL_CQOS(value) ((USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos)))
|
||||
#define USB_QOSCTRL_CQOS(value) (USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))
|
||||
#define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
|
||||
#define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
|
||||
#define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
|
||||
@ -136,7 +133,7 @@ typedef union {
|
||||
#define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos)
|
||||
#define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */
|
||||
#define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos)
|
||||
#define USB_QOSCTRL_DQOS(value) ((USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos)))
|
||||
#define USB_QOSCTRL_DQOS(value) (USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))
|
||||
#define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */
|
||||
#define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */
|
||||
#define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */
|
||||
@ -176,7 +173,7 @@ typedef union {
|
||||
#define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos)
|
||||
#define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */
|
||||
#define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos)
|
||||
#define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos)))
|
||||
#define USB_DEVICE_CTRLB_SPDCONF(value) (USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))
|
||||
#define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */
|
||||
#define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */
|
||||
#define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */
|
||||
@ -199,7 +196,7 @@ typedef union {
|
||||
#define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos)
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos)
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos)))
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK(value) (USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */
|
||||
#define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */
|
||||
@ -238,7 +235,7 @@ typedef union {
|
||||
#define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos)
|
||||
#define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */
|
||||
#define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos)
|
||||
#define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos)))
|
||||
#define USB_HOST_CTRLB_SPDCONF(value) (USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))
|
||||
#define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */
|
||||
#define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */
|
||||
#define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos)
|
||||
@ -273,7 +270,7 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */
|
||||
#define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos)
|
||||
#define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos)))
|
||||
#define USB_DEVICE_DADD_DADD(value) (USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))
|
||||
#define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */
|
||||
#define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos)
|
||||
#define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */
|
||||
@ -295,7 +292,7 @@ typedef union {
|
||||
|
||||
#define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */
|
||||
#define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos)
|
||||
#define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos)))
|
||||
#define USB_HOST_HSOFC_FLENC(value) (USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))
|
||||
#define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */
|
||||
#define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos)
|
||||
#define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */
|
||||
@ -318,7 +315,7 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */
|
||||
#define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos)
|
||||
#define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos)))
|
||||
#define USB_DEVICE_STATUS_SPEED(value) (USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))
|
||||
#define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */
|
||||
#define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */
|
||||
#define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */
|
||||
@ -327,7 +324,7 @@ typedef union {
|
||||
#define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos)
|
||||
#define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */
|
||||
#define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos)
|
||||
#define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos)))
|
||||
#define USB_DEVICE_STATUS_LINESTATE(value) (USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))
|
||||
#define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */
|
||||
#define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */
|
||||
#define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */
|
||||
@ -354,18 +351,18 @@ typedef union {
|
||||
|
||||
#define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */
|
||||
#define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos)
|
||||
#define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos)))
|
||||
#define USB_HOST_STATUS_SPEED(value) (USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))
|
||||
#define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */
|
||||
#define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos)
|
||||
#define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos)))
|
||||
#define USB_HOST_STATUS_LINESTATE(value) (USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))
|
||||
#define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */
|
||||
|
||||
/* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint8_t FSMSTATE:7; /*!< bit: 0.. 6 Fine State Machine Status */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} USB_FSMSTATUS_Type;
|
||||
@ -375,8 +372,8 @@ typedef union {
|
||||
#define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */
|
||||
|
||||
#define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */
|
||||
#define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos)
|
||||
#define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos)))
|
||||
#define USB_FSMSTATUS_FSMSTATE_Msk (0x7Ful << USB_FSMSTATUS_FSMSTATE_Pos)
|
||||
#define USB_FSMSTATUS_FSMSTATE(value) (USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))
|
||||
#define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */
|
||||
#define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */
|
||||
#define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */
|
||||
@ -391,7 +388,7 @@ typedef union {
|
||||
#define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
||||
#define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
||||
#define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos)
|
||||
#define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */
|
||||
#define USB_FSMSTATUS_MASK 0x7Ful /**< \brief (USB_FSMSTATUS) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
@ -411,10 +408,10 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */
|
||||
#define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos)
|
||||
#define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos)))
|
||||
#define USB_DEVICE_FNUM_MFNUM(value) (USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))
|
||||
#define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */
|
||||
#define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos)
|
||||
#define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos)))
|
||||
#define USB_DEVICE_FNUM_FNUM(value) (USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))
|
||||
#define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */
|
||||
#define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos)
|
||||
#define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */
|
||||
@ -436,10 +433,10 @@ typedef union {
|
||||
|
||||
#define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */
|
||||
#define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos)
|
||||
#define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos)))
|
||||
#define USB_HOST_FNUM_MFNUM(value) (USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))
|
||||
#define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */
|
||||
#define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos)
|
||||
#define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos)))
|
||||
#define USB_HOST_FNUM_FNUM(value) (USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))
|
||||
#define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */
|
||||
@ -457,7 +454,7 @@ typedef union {
|
||||
|
||||
#define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */
|
||||
#define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos)
|
||||
#define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos)))
|
||||
#define USB_HOST_FLENHIGH_FLENHIGH(value) (USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))
|
||||
#define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */
|
||||
@ -632,19 +629,19 @@ typedef union {
|
||||
|
||||
/* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
|
||||
uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
|
||||
uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
|
||||
uint16_t EORST:1; /*!< bit: 3 End of Reset */
|
||||
uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
||||
uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
|
||||
uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
|
||||
uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
||||
uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
|
||||
uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
__I uint16_t SUSPEND:1; /*!< bit: 0 Suspend */
|
||||
__I uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */
|
||||
__I uint16_t SOF:1; /*!< bit: 2 Start Of Frame */
|
||||
__I uint16_t EORST:1; /*!< bit: 3 End of Reset */
|
||||
__I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
||||
__I uint16_t EORSM:1; /*!< bit: 5 End Of Resume */
|
||||
__I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */
|
||||
__I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
||||
__I uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */
|
||||
__I uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */
|
||||
__I uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} USB_DEVICE_INTFLAG_Type;
|
||||
@ -677,18 +674,18 @@ typedef union {
|
||||
|
||||
/* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
|
||||
uint16_t RST:1; /*!< bit: 3 Bus Reset */
|
||||
uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
||||
uint16_t DNRSM:1; /*!< bit: 5 Downstream */
|
||||
uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
|
||||
uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
||||
uint16_t DCONN:1; /*!< bit: 8 Device Connection */
|
||||
uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
|
||||
uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
__I uint16_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
__I uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */
|
||||
__I uint16_t RST:1; /*!< bit: 3 Bus Reset */
|
||||
__I uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */
|
||||
__I uint16_t DNRSM:1; /*!< bit: 5 Downstream */
|
||||
__I uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */
|
||||
__I uint16_t RAMACER:1; /*!< bit: 7 Ram Access */
|
||||
__I uint16_t DCONN:1; /*!< bit: 8 Device Connection */
|
||||
__I uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */
|
||||
__I uint16_t :6; /*!< bit: 10..15 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} USB_HOST_INTFLAG_Type;
|
||||
@ -758,7 +755,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos)
|
||||
#define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */
|
||||
#define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos)
|
||||
#define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos)))
|
||||
#define USB_DEVICE_EPINTSMRY_EPINT(value) (USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))
|
||||
#define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */
|
||||
@ -804,7 +801,7 @@ typedef union {
|
||||
#define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos)
|
||||
#define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */
|
||||
#define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos)
|
||||
#define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos)))
|
||||
#define USB_HOST_PINTSMRY_EPINT(value) (USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))
|
||||
#define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */
|
||||
|
||||
/* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */
|
||||
@ -822,7 +819,7 @@ typedef union {
|
||||
|
||||
#define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */
|
||||
#define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos)
|
||||
#define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos)))
|
||||
#define USB_DESCADD_DESCADD(value) (USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))
|
||||
#define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */
|
||||
|
||||
/* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */
|
||||
@ -845,13 +842,13 @@ typedef union {
|
||||
|
||||
#define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */
|
||||
#define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos)
|
||||
#define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos)))
|
||||
#define USB_PADCAL_TRANSP(value) (USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))
|
||||
#define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */
|
||||
#define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos)
|
||||
#define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos)))
|
||||
#define USB_PADCAL_TRANSN(value) (USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))
|
||||
#define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */
|
||||
#define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos)
|
||||
#define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos)))
|
||||
#define USB_PADCAL_TRIM(value) (USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))
|
||||
#define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */
|
||||
@ -872,10 +869,10 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */
|
||||
#define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos)
|
||||
#define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos)))
|
||||
#define USB_DEVICE_EPCFG_EPTYPE0(value) (USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))
|
||||
#define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */
|
||||
#define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos)
|
||||
#define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos)))
|
||||
#define USB_DEVICE_EPCFG_EPTYPE1(value) (USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))
|
||||
#define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */
|
||||
#define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos)
|
||||
#define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */
|
||||
@ -898,12 +895,12 @@ typedef union {
|
||||
|
||||
#define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */
|
||||
#define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos)
|
||||
#define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos)))
|
||||
#define USB_HOST_PCFG_PTOKEN(value) (USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))
|
||||
#define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */
|
||||
#define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos)
|
||||
#define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */
|
||||
#define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos)
|
||||
#define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos)))
|
||||
#define USB_HOST_PCFG_PTYPE(value) (USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))
|
||||
#define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */
|
||||
@ -921,7 +918,7 @@ typedef union {
|
||||
|
||||
#define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */
|
||||
#define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos)
|
||||
#define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos)))
|
||||
#define USB_HOST_BINTERVAL_BITINTERVAL(value) (USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))
|
||||
#define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */
|
||||
@ -961,7 +958,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos)
|
||||
#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */
|
||||
#define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)
|
||||
#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos)))
|
||||
#define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) (USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))
|
||||
#define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */
|
||||
#define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos)
|
||||
#define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */
|
||||
@ -1037,7 +1034,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos)
|
||||
#define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */
|
||||
#define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)
|
||||
#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos)))
|
||||
#define USB_DEVICE_EPSTATUSSET_STALLRQ(value) (USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))
|
||||
#define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */
|
||||
#define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos)
|
||||
#define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */
|
||||
@ -1113,7 +1110,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos)
|
||||
#define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */
|
||||
#define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos)
|
||||
#define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos)))
|
||||
#define USB_DEVICE_EPSTATUS_STALLRQ(value) (USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))
|
||||
#define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */
|
||||
#define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos)
|
||||
#define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */
|
||||
@ -1154,23 +1151,23 @@ typedef union {
|
||||
|
||||
/* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
|
||||
uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
|
||||
uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
|
||||
uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
|
||||
uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
|
||||
uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
|
||||
uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
__I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
|
||||
__I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
|
||||
__I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
|
||||
__I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
|
||||
__I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
|
||||
__I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
|
||||
__I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
|
||||
__I uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
|
||||
uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
|
||||
uint8_t :1; /*!< bit: 4 Reserved */
|
||||
uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
__I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
|
||||
__I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
|
||||
__I uint8_t :1; /*!< bit: 4 Reserved */
|
||||
__I uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */
|
||||
__I uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} USB_DEVICE_EPINTFLAG_Type;
|
||||
@ -1185,14 +1182,14 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */
|
||||
#define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos)))
|
||||
#define USB_DEVICE_EPINTFLAG_TRCPT(value) (USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos)))
|
||||
#define USB_DEVICE_EPINTFLAG_TRFAIL(value) (USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))
|
||||
#define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */
|
||||
#define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */
|
||||
@ -1201,24 +1198,24 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */
|
||||
#define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos)
|
||||
#define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos)))
|
||||
#define USB_DEVICE_EPINTFLAG_STALL(value) (USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))
|
||||
#define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
|
||||
uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
|
||||
uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
|
||||
uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
|
||||
uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
|
||||
uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
|
||||
uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
__I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */
|
||||
__I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */
|
||||
__I uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */
|
||||
__I uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */
|
||||
__I uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */
|
||||
__I uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */
|
||||
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
struct {
|
||||
uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
__I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} vec; /*!< Structure used for vec access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} USB_HOST_PINTFLAG_Type;
|
||||
@ -1233,7 +1230,7 @@ typedef union {
|
||||
#define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos)
|
||||
#define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */
|
||||
#define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos)
|
||||
#define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos)))
|
||||
#define USB_HOST_PINTFLAG_TRCPT(value) (USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))
|
||||
#define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */
|
||||
#define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos)
|
||||
#define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */
|
||||
@ -1277,14 +1274,14 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos)))
|
||||
#define USB_DEVICE_EPINTENCLR_TRCPT(value) (USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos)))
|
||||
#define USB_DEVICE_EPINTENCLR_TRFAIL(value) (USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))
|
||||
#define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */
|
||||
@ -1293,7 +1290,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */
|
||||
#define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos)
|
||||
#define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos)))
|
||||
#define USB_DEVICE_EPINTENCLR_STALL(value) (USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))
|
||||
#define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */
|
||||
@ -1325,7 +1322,7 @@ typedef union {
|
||||
#define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos)
|
||||
#define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */
|
||||
#define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos)
|
||||
#define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos)))
|
||||
#define USB_HOST_PINTENCLR_TRCPT(value) (USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))
|
||||
#define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */
|
||||
#define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos)
|
||||
#define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */
|
||||
@ -1369,14 +1366,14 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */
|
||||
#define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos)))
|
||||
#define USB_DEVICE_EPINTENSET_TRCPT(value) (USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos)))
|
||||
#define USB_DEVICE_EPINTENSET_TRFAIL(value) (USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))
|
||||
#define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */
|
||||
#define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */
|
||||
@ -1385,7 +1382,7 @@ typedef union {
|
||||
#define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */
|
||||
#define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos)
|
||||
#define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos)))
|
||||
#define USB_DEVICE_EPINTENSET_STALL(value) (USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))
|
||||
#define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */
|
||||
@ -1417,7 +1414,7 @@ typedef union {
|
||||
#define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos)
|
||||
#define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */
|
||||
#define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos)
|
||||
#define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos)))
|
||||
#define USB_HOST_PINTENSET_TRCPT(value) (USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))
|
||||
#define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */
|
||||
#define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos)
|
||||
#define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */
|
||||
@ -1442,7 +1439,7 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */
|
||||
#define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos)
|
||||
#define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos)))
|
||||
#define USB_DEVICE_ADDR_ADDR(value) (USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))
|
||||
#define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */
|
||||
@ -1459,7 +1456,7 @@ typedef union {
|
||||
|
||||
#define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */
|
||||
#define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos)
|
||||
#define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos)))
|
||||
#define USB_HOST_ADDR_ADDR(value) (USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))
|
||||
#define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */
|
||||
@ -1479,13 +1476,13 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */
|
||||
#define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)
|
||||
#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos)))
|
||||
#define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) (USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))
|
||||
#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */
|
||||
#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)
|
||||
#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
|
||||
#define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))
|
||||
#define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */
|
||||
#define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos)
|
||||
#define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos)))
|
||||
#define USB_DEVICE_PCKSIZE_SIZE(value) (USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))
|
||||
#define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */
|
||||
#define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos)
|
||||
#define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */
|
||||
@ -1507,13 +1504,13 @@ typedef union {
|
||||
|
||||
#define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */
|
||||
#define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)
|
||||
#define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos)))
|
||||
#define USB_HOST_PCKSIZE_BYTE_COUNT(value) (USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))
|
||||
#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */
|
||||
#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)
|
||||
#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos)))
|
||||
#define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) (USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))
|
||||
#define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */
|
||||
#define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos)
|
||||
#define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos)))
|
||||
#define USB_HOST_PCKSIZE_SIZE(value) (USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))
|
||||
#define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */
|
||||
#define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos)
|
||||
#define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */
|
||||
@ -1534,10 +1531,10 @@ typedef union {
|
||||
|
||||
#define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */
|
||||
#define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos)
|
||||
#define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos)))
|
||||
#define USB_DEVICE_EXTREG_SUBPID(value) (USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))
|
||||
#define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */
|
||||
#define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos)
|
||||
#define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos)))
|
||||
#define USB_DEVICE_EXTREG_VARIABLE(value) (USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))
|
||||
#define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */
|
||||
@ -1556,10 +1553,10 @@ typedef union {
|
||||
|
||||
#define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */
|
||||
#define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos)
|
||||
#define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos)))
|
||||
#define USB_HOST_EXTREG_SUBPID(value) (USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))
|
||||
#define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */
|
||||
#define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos)
|
||||
#define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos)))
|
||||
#define USB_HOST_EXTREG_VARIABLE(value) (USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))
|
||||
#define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */
|
||||
|
||||
/* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */
|
||||
@ -1620,13 +1617,13 @@ typedef union {
|
||||
|
||||
#define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */
|
||||
#define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos)
|
||||
#define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos)))
|
||||
#define USB_HOST_CTRL_PIPE_PDADDR(value) (USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))
|
||||
#define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */
|
||||
#define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos)
|
||||
#define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos)))
|
||||
#define USB_HOST_CTRL_PIPE_PEPNUM(value) (USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))
|
||||
#define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */
|
||||
#define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos)
|
||||
#define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos)))
|
||||
#define USB_HOST_CTRL_PIPE_PERMAX(value) (USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))
|
||||
#define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */
|
||||
|
||||
/* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */
|
||||
@ -1659,7 +1656,7 @@ typedef union {
|
||||
#define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos)
|
||||
#define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */
|
||||
#define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos)
|
||||
#define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos)))
|
||||
#define USB_HOST_STATUS_PIPE_ERCNT(value) (USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))
|
||||
#define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */
|
||||
|
||||
/** \brief UsbDeviceDescBank SRAM registers */
|
||||
@ -1793,6 +1790,7 @@ typedef struct { /* USB is Host */
|
||||
UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */
|
||||
} UsbHostDescriptor;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define SECTION_USB_DESCRIPTOR
|
||||
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Component description for WDT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_COMPONENT_
|
||||
#define _SAMD21_WDT_COMPONENT_
|
||||
@ -97,7 +94,7 @@ typedef union {
|
||||
|
||||
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
|
||||
#define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
|
||||
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
|
||||
#define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
@ -124,7 +121,7 @@ typedef union {
|
||||
#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
|
||||
#define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
|
||||
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
|
||||
#define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
@ -167,7 +164,7 @@ typedef union {
|
||||
|
||||
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
|
||||
#define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
|
||||
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
|
||||
#define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
|
||||
@ -232,10 +229,10 @@ typedef union {
|
||||
|
||||
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTFLAG_Type;
|
||||
@ -281,7 +278,7 @@ typedef union {
|
||||
|
||||
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
|
||||
#define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
|
||||
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
|
||||
#define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
|
||||
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for AC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_INSTANCE_
|
||||
#define _SAMD21_AC_INSTANCE_
|
||||
@ -84,7 +81,7 @@
|
||||
#define AC_CMP_NUM 2 // Number of comparators
|
||||
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC_NUM_CMP 2
|
||||
#define AC_NUM_CMP 2
|
||||
#define AC_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for AC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -81,7 +81,7 @@
|
||||
#define AC1_CMP_NUM 2 // Number of comparators
|
||||
#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC1_NUM_CMP 2
|
||||
#define AC1_NUM_CMP 2
|
||||
#define AC1_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC1_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for ADC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_INSTANCE_
|
||||
#define _SAMD21_ADC_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for DAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_INSTANCE_
|
||||
#define _SAMD21_DAC_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for DMAC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_INSTANCE_
|
||||
#define _SAMD21_DMAC_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for DSU
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_INSTANCE_
|
||||
#define _SAMD21_DSU_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for EIC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_INSTANCE_
|
||||
#define _SAMD21_EIC_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_INSTANCE_
|
||||
#define _SAMD21_EVSYS_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for GCLK
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_INSTANCE_
|
||||
#define _SAMD21_GCLK_INSTANCE_
|
||||
@ -63,7 +60,7 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for GCLK peripheral ========== */
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for I2S
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_INSTANCE_
|
||||
#define _SAMD21_I2S_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for MTB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_INSTANCE_
|
||||
#define _SAMD21_MTB_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_INSTANCE_
|
||||
#define _SAMD21_NVMCTRL_INSTANCE_
|
||||
@ -77,16 +74,15 @@
|
||||
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
|
||||
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
|
||||
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
|
||||
#define NVMCTRL_FLASH_SIZE 65536
|
||||
#define NVMCTRL_FLASH_SIZE 65536
|
||||
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
|
||||
#define NVMCTRL_PAGES 1024
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
|
||||
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
|
||||
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for PAC0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC0_INSTANCE_
|
||||
#define _SAMD21_PAC0_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for PAC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC1_INSTANCE_
|
||||
#define _SAMD21_PAC1_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for PAC2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC2_INSTANCE_
|
||||
#define _SAMD21_PAC2_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for PM
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_INSTANCE_
|
||||
#define _SAMD21_PM_INSTANCE_
|
||||
@ -83,10 +80,10 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PM peripheral ========== */
|
||||
#define PM_CTRL_MCSEL_DFLL48M 3
|
||||
#define PM_CTRL_MCSEL_GCLK 0
|
||||
#define PM_CTRL_MCSEL_OSC8M 1
|
||||
#define PM_CTRL_MCSEL_XOSC 2
|
||||
#define PM_PM_CLK_APB_NUM 2
|
||||
#define PM_CTRL_MCSEL_DFLL48M 3
|
||||
#define PM_CTRL_MCSEL_GCLK 0
|
||||
#define PM_CTRL_MCSEL_OSC8M 1
|
||||
#define PM_CTRL_MCSEL_XOSC 2
|
||||
#define PM_PM_CLK_APB_NUM 2
|
||||
|
||||
#endif /* _SAMD21_PM_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for PORT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_INSTANCE_
|
||||
#define _SAMD21_PORT_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_INSTANCE_
|
||||
#define _SAMD21_RTC_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SBMATRIX
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SBMATRIX_INSTANCE_
|
||||
#define _SAMD21_SBMATRIX_INSTANCE_
|
||||
@ -149,7 +146,7 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SBMATRIX peripheral ========== */
|
||||
#define SBMATRIX_DEFINED
|
||||
#define SBMATRIX_DEFINED
|
||||
/* ========== Instance parameters for SBMATRIX ========== */
|
||||
#define SBMATRIX_SLAVE_FLASH 0
|
||||
#define SBMATRIX_SLAVE_HPB0 1
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM0_INSTANCE_
|
||||
#define _SAMD21_SERCOM0_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
|
||||
#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
|
||||
#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Synchronization Busy */
|
||||
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Synchronization Busy */
|
||||
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
|
||||
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
|
||||
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM0_INT_MSB 6
|
||||
#define SERCOM0_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM0_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM1_INSTANCE_
|
||||
#define _SAMD21_SERCOM1_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
|
||||
#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
|
||||
#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Synchronization Busy */
|
||||
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Synchronization Busy */
|
||||
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
|
||||
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
|
||||
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM1_INT_MSB 6
|
||||
#define SERCOM1_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM1_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM2_INSTANCE_
|
||||
#define _SAMD21_SERCOM2_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
|
||||
#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
|
||||
#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Synchronization Busy */
|
||||
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Synchronization Busy */
|
||||
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
|
||||
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
|
||||
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM2_INT_MSB 6
|
||||
#define SERCOM2_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM2_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM3
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM3_INSTANCE_
|
||||
#define _SAMD21_SERCOM3_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
|
||||
#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
|
||||
#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Synchronization Busy */
|
||||
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Synchronization Busy */
|
||||
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
|
||||
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
|
||||
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM3_INT_MSB 6
|
||||
#define SERCOM3_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM3_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM4
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM4_INSTANCE_
|
||||
#define _SAMD21_SERCOM4_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
|
||||
#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
|
||||
#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Synchronization Busy */
|
||||
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Synchronization Busy */
|
||||
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
|
||||
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
|
||||
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM4_INT_MSB 6
|
||||
#define SERCOM4_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM4_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SERCOM5
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM5_INSTANCE_
|
||||
#define _SAMD21_SERCOM5_INSTANCE_
|
||||
@ -56,7 +53,7 @@
|
||||
#define REG_SERCOM5_I2CM_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
@ -66,7 +63,7 @@
|
||||
#define REG_SERCOM5_I2CS_INTENSET (0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
|
||||
@ -76,7 +73,7 @@
|
||||
#define REG_SERCOM5_SPI_INTENSET (0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
|
||||
#define REG_SERCOM5_SPI_ADDR (0x42001C24U) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (0x42001C28U) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
@ -88,7 +85,7 @@
|
||||
#define REG_SERCOM5_USART_INTENSET (0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (0x42001C1AU) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
|
||||
#define REG_SERCOM5_USART_DATA (0x42001C28U) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#else
|
||||
@ -99,7 +96,7 @@
|
||||
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CM Synchronization Busy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
@ -109,7 +106,7 @@
|
||||
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) I2CS Synchronization Busy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28U) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00U) /**< \brief (SERCOM5) SPI Control A */
|
||||
@ -119,7 +116,7 @@
|
||||
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) SPI Synchronization Busy */
|
||||
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24U) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28U) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
@ -131,7 +128,7 @@
|
||||
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16U) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18U) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AU) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CU) /**< \brief (SERCOM5) USART Synchronization Busy */
|
||||
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28U) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30U) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
@ -141,6 +138,6 @@
|
||||
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
|
||||
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
|
||||
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM5_INT_MSB 6
|
||||
#define SERCOM5_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM5_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_INSTANCE_
|
||||
#define _SAMD21_SYSCTRL_INSTANCE_
|
||||
@ -93,31 +90,32 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SYSCTRL peripheral ========== */
|
||||
#define SYSCTRL_BGAP_CALIB_MSB 11
|
||||
#define SYSCTRL_BOD33_CALIB_MSB 5
|
||||
#define SYSCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define SYSCTRL_DFLL48M_FINE_MSB 9
|
||||
#define SYSCTRL_BGAP_CALIB_MSB 11
|
||||
#define SYSCTRL_BOD33_CALIB_MSB 5
|
||||
#define SYSCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define SYSCTRL_DFLL48M_FINE_MSB 9
|
||||
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
|
||||
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
|
||||
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
|
||||
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
#define SYSCTRL_POR33_ENTEST_MSB 1
|
||||
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
|
||||
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
|
||||
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
|
||||
#define SYSCTRL_VREF_CONTROL_MSB 48
|
||||
#define SYSCTRL_VREF_STATUS_MSB 7
|
||||
#define SYSCTRL_VREG_LEVEL_MSB 2
|
||||
#define SYSCTRL_BOD12_VERSION 0x111
|
||||
#define SYSCTRL_BOD33_VERSION 0x111
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x301
|
||||
#define SYSCTRL_FDPLL_VERSION 0x111
|
||||
#define SYSCTRL_OSCULP32K_VERSION 0x111
|
||||
#define SYSCTRL_OSC8M_VERSION 0x120
|
||||
#define SYSCTRL_OSC32K_VERSION 0x112
|
||||
#define SYSCTRL_VREF_VERSION 0x201
|
||||
#define SYSCTRL_VREG_VERSION 0x201
|
||||
#define SYSCTRL_XOSC_VERSION 0x114
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x113
|
||||
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
#define SYSCTRL_POR33_ENTEST_MSB 1
|
||||
#define SYSCTRL_SYSTEM_CLOCK 1000000 // Initial system clock frequency
|
||||
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
|
||||
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
|
||||
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
|
||||
#define SYSCTRL_VREF_CONTROL_MSB 48
|
||||
#define SYSCTRL_VREF_STATUS_MSB 7
|
||||
#define SYSCTRL_VREG_LEVEL_MSB 2
|
||||
#define SYSCTRL_BOD12_VERSION 0x112
|
||||
#define SYSCTRL_BOD33_VERSION 0x112
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x301
|
||||
#define SYSCTRL_FDPLL_VERSION 0x111
|
||||
#define SYSCTRL_OSCULP32K_VERSION 0x111
|
||||
#define SYSCTRL_OSC8M_VERSION 0x120
|
||||
#define SYSCTRL_OSC32K_VERSION 0x112
|
||||
#define SYSCTRL_VREF_VERSION 0x201
|
||||
#define SYSCTRL_VREG_VERSION 0x201
|
||||
#define SYSCTRL_XOSC_VERSION 0x114
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x113
|
||||
|
||||
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TC3
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC3_INSTANCE_
|
||||
#define _SAMD21_TC3_INSTANCE_
|
||||
@ -106,7 +103,7 @@
|
||||
#define TC3_DMAC_ID_MC_SIZE 2
|
||||
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
|
||||
#define TC3_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TC3_MASTER 0
|
||||
#define TC3_MASTER 0
|
||||
#define TC3_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC3_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TC4
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC4_INSTANCE_
|
||||
#define _SAMD21_TC4_INSTANCE_
|
||||
@ -106,7 +103,7 @@
|
||||
#define TC4_DMAC_ID_MC_SIZE 2
|
||||
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
|
||||
#define TC4_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC4_MASTER 1
|
||||
#define TC4_MASTER 1
|
||||
#define TC4_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC4_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TC5
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC5_INSTANCE_
|
||||
#define _SAMD21_TC5_INSTANCE_
|
||||
@ -106,7 +103,7 @@
|
||||
#define TC5_DMAC_ID_MC_SIZE 2
|
||||
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
|
||||
#define TC5_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC5_MASTER 0
|
||||
#define TC5_MASTER 0
|
||||
#define TC5_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC5_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TC6
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC6_INSTANCE_
|
||||
#define _SAMD21_TC6_INSTANCE_
|
||||
@ -106,7 +103,7 @@
|
||||
#define TC6_DMAC_ID_MC_SIZE 2
|
||||
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
|
||||
#define TC6_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC6_MASTER 1
|
||||
#define TC6_MASTER 1
|
||||
#define TC6_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC6_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC6_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TC7
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC7_INSTANCE_
|
||||
#define _SAMD21_TC7_INSTANCE_
|
||||
@ -106,7 +103,7 @@
|
||||
#define TC7_DMAC_ID_MC_SIZE 2
|
||||
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
|
||||
#define TC7_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC7_MASTER 0
|
||||
#define TC7_MASTER 0
|
||||
#define TC7_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC7_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC7_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TCC0
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC0_INSTANCE_
|
||||
#define _SAMD21_TCC0_INSTANCE_
|
||||
@ -124,11 +121,11 @@
|
||||
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
|
||||
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
|
||||
#define TCC0_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC0_MASTER 0
|
||||
#define TCC0_MASTER 0
|
||||
#define TCC0_OTMX 1 // Output Matrix feature implemented
|
||||
#define TCC0_OW_NUM 8 // Number of Output Waveforms
|
||||
#define TCC0_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC0_SIZE 24
|
||||
#define TCC0_SIZE 24
|
||||
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
|
||||
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TCC1
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC1_INSTANCE_
|
||||
#define _SAMD21_TCC1_INSTANCE_
|
||||
@ -112,11 +109,11 @@
|
||||
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC1_EXT 24 // Coding of implemented extended features
|
||||
#define TCC1_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC1_MASTER 1
|
||||
#define TCC1_MASTER 1
|
||||
#define TCC1_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC1_OW_NUM 4 // Number of Output Waveforms
|
||||
#define TCC1_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC1_SIZE 24
|
||||
#define TCC1_SIZE 24
|
||||
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for TCC2
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC2_INSTANCE_
|
||||
#define _SAMD21_TCC2_INSTANCE_
|
||||
@ -108,11 +105,11 @@
|
||||
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC2_EXT 0 // Coding of implemented extended features
|
||||
#define TCC2_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TCC2_MASTER 0
|
||||
#define TCC2_MASTER 0
|
||||
#define TCC2_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC2_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TCC2_PG 0 // Pattern Generation feature implemented
|
||||
#define TCC2_SIZE 16
|
||||
#define TCC2_SIZE 16
|
||||
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for USB
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_USB_INSTANCE_
|
||||
#define _SAMD21_USB_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Instance description for WDT
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2016 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_INSTANCE_
|
||||
#define _SAMD21_WDT_INSTANCE_
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E15A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E15A_
|
||||
#define _SAMD21E15A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -139,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -166,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -222,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -352,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -532,9 +530,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000DUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E15B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -124,7 +124,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -136,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -163,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -219,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -349,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -370,6 +371,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -443,6 +445,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -529,9 +532,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011427UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E15BU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -124,7 +124,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -136,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -163,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -219,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -349,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -370,6 +371,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -443,6 +445,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -529,14 +532,19 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011456UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */
|
||||
#define PORT_GROUPS 2
|
||||
#define PORT_GROUPS 1
|
||||
#define USB_HOST 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E15L
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -134,16 +134,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -155,27 +155,27 @@ typedef struct _DeviceVectors
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnReserved7;
|
||||
void* pvReserved7;
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnReserved26;
|
||||
void* pfnReserved27;
|
||||
void* pvReserved26;
|
||||
void* pvReserved27;
|
||||
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
|
||||
} DeviceVectors;
|
||||
|
||||
@ -215,6 +215,7 @@ void AC1_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -340,7 +341,7 @@ void AC1_Handler ( void );
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -361,6 +362,7 @@ void AC1_Handler ( void );
|
||||
#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -430,6 +432,7 @@ void AC1_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -508,9 +511,14 @@ void AC1_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001143FUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E16A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E16A_
|
||||
#define _SAMD21E16A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -139,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -166,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -222,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -352,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -532,9 +530,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000CUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E16B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -124,7 +124,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -136,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -163,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -219,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -349,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -370,6 +371,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -443,6 +445,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -529,9 +532,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011426UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E16BU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -124,7 +124,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -136,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -163,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -219,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -349,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -370,6 +371,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -443,6 +445,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -529,14 +532,19 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011455UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */
|
||||
#define PORT_GROUPS 2
|
||||
#define PORT_GROUPS 1
|
||||
#define USB_HOST 1
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E16L
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -134,16 +134,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -155,27 +155,27 @@ typedef struct _DeviceVectors
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnReserved7;
|
||||
void* pvReserved7;
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnReserved26;
|
||||
void* pfnReserved27;
|
||||
void* pvReserved26;
|
||||
void* pvReserved27;
|
||||
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
|
||||
} DeviceVectors;
|
||||
|
||||
@ -215,6 +215,7 @@ void AC1_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -340,7 +341,7 @@ void AC1_Handler ( void );
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -361,6 +362,7 @@ void AC1_Handler ( void );
|
||||
#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -430,6 +432,7 @@ void AC1_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -508,9 +511,14 @@ void AC1_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001143EUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E17A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E17A_
|
||||
#define _SAMD21E17A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -139,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -166,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -222,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -352,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -532,9 +530,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000BUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21E18A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21E18A_
|
||||
#define _SAMD21E18A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -139,16 +136,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -166,22 +163,22 @@ typedef struct _DeviceVectors
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
|
||||
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
|
||||
void* pfnReserved13;
|
||||
void* pfnReserved14;
|
||||
void* pvReserved13;
|
||||
void* pvReserved14;
|
||||
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
|
||||
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
|
||||
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -222,6 +219,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -352,7 +350,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -532,9 +530,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000AUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G15A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G15A_
|
||||
#define _SAMD21G15A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -141,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -176,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -226,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -360,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -544,9 +542,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010008UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G15B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -126,7 +126,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -138,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -173,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -223,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -357,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -378,6 +379,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -453,6 +455,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -541,9 +544,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011424UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G15L
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -138,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -159,7 +159,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnReserved7;
|
||||
void* pvReserved7;
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
@ -178,8 +178,8 @@ typedef struct _DeviceVectors
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnReserved26;
|
||||
void* pfnReserved27;
|
||||
void* pvReserved26;
|
||||
void* pvReserved27;
|
||||
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
|
||||
} DeviceVectors;
|
||||
|
||||
@ -223,6 +223,7 @@ void AC1_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -356,7 +357,7 @@ void AC1_Handler ( void );
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G16A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G16A_
|
||||
#define _SAMD21G16A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -141,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -176,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -226,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -360,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -544,9 +542,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010007UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G16B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -126,7 +126,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -138,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -173,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -223,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -357,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -378,6 +379,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -453,6 +455,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -541,9 +544,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011423UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G16L
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -138,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -159,7 +159,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
|
||||
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
|
||||
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
|
||||
void* pfnReserved7;
|
||||
void* pvReserved7;
|
||||
void* pfnEVSYS_Handler; /* 8 Event System Interface */
|
||||
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
|
||||
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
|
||||
@ -178,8 +178,8 @@ typedef struct _DeviceVectors
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnReserved26;
|
||||
void* pfnReserved27;
|
||||
void* pvReserved26;
|
||||
void* pvReserved27;
|
||||
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
|
||||
} DeviceVectors;
|
||||
|
||||
@ -223,6 +223,7 @@ void AC1_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -356,7 +357,7 @@ void AC1_Handler ( void );
|
||||
#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */
|
||||
#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */
|
||||
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G17A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G17A_
|
||||
#define _SAMD21G17A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -141,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -176,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -226,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -360,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -544,9 +542,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010006UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G17AU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G17AU_
|
||||
#define _SAMD21G17AU_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010010UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G18A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G18A_
|
||||
#define _SAMD21G18A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -141,16 +138,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -176,14 +173,14 @@ typedef struct _DeviceVectors
|
||||
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
|
||||
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
|
||||
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
|
||||
void* pfnReserved21;
|
||||
void* pfnReserved22;
|
||||
void* pvReserved21;
|
||||
void* pvReserved22;
|
||||
void* pfnADC_Handler; /* 23 Analog Digital Converter */
|
||||
void* pfnAC_Handler; /* 24 Analog Comparators */
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -226,6 +223,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -360,7 +358,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -544,9 +542,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010005UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21G18AU
|
||||
*
|
||||
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21G18AU_
|
||||
#define _SAMD21G18AU_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x1001000FUL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J15A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21J15A_
|
||||
#define _SAMD21J15A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010003UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J15B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -128,7 +128,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -140,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -182,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -227,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -365,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -386,6 +387,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -463,6 +465,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -553,9 +556,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 512
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011421UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J16A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21J16A_
|
||||
#define _SAMD21J16A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010002UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J16B
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -72,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -128,7 +128,7 @@ typedef enum IRQn
|
||||
PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
|
||||
I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
|
||||
|
||||
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
|
||||
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
|
||||
} IRQn_Type;
|
||||
|
||||
typedef struct _DeviceVectors
|
||||
@ -140,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -182,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -227,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -365,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -386,6 +387,7 @@ void I2S_Handler ( void );
|
||||
#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */
|
||||
#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */
|
||||
#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -463,6 +465,7 @@ void I2S_Handler ( void );
|
||||
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
|
||||
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
|
||||
|
||||
#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */
|
||||
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
|
||||
#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */
|
||||
#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */
|
||||
@ -553,9 +556,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 1024
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10011420UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J17A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21J17A_
|
||||
#define _SAMD21J17A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 2048
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010001UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
*
|
||||
* \brief Header file for SAMD21J18A
|
||||
*
|
||||
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
|
||||
* Copyright (c) 2017 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
@ -40,9 +40,6 @@
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
/*
|
||||
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21J18A_
|
||||
#define _SAMD21J18A_
|
||||
@ -75,7 +72,7 @@ typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatil
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
|
||||
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
|
||||
@ -143,16 +140,16 @@ typedef struct _DeviceVectors
|
||||
void* pfnReset_Handler;
|
||||
void* pfnNMI_Handler;
|
||||
void* pfnHardFault_Handler;
|
||||
void* pfnReservedM12;
|
||||
void* pfnReservedM11;
|
||||
void* pfnReservedM10;
|
||||
void* pfnReservedM9;
|
||||
void* pfnReservedM8;
|
||||
void* pfnReservedM7;
|
||||
void* pfnReservedM6;
|
||||
void* pvReservedM12;
|
||||
void* pvReservedM11;
|
||||
void* pvReservedM10;
|
||||
void* pvReservedM9;
|
||||
void* pvReservedM8;
|
||||
void* pvReservedM7;
|
||||
void* pvReservedM6;
|
||||
void* pfnSVC_Handler;
|
||||
void* pfnReservedM4;
|
||||
void* pfnReservedM3;
|
||||
void* pvReservedM4;
|
||||
void* pvReservedM3;
|
||||
void* pfnPendSV_Handler;
|
||||
void* pfnSysTick_Handler;
|
||||
|
||||
@ -185,7 +182,7 @@ typedef struct _DeviceVectors
|
||||
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
|
||||
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
|
||||
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
|
||||
void* pfnReserved28;
|
||||
void* pvReserved28;
|
||||
} DeviceVectors;
|
||||
|
||||
/* Cortex-M0+ processor handlers */
|
||||
@ -230,6 +227,7 @@ void I2S_Handler ( void );
|
||||
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define LITTLE_ENDIAN 1
|
||||
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
|
||||
@ -368,7 +366,7 @@ void I2S_Handler ( void );
|
||||
#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */
|
||||
#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */
|
||||
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */
|
||||
#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
@ -556,9 +554,14 @@ void I2S_Handler ( void );
|
||||
#define FLASH_NB_OF_PAGES 4096
|
||||
#define FLASH_USER_PAGE_SIZE 64
|
||||
#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */
|
||||
#define FLASH_ADDR (0x00000000UL) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */
|
||||
|
||||
#define FLASH_ADDR (0x00000000u) /**< FLASH base address */
|
||||
#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */
|
||||
#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */
|
||||
#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */
|
||||
#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */
|
||||
#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */
|
||||
#define PPB_ADDR (0xE0000000u) /**< PPB base address */
|
||||
|
||||
#define DSU_DID_RESETVALUE 0x10010000UL
|
||||
#define EIC_EXTINT_NUM 16
|
||||
|
||||
52
cpu/sam0_common/include/vendor/saml21/README.md
vendored
52
cpu/sam0_common/include/vendor/saml21/README.md
vendored
@ -1,52 +0,0 @@
|
||||
# CMSIS from Atmel Software Foundation (ASF)
|
||||
|
||||
The include files in the directory tree are copied from ASF. See
|
||||
https://spaces.atmel.com/gf/project/asf/frs/?action=FrsReleaseBrowse&frs_package_id=4
|
||||
(dd. 2016-11-07 ASF version 3.33.0 was used)
|
||||
|
||||
The directory tree was copied "as is" and its structure is as follows:
|
||||
|
||||
cmsis
|
||||
└── saml21
|
||||
├── include
|
||||
│ ├── component
|
||||
│ ├── instance
|
||||
│ └── pio
|
||||
├── include_b
|
||||
│ ├── component
|
||||
│ ├── instance
|
||||
│ └── pio
|
||||
└── source
|
||||
├── gcc
|
||||
└── iar
|
||||
|
||||
There is only one include file (per CPU variant) that should be included in
|
||||
the source code. For SAML21 that is cmsis/saml21/include/saml21.h. But
|
||||
that will only work if the proper define is set. The define is named after
|
||||
the variant, for example `__SAML21J18A__`. This define must be set in the
|
||||
`Makefile.include` of the board.
|
||||
|
||||
Be aware that if you want to make changes to any file in this tree that the
|
||||
changes will be lost when a new ASF release is going to be used.
|
||||
|
||||
## Trailing White Space
|
||||
|
||||
Because of the whitespace check (dist/tools/whitespacecheck/check.sh) all
|
||||
the trailing white space had to be removed. Please take this into account
|
||||
when comparing to the original ASF distribution.
|
||||
|
||||
find include/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
|
||||
find include_b/ -name '*.h' -exec sed -i 's/\s*$//' '{}' +
|
||||
|
||||
## LITTLE_ENDIAN
|
||||
|
||||
These include files define `LITTLE_ENDIAN`. But we think this is wrong. It
|
||||
seems more logical to let the compiler decide in which mode the ARM code is
|
||||
to be translated. In include/machine/endian.h there is already a define of
|
||||
`LITTLE_ENDIAN` (and `BIG_ENDIAN`) for a different purpose.
|
||||
|
||||
So, we decided to remove the define from the ASF CMSIS files. The command
|
||||
for it (running from this directory) is:
|
||||
|
||||
find include/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +
|
||||
find include_b/ -name '*.h' -exec sed -i '/^#define\s\s*LITTLE_ENDIAN/d' '{}' +
|
||||
@ -104,6 +104,6 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DSU peripheral ========== */
|
||||
#define DSU_CLK_AHB_ID 5
|
||||
#define DSU_CLK_AHB_ID 5
|
||||
|
||||
#endif /* _SAML21_DSU_INSTANCE_ */
|
||||
|
||||
@ -70,8 +70,8 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EIC peripheral ========== */
|
||||
#define EIC_GCLK_ID 3
|
||||
#define EIC_NUMBER_OF_CONFIG_REGS 2
|
||||
#define EIC_NUMBER_OF_INTERRUPTS 16
|
||||
#define EIC_GCLK_ID 3
|
||||
#define EIC_NUMBER_OF_CONFIG_REGS 2
|
||||
#define EIC_NUMBER_OF_INTERRUPTS 16
|
||||
|
||||
#endif /* _SAML21_EIC_INSTANCE_ */
|
||||
|
||||
@ -144,20 +144,20 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for GCLK peripheral ========== */
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
|
||||
#define GCLK_NUM 36 // Number of Generic Clock Users
|
||||
#define GCLK_SOURCE_DFLL48M 7
|
||||
#define GCLK_SOURCE_FDPLL 8
|
||||
#define GCLK_SOURCE_GCLKGEN1 2
|
||||
#define GCLK_SOURCE_GCLKIN 1
|
||||
#define GCLK_SOURCE_DFLL48M 7
|
||||
#define GCLK_SOURCE_FDPLL 8
|
||||
#define GCLK_SOURCE_GCLKGEN1 2
|
||||
#define GCLK_SOURCE_GCLKIN 1
|
||||
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
|
||||
#define GCLK_SOURCE_OSCULP32K 3
|
||||
#define GCLK_SOURCE_OSC16M 6
|
||||
#define GCLK_SOURCE_OSC32K 4
|
||||
#define GCLK_SOURCE_XOSC 0
|
||||
#define GCLK_SOURCE_XOSC32K 5
|
||||
#define GCLK_SOURCE_OSCULP32K 3
|
||||
#define GCLK_SOURCE_OSC16M 6
|
||||
#define GCLK_SOURCE_OSC32K 4
|
||||
#define GCLK_SOURCE_XOSC 0
|
||||
#define GCLK_SOURCE_XOSC32K 5
|
||||
|
||||
#endif /* _SAML21_GCLK_INSTANCE_ */
|
||||
|
||||
@ -76,9 +76,9 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for MCLK peripheral ========== */
|
||||
#define MCLK_CTRLA_MCSEL_GCLK 1
|
||||
#define MCLK_CTRLA_MCSEL_OSC8M 0
|
||||
#define MCLK_MCLK_CLK_APB_NUM 5
|
||||
#define MCLK_CTRLA_MCSEL_GCLK 1
|
||||
#define MCLK_CTRLA_MCSEL_OSC8M 0
|
||||
#define MCLK_MCLK_CLK_APB_NUM 5
|
||||
#define MCLK_SYSTEM_CLOCK 1000000 // System Clock Frequency at Reset
|
||||
|
||||
#endif /* _SAML21_MCLK_INSTANCE_ */
|
||||
|
||||
@ -75,20 +75,20 @@
|
||||
#define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register
|
||||
#define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock
|
||||
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF
|
||||
#define NVMCTRL_FLASH_SIZE 262144
|
||||
#define NVMCTRL_FLASH_SIZE 262144
|
||||
#define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test
|
||||
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
|
||||
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
|
||||
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF
|
||||
#define NVMCTRL_RWWEE_PAGES 128
|
||||
#define NVMCTRL_RWWEE_PAGES 128
|
||||
#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
|
||||
|
||||
#endif /* _SAML21_NVMCTRL_INSTANCE_ */
|
||||
|
||||
@ -66,6 +66,6 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
|
||||
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
|
||||
#endif /* _SAML21_OSC32KCTRL_INSTANCE_ */
|
||||
|
||||
@ -82,14 +82,14 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for OSCCTRL peripheral ========== */
|
||||
#define OSCCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define OSCCTRL_DFLL48M_FINE_MSB 9
|
||||
#define OSCCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define OSCCTRL_DFLL48M_FINE_MSB 9
|
||||
#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
|
||||
#define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
|
||||
#define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
|
||||
#define OSCCTRL_DFLL48M_VERSION 0x310
|
||||
#define OSCCTRL_FDPLL_VERSION 0x200
|
||||
#define OSCCTRL_OSC16M_VERSION 0x100
|
||||
#define OSCCTRL_XOSC_VERSION 0x120
|
||||
#define OSCCTRL_DFLL48M_VERSION 0x310
|
||||
#define OSCCTRL_FDPLL_VERSION 0x200
|
||||
#define OSCCTRL_OSC16M_VERSION 0x100
|
||||
#define OSCCTRL_XOSC_VERSION 0x120
|
||||
|
||||
#endif /* _SAML21_OSCCTRL_INSTANCE_ */
|
||||
|
||||
@ -106,14 +106,14 @@
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PORT peripheral ========== */
|
||||
#define PORT_BITS 84
|
||||
#define PORT_BITS 84
|
||||
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
|
||||
#define PORT_DRVSTR 1 // DRVSTR supported?
|
||||
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000D0000 }
|
||||
#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF, 0x00000000 }
|
||||
#define PORT_EV_NUM 4
|
||||
#define PORT_EV_NUM 4
|
||||
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
|
||||
#define PORT_ODRAIN 0 // ODRAIN supported?
|
||||
|
||||
@ -136,9 +136,9 @@
|
||||
/* ========== Instance parameters for SERCOM0 peripheral ========== */
|
||||
#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
|
||||
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
|
||||
#define SERCOM0_GCLK_ID_CORE 18
|
||||
#define SERCOM0_GCLK_ID_SLOW 17
|
||||
#define SERCOM0_INT_MSB 6
|
||||
#define SERCOM0_PMSB 3
|
||||
#define SERCOM0_GCLK_ID_CORE 18
|
||||
#define SERCOM0_GCLK_ID_SLOW 17
|
||||
#define SERCOM0_INT_MSB 6
|
||||
#define SERCOM0_PMSB 3
|
||||
|
||||
#endif /* _SAML21_SERCOM0_INSTANCE_ */
|
||||
|
||||
@ -136,9 +136,9 @@
|
||||
/* ========== Instance parameters for SERCOM1 peripheral ========== */
|
||||
#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
|
||||
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
|
||||
#define SERCOM1_GCLK_ID_CORE 19
|
||||
#define SERCOM1_GCLK_ID_SLOW 17
|
||||
#define SERCOM1_INT_MSB 6
|
||||
#define SERCOM1_PMSB 3
|
||||
#define SERCOM1_GCLK_ID_CORE 19
|
||||
#define SERCOM1_GCLK_ID_SLOW 17
|
||||
#define SERCOM1_INT_MSB 6
|
||||
#define SERCOM1_PMSB 3
|
||||
|
||||
#endif /* _SAML21_SERCOM1_INSTANCE_ */
|
||||
|
||||
@ -136,9 +136,9 @@
|
||||
/* ========== Instance parameters for SERCOM2 peripheral ========== */
|
||||
#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
|
||||
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
|
||||
#define SERCOM2_GCLK_ID_CORE 20
|
||||
#define SERCOM2_GCLK_ID_SLOW 17
|
||||
#define SERCOM2_INT_MSB 6
|
||||
#define SERCOM2_PMSB 3
|
||||
#define SERCOM2_GCLK_ID_CORE 20
|
||||
#define SERCOM2_GCLK_ID_SLOW 17
|
||||
#define SERCOM2_INT_MSB 6
|
||||
#define SERCOM2_PMSB 3
|
||||
|
||||
#endif /* _SAML21_SERCOM2_INSTANCE_ */
|
||||
|
||||
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Reference in New Issue
Block a user