sam0_common: add Watchdog implementation
This commit is contained in:
Benjamin Valentin
Benjamin Valentin
parent
04b92683e4
commit
c9f8ff1cf1
@ -4,5 +4,6 @@ FEATURES_PROVIDED += periph_flashpage_raw
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FEATURES_PROVIDED += periph_flashpage_rwee
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb
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-include $(RIOTCPU)/cortexm_common/Makefile.features
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@ -496,6 +496,26 @@ typedef struct {
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} sam0_common_usb_config_t;
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#endif /* USB_INST_NUM */
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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/* Limits are in clock cycles according to data sheet.
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As the WDT is clocked by a 1024 Hz clock, 1 cycle ≈ 1 ms */
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#define NWDT_TIME_LOWER_LIMIT (8U)
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#define NWDT_TIME_UPPER_LIMIT (16384U)
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/** @} */
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/**
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* @brief Watchdog can be stopped.
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*/
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#define WDT_HAS_STOP (1)
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/**
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* @brief Watchdog has to be initialized.
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*/
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#define WDT_HAS_INIT (1)
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#ifdef __cplusplus
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}
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#endif
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234
cpu/sam0_common/periph/wdt.c
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234
cpu/sam0_common/periph/wdt.c
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@ -0,0 +1,234 @@
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/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @ingroup drivers_periph_wdt
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* @{
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*
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* @file wdt.c
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* @brief Low-level WDT driver implementation
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "periph/wdt.h"
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#include "pm_layered.h"
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#include "board.h"
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#include "debug.h"
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#ifndef WDT_CLOCK_HZ
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#define WDT_CLOCK_HZ 1024
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#endif
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/* work around inconsistency in header files */
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#ifndef WDT_CONFIG_PER_8_Val
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#define WDT_CONFIG_PER_8_Val WDT_CONFIG_PER_CYC8_Val
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#endif
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#ifndef WDT_CONFIG_PER_8K_Val
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#define WDT_CONFIG_PER_8K_Val WDT_CONFIG_PER_CYC8192_Val
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#endif
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#ifndef WDT_CONFIG_PER_16K_Val
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#define WDT_CONFIG_PER_16K_Val WDT_CONFIG_PER_CYC16384_Val
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#endif
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static inline void _set_enable(bool on)
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{
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/* work around strange watchdog behaviour if IDLE2 is used on samd21 */
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#ifdef CPU_FAM_SAMD21
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if (on) {
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pm_block(1);
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}
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#endif
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#ifdef WDT_CTRLA_ENABLE
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WDT->CTRLA.bit.ENABLE = on;
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#else
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WDT->CTRL.bit.ENABLE = on;
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#endif
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}
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static inline void _wait_syncbusy(void)
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{
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#ifdef WDT_STATUS_SYNCBUSY
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while (WDT->STATUS.bit.SYNCBUSY) {}
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#else
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while (WDT->SYNCBUSY.reg) {}
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#endif
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}
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static uint32_t ms_to_per(uint32_t ms)
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{
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const uint32_t cycles = (ms * WDT_CLOCK_HZ) / 1024;
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/* Minimum WDT period is 8 clock cycles (register value 0) */
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if (cycles <= 8) {
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return 0;
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}
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/* Round up to next pow2 and calculate the register value */
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return 29 - __builtin_clz(cycles - 1);
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}
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#ifdef CPU_SAMD21
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static void _wdt_clock_setup(void)
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{
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/* RTC / RTT will alredy set up GCLK2 as needed */
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#if !defined(MODULE_PERIPH_RTC) && !defined(MODULE_PERIPH_RTT)
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/* Setup clock GCLK2 with OSCULP32K divided by 32 */
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GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(4);
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GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSCULP32K | GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_DIVSEL;
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while (GCLK->STATUS.bit.SYNCBUSY) {}
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#endif
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/* Connect to GCLK2 (~1.024 kHz) */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
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| GCLK_CLKCTRL_GEN_GCLK2
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| GCLK_CLKCTRL_CLKEN;
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}
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#else
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static void _wdt_clock_setup(void)
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{
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/* nothing to do here */
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}
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#endif
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void wdt_init(void)
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{
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_wdt_clock_setup();
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#ifdef MCLK
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MCLK->APBAMASK.bit.WDT_ = 1;
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#else
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PM->APBAMASK.bit.WDT_ = 1;
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#endif
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_set_enable(0);
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NVIC_EnableIRQ(WDT_IRQn);
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}
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void wdt_setup_reboot(uint32_t min_time, uint32_t max_time)
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{
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uint32_t per, win;
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if (max_time == 0) {
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DEBUG("invalid period: max_time = %"PRIu32"\n", max_time);
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return;
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}
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per = ms_to_per(max_time);
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if (per > WDT_CONFIG_PER_16K_Val) {
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DEBUG("invalid period: max_time = %"PRIu32"\n", max_time);
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return;
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}
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if (min_time) {
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win = ms_to_per(min_time);
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if (win > WDT_CONFIG_PER_8K_Val) {
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DEBUG("invalid period: min_time = %"PRIu32"\n", min_time);
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return;
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}
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if (per < win) {
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per = win + 1;
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}
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#ifdef WDT_CTRLA_WEN
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WDT->CTRLA.bit.WEN = 1;
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#else
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WDT->CTRL.bit.WEN = 1;
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#endif
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} else {
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win = 0;
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#ifdef WDT_CTRLA_WEN
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WDT->CTRLA.bit.WEN = 0;
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#else
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WDT->CTRL.bit.WEN = 0;
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#endif
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}
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WDT->INTFLAG.reg = WDT_INTFLAG_EW;
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DEBUG("watchdog window: %"PRIu32", period: %"PRIu32"\n", win, per);
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WDT->CONFIG.reg = WDT_CONFIG_WINDOW(win) | WDT_CONFIG_PER(per);
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_wait_syncbusy();
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}
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void wdt_stop(void)
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{
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_set_enable(0);
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_wait_syncbusy();
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}
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void wdt_start(void)
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{
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_set_enable(1);
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_wait_syncbusy();
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}
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void wdt_kick(void)
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{
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WDT->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val;
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}
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#ifdef MODULE_PERIPH_WDT_CB
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static wdt_cb_t cb;
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static void* cb_arg;
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void wdt_setup_reboot_with_callback(uint32_t min_time, uint32_t max_time,
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wdt_cb_t wdt_cb, void *arg)
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{
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uint32_t per = ms_to_per(max_time);
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if (per == WDT_CONFIG_PER_8_Val && wdt_cb) {
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DEBUG("period too short for early warning\n");
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return;
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}
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cb = wdt_cb;
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cb_arg = arg;
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if (cb != NULL) {
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uint32_t warning_offset = ms_to_per(WDT_WARNING_PERIOD);
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if (warning_offset == 0) {
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warning_offset = 1;
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}
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if (warning_offset >= per) {
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warning_offset = per - 1;
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}
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WDT->INTENSET.reg = WDT_INTENSET_EW;
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WDT->EWCTRL.bit.EWOFFSET = per - warning_offset;
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} else {
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WDT->INTENCLR.reg = WDT_INTENCLR_EW;
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}
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wdt_setup_reboot(min_time, max_time);
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}
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void isr_wdt(void)
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{
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WDT->INTFLAG.reg = WDT_INTFLAG_EW;
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if (cb != NULL) {
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cb(cb_arg);
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}
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cortexm_isr_end();
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}
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#endif /* MODULE_PERIPH_WDT_CB */
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