boards/sam%21-xpro: prefer XOSC32K for RTC/RTT (GCLK2)
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@ -63,7 +63,16 @@ extern "C" {
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#define CLOCK_USE_PLL (1)
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#define CLOCK_USE_XOSC32_DFLL (0)
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/*
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* 0: use XOSC32K (always 32.768kHz) to clock GCLK2
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* 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
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*
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* OSCULP32K is factory calibrated to be around 32.768kHz but this values can
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* be of by a couple off % points, so prefer XOSC32K as default configuration.
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*/
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#define GEN2_ULP32K (0)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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@ -76,7 +85,6 @@ extern "C" {
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#define CLOCK_CORECLOCK (48000000U)
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#define CLOCK_XOSC32K (32768UL)
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#define CLOCK_8MHZ (1)
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#define GEN2_ULP32K (1)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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@ -63,7 +63,16 @@ extern "C" {
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#define CLOCK_USE_PLL (1)
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#define CLOCK_USE_XOSC32_DFLL (0)
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/*
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* 0: use XOSC32K (always 32.768kHz) to clock GCLK2
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* 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
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*
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* OSCULP32K is factory calibrated to be around 32.768kHz but this values can
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* be of by a couple off % points, so prefer XOSC32K as default configuration.
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*/
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#define GEN2_ULP32K (0)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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@ -76,7 +85,6 @@ extern "C" {
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#define CLOCK_CORECLOCK (48000000U)
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#define CLOCK_XOSC32K (32768UL)
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#define CLOCK_8MHZ (1)
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#define GEN2_ULP32K (1)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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