From cbf78fe3d416bfebc1a6c0c664408b46dcb2bf00 Mon Sep 17 00:00:00 2001
From: Francisco Molina <femolina@uc.cl>
Date: Tue, 18 Aug 2020 15:41:04 +0200
Subject: [PATCH] cpu/efm32: allow running both LETIMER and regular timer

---
 cpu/efm32/include/periph_cpu.h | 18 ++++--------------
 cpu/efm32/periph/timer.c       | 24 +++++++++++++++++-------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/cpu/efm32/include/periph_cpu.h b/cpu/efm32/include/periph_cpu.h
index 4260578814..963a87f7dc 100644
--- a/cpu/efm32/include/periph_cpu.h
+++ b/cpu/efm32/include/periph_cpu.h
@@ -357,28 +357,18 @@ typedef struct {
     timer_dev_t prescaler;  /**< the lower neighboring timer (not initialized for LETIMER) */
     timer_dev_t timer;      /**< the higher numbered timer */
     IRQn_Type irq;          /**< number of the higher timer IRQ channel */
+    uint8_t channel_numof;       /**< number of channels per timer */
 } timer_conf_t;
 /** @} */
 
 
 /**
- * @brief   The implementation can use one LETIMER or two regular timers cascaded
+ * @brief   Use LETIMER as the base timer for XTIMER
  */
-#ifndef CONFIG_EFM32_USE_LETIMER
-#define CONFIG_EFM32_USE_LETIMER   0
+#ifndef CONFIG_EFM32_XTIMER_USE_LETIMER
+#define CONFIG_EFM32_XTIMER_USE_LETIMER   0
 #endif
 
-#if IS_ACTIVE(CONFIG_EFM32_USE_LETIMER)
-/**
- * @brief   This timer implementation has two available channels
- */
-#define TIMER_CHANNEL_NUMOF     (2)
-#else
-/**
- * @brief   This timer implementation has three available channels
- */
-#define TIMER_CHANNEL_NUMOF     (3)
-#endif
 
 /**
  * @brief   UART device configuration.
diff --git a/cpu/efm32/periph/timer.c b/cpu/efm32/periph/timer.c
index b7219b5342..08fd27f17b 100644
--- a/cpu/efm32/periph/timer.c
+++ b/cpu/efm32/periph/timer.c
@@ -165,7 +165,7 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
     if (!_is_letimer(dev)) {
         TIMER_TypeDef *tim = timer_config[dev].timer.dev;
 
-        if (channel < 0 || channel >= TIMER_CHANNEL_NUMOF) {
+        if (channel < 0 || channel >= timer_config[dev].channel_numof) {
             return -1;
         }
 
@@ -278,15 +278,12 @@ void timer_start(tim_t dev)
     }
 }
 
-#ifdef TIMER_0_ISR
-void TIMER_0_ISR(void)
+static void _timer_isr(tim_t dev)
 {
-    tim_t dev = 0;
-
     if (_is_letimer(dev)) {
         LETIMER_TypeDef *tim = timer_config[dev].timer.dev;
 
-        for (int i = 0; i < TIMER_CHANNEL_NUMOF; i++) {
+        for (int i = 0; i < timer_config[dev].channel_numof; i++) {
             if (tim->IF & (LETIMER_IF_COMP0 << i))
             {
                 LETIMER_IntDisable(tim, LETIMER_IEN_COMP0 << i);
@@ -298,7 +295,7 @@ void TIMER_0_ISR(void)
     else {
         TIMER_TypeDef *tim = timer_config[dev].timer.dev;
 
-        for (int i = 0; i < TIMER_CHANNEL_NUMOF; i++) {
+        for (int i = 0; i < timer_config[dev].channel_numof; i++) {
             if (tim->IF & (TIMER_IF_CC0 << i)) {
                 tim->CC[i].CTRL = _TIMER_CC_CTRL_MODE_OFF;
                 tim->IFC = (TIMER_IFC_CC0 << i);
@@ -308,4 +305,17 @@ void TIMER_0_ISR(void)
     }
     cortexm_isr_end();
 }
+
+#ifdef TIMER_0_ISR
+void TIMER_0_ISR(void)
+{
+    _timer_isr(0);
+}
 #endif /* TIMER_0_ISR */
+
+#ifdef TIMER_1_ISR
+void TIMER_1_ISR(void)
+{
+    _timer_isr(1);
+}
+#endif /* TIMER_1_ISR */