diff --git a/cpu/sam0_common/include/vendor/README.md b/cpu/sam0_common/include/vendor/README.md index f662d39cee..1dfb70fba7 100644 --- a/cpu/sam0_common/include/vendor/README.md +++ b/cpu/sam0_common/include/vendor/README.md @@ -60,6 +60,13 @@ saml11: `Atmel.SAML11_DFP.1.0.91.atpack` Each atpack has an include subdirectory with the files we copy into RIOT. The files are copied unmodified. +## SAML21 files + +saml21: `Atmel.SAML21_DFP.1.2.125.atpack` + +Each atpack has an include subdirectory with the files we copy into +RIOT. The files are copied unmodified. + ## SAMR21 files samr21: `Atmel.SAMR21_DFP.1.1.72.atpack` diff --git a/cpu/sam0_common/include/vendor/saml21/include/component-version.h b/cpu/sam0_common/include/vendor/saml21/include/component-version.h new file mode 100644 index 0000000000..9241f25e2d --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 125 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-08-31 15:02:56" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/cpu/sam0_common/include/vendor/saml21/include/component/ac.h b/cpu/sam0_common/include/vendor/saml21/include/component/ac.h index 7ffdaea796..d7f1c11e42 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/component/ac.h +++ b/cpu/sam0_common/include/vendor/saml21/include/component/ac.h @@ -1,600 +1,586 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_AC_COMPONENT_ -#define _SAML21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAML21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2245 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK 0x03ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (0x3ul << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK 0x3313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK 0x03ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (0x1ul << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK 0x01ul /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (0x1ul << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x7ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val 0x4ul /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_MEDLOW_Val 0x1ul /**< \brief (AC_COMPCTRL) Medium low speed */ -#define AC_COMPCTRL_SPEED_MEDHIGH_Val 0x2ul /**< \brief (AC_COMPCTRL) Medium high speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x3ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (0x1ul << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (0x3ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val 0x0ul /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST70_Val 0x1ul /**< \brief (AC_COMPCTRL) 70mV */ -#define AC_COMPCTRL_HYST_HYST90_Val 0x2ul /**< \brief (AC_COMPCTRL) 90mV */ -#define AC_COMPCTRL_HYST_HYST110_Val 0x3ul /**< \brief (AC_COMPCTRL) 110mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK 0x373BF75Eul /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (0x1ul << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (0x1ul << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (0x1ul << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (0x3ul << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK 0x0000001Ful /**< \brief (AC_SYNCBUSY) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_AC_COMPONENT_ +#define _SAML21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAML21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_MEDLOW_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Medium low speed */ +#define AC_COMPCTRL_SPEED_MEDHIGH_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Medium high speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST70_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 70mV */ +#define AC_COMPCTRL_HYST_HYST90_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 90mV */ +#define AC_COMPCTRL_HYST_HYST110_Val _U_(0x3) /**< \brief (AC_COMPCTRL) 110mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/component/adc_100.h b/cpu/sam0_common/include/vendor/saml21/include/component/adc_100.h index a583d05ac2..3673c346f3 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/component/adc_100.h +++ b/cpu/sam0_common/include/vendor/saml21/include/component/adc_100.h @@ -1,760 +1,728 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_ADC_COMPONENT_ -#define _SAML21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAML21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2247 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (0x1ul << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_MASK 0xC3ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x00ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV2_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x07ul /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0ul /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5ul /**< \brief (ADC_REFCTRL) VCCANA */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (0x1ul << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (0x1ul << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (0x1ul << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x3Ful /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK 0x07ul /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK 0x07ul /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK 0x07ul /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SEQSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ -#define ADC_SEQSTATUS_RESETVALUE 0x00ul /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ - -#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ -#define ADC_SEQSTATUS_SEQSTATE_Msk (0x1Ful << ADC_SEQSTATUS_SEQSTATE_Pos) -#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) -#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ -#define ADC_SEQSTATUS_SEQBUSY (0x1ul << ADC_SEQSTATUS_SEQBUSY_Pos) -#define ADC_SEQSTATUS_MASK 0x9Ful /**< \brief (ADC_SEQSTATUS) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x0000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val 0x14ul /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val 0x15ul /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val 0x16ul /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val 0x17ul /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val 0x1Dul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP01_Val 0x1Eul /**< \brief (ADC_INPUTCTRL) OPAMP0 or OPAMP1 output */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP2_Val 0x1Ful /**< \brief (ADC_INPUTCTRL) OPAMP2 output */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP01 (ADC_INPUTCTRL_MUXPOS_OPAMP01_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP2 (ADC_INPUTCTRL_MUXPOS_OPAMP2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MASK 0x1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ -#define ADC_CTRLC_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLC reset_value) Control C */ - -#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ -#define ADC_CTRLC_DIFFMODE (0x1ul << ADC_CTRLC_DIFFMODE_Pos) -#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ -#define ADC_CTRLC_LEFTADJ (0x1ul << ADC_CTRLC_LEFTADJ_Pos) -#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ -#define ADC_CTRLC_FREERUN (0x1ul << ADC_CTRLC_FREERUN_Pos) -#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ -#define ADC_CTRLC_CORREN (0x1ul << ADC_CTRLC_CORREN_Pos) -#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ -#define ADC_CTRLC_RESSEL_Msk (0x3ul << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) -#define ADC_CTRLC_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLC) 12-bit result */ -#define ADC_CTRLC_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLC) For averaging mode output */ -#define ADC_CTRLC_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLC) 10-bit result */ -#define ADC_CTRLC_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLC) 8-bit result */ -#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ -#define ADC_CTRLC_WINMODE_Msk (0x7ul << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) -#define ADC_CTRLC_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_CTRLC) No window mode (default) */ -#define ADC_CTRLC_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_CTRLC) RESULT > WINLT */ -#define ADC_CTRLC_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_CTRLC) RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_MASK 0x073Ful /**< \brief (ADC_CTRLC) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (0x1ul << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK 0xBFul /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint16_t AVGCTRL:1; /*!< bit: 2 AVGCTRL Synchronization Busy */ - uint16_t SAMPCTRL:1; /*!< bit: 3 SAMPCTRL Synchronization Busy */ - uint16_t CTRLC:1; /*!< bit: 4 CTRLC Synchronization Busy */ - uint16_t INPUTCTRL:1; /*!< bit: 5 INPUTCTRL Synchronization Busy */ - uint16_t OFFSETCORR:1; /*!< bit: 6 OFFSETCTRL Synchronization Busy */ - uint16_t GAINCORR:1; /*!< bit: 7 GAINCORR Synchronization Busy */ - uint16_t WINLT:1; /*!< bit: 8 WINLT Synchronization Busy */ - uint16_t WINUT:1; /*!< bit: 9 WINUT Synchronization Busy */ - uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (0x1ul << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (0x1ul << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (0x1ul << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 3 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (0x1ul << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_CTRLC_Pos 4 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLC (0x1ul << ADC_SYNCBUSY_CTRLC_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (0x1ul << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 6 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (0x1ul << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 7 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (0x1ul << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 8 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (0x1ul << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 9 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (0x1ul << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (0x1ul << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK 0x07FFul /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ -#define ADC_SEQCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ - -#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ -#define ADC_SEQCTRL_SEQEN_Msk (0xFFFFFFFFul << ADC_SEQCTRL_SEQEN_Pos) -#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) -#define ADC_SEQCTRL_MASK 0xFFFFFFFFul /**< \brief (ADC_SEQCTRL) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (0x7ul << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (0x7ul << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK 0x0707ul /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ - __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ - RoReg8 Reserved1[0x2]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x3]; - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ - RoReg8 Reserved3[0x3]; - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ - RoReg8 Reserved4[0x2]; - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ - RoReg8 Reserved5[0x2]; - __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_ADC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_ADC_COMPONENT_ +#define _SAML21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAML21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK _U_(0xC3) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VCCANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) +#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) +#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_MASK _U_(0x073F) /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 2 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 3 SAMPCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 4 CTRLC Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 5 INPUTCTRL Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 6 OFFSETCTRL Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 7 GAINCORR Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 8 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 9 WINUT Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 3 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 4 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 6 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 7 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 8 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 9 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) +#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/component/aes.h b/cpu/sam0_common/include/vendor/saml21/include/component/aes.h index 7bba3fbd59..193232bd64 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/component/aes.h +++ b/cpu/sam0_common/include/vendor/saml21/include/component/aes.h @@ -1,347 +1,325 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_AES_COMPONENT_ -#define _SAML21_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAML21_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x100 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ - uint32_t LOD:1; /*!< bit: 12 LOD Enable */ - uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ - uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE 0x00000000ul /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (0x1ul << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (0x1ul << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (0x7ul << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ -#define AES_CTRLA_CFBS_Msk (0x7ul << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ -#define AES_CTRLA_KEYSIZE_Msk (0x3ul << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ -#define AES_CTRLA_CIPHER (0x1ul << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ -#define AES_CTRLA_STARTMODE (0x1ul << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ -#define AES_CTRLA_LOD (0x1ul << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ -#define AES_CTRLA_KEYGEN (0x1ul << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ -#define AES_CTRLA_XORKEY (0x1ul << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ -#define AES_CTRLA_CTYPE_Msk (0xFul << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK 0x000F7FFFul /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Manual Start */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE 0x00ul /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ -#define AES_CTRLB_START (0x1ul << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (0x1ul << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (0x1ul << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (0x1ul << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK 0x0Ful /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE 0x00ul /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ -#define AES_INTENCLR_ENCCMP (0x1ul << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_0_Val 0x0ul /**< \brief (AES_INTENCLR) 1 (no division) */ -#define AES_INTENCLR_ENCCMP_1_Val 0x1ul /**< \brief (AES_INTENCLR) 2 */ -#define AES_INTENCLR_ENCCMP_2_Val 0x2ul /**< \brief (AES_INTENCLR) 4 */ -#define AES_INTENCLR_ENCCMP_3_Val 0x3ul /**< \brief (AES_INTENCLR) 8 */ -#define AES_INTENCLR_ENCCMP_0 (AES_INTENCLR_ENCCMP_0_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_1 (AES_INTENCLR_ENCCMP_1_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_2 (AES_INTENCLR_ENCCMP_2_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_3 (AES_INTENCLR_ENCCMP_3_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ -#define AES_INTENCLR_GFMCMP (0x1ul << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK 0x03ul /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE 0x00ul /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ -#define AES_INTENSET_ENCCMP (0x1ul << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ -#define AES_INTENSET_GFMCMP (0x1ul << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK 0x03ul /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE 0x00ul /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (0x1ul << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (0x1ul << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK 0x03ul /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE 0x00ul /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (0x3ul << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK 0x03ul /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (0x1ul << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK 0x01ul /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE 0x00000000ul /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK 0xFFFFFFFFul /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE 0x00000000ul /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK 0xFFFFFFFFul /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE 0x00000000ul /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK 0xFFFFFFFFul /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE 0x00000000ul /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK 0xFFFFFFFFul /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE 0x00000000ul /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK 0xFFFFFFFFul /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE 0x00000000ul /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK 0xFFFFFFFFul /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE 0x00000000ul /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK 0xFFFFFFFFul /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AES_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_AES_COMPONENT_ +#define _SAML21_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAML21_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x100 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ + uint32_t LOD:1; /*!< bit: 12 LOD Enable */ + uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ + uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Manual Start */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/component/ccl.h b/cpu/sam0_common/include/vendor/saml21/include/component/ccl.h index 279ecef914..180a5c6975 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/component/ccl.h +++ b/cpu/sam0_common/include/vendor/saml21/include/component/ccl.h @@ -1,202 +1,188 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_CCL_COMPONENT_ -#define _SAML21_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAML21_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x100 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE 0x00ul /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (0x1ul << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (0x1ul << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ -#define CCL_CTRL_RUNSTDBY (0x1ul << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK 0x43ul /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE 0x00ul /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (0xFul << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val 0x0ul /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val 0x1ul /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val 0x2ul /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val 0x3ul /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val 0x4ul /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK 0x0Ful /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ - uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE 0x00000000ul /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (0x1ul << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (0x3ul << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val 0x0ul /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val 0x1ul /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val 0x2ul /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (0x1ul << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (0xFul << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val 0x0ul /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val 0x1ul /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val 0x2ul /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val 0x3ul /**< \brief (CCL_LUTCTRL) Event in put source */ -#define CCL_LUTCTRL_INSEL0_IO_Val 0x4ul /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val 0x5ul /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val 0x6ul /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val 0x7ul /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val 0x8ul /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val 0x9ul /**< \brief (CCL_LUTCTRL) SERCOM inout source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (0xFul << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (0xFul << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ -#define CCL_LUTCTRL_INVEI (0x1ul << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (0x1ul << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (0x1ul << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (0xFFul << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK 0xFF7FFFB2ul /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_CCL_COMPONENT_ */ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_CCL_COMPONENT_ +#define _SAML21_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAML21_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x100 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/component/dac.h b/cpu/sam0_common/include/vendor/saml21/include/component/dac.h index f598d10304..40a2fb842b 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/component/dac.h +++ b/cpu/sam0_common/include/vendor/saml21/include/component/dac.h @@ -1,471 +1,455 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_DAC_COMPONENT_ -#define _SAML21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAML21_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2244 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK 0x03ul /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (0x1ul << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val 0x0ul /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val 0x1ul /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val 0x2ul /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val 0x3ul /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK 0x07ul /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (0x3ul << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (0x3ul << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (0x3ul << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_MASK 0x3Ful /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENCLR_UNDERRUN_Msk (0x3ul << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (0x3ul << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_MASK 0x0Ful /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENSET_UNDERRUN_Msk (0x3ul << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (0x3ul << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_MASK 0x0Ful /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (0x3ul << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (0x3ul << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_MASK 0x0Ful /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (0x3ul << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (0x3ul << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK 0x0Ful /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (0x1ul << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (0x1ul << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (0x3ul << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (0x3ul << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK 0x0000003Ful /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DACx Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DACx Control */ -#define DAC_DACCTRL_RESETVALUE 0x0000ul /**< \brief (DAC_DACCTRL reset_value) DACx Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (0x1ul << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (0x1ul << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (0x3ul << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC12M_Val 0x0ul /**< \brief (DAC_DACCTRL) 1MHz -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E18A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E18A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E18A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E18A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E18A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E18A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E18A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E18A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E18A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 14, /**< 14 SAML21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E18A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E18A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E18A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E18A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E18A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E18A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnReserved12; - void* pfnReserved13; - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc_100.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic_100.h" -#include "component/evsys.h" -#include "component/gclk_100.h" -#include "component/mclk_100.h" -#include "component/mtb.h" -#include "component/nvmctrl_301.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac_100.h" -#include "component/pm_100.h" -#include "component/port.h" -#include "component/rstc_100.h" -#include "component/rtc_100.h" -#include "component/sercom.h" -#include "component/supc_100.h" -#include "component/tal.h" -#include "component/tc_100.h" -#include "component/tcc_200.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc_100.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic_100.h" -#include "instance/evsys.h" -#include "instance/gclk_100.h" -#include "instance/mclk_100.h" -#include "instance/mtb.h" -#include "instance/nvmctrl_301.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac_100.h" -#include "instance/pm_100.h" -#include "instance/port.h" -#include "instance/rstc_100.h" -#include "instance/rtc_100.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/supc_100.h" -#include "instance/tal.h" -#include "instance/tc0_100.h" -#include "instance/tc1_100.h" -#include "instance/tc4_100.h" -#include "instance/tcc0_200.h" -#include "instance/tcc1_200.h" -#include "instance/tcc2_200.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ -/** \defgroup SAML21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1081000AUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E18A_H */ +/** + * \file + * + * \brief Header file for SAML21E18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21E18A_ +#define _SAML21E18A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E18A_definitions SAML21E18A definitions + * This file defines all structures and symbols for SAML21E18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21E18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 14, /**< 14 SAML21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E18A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E18A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E18A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E18A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E18A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pvReserved12; + void* pvReserved13; + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc_100.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic_100.h" +#include "component/evsys.h" +#include "component/gclk_100.h" +#include "component/mclk_100.h" +#include "component/mtb.h" +#include "component/nvmctrl_301.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac_100.h" +#include "component/pm_100.h" +#include "component/port.h" +#include "component/rstc_100.h" +#include "component/rtc_100.h" +#include "component/sercom.h" +#include "component/supc_100.h" +#include "component/tc_100.h" +#include "component/tcc_200.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc_100.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic_100.h" +#include "instance/evsys.h" +#include "instance/gclk_100.h" +#include "instance/mclk_100.h" +#include "instance/mtb.h" +#include "instance/nvmctrl_301.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac_100.h" +#include "instance/pm_100.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc_100.h" +#include "instance/rtc_100.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/supc_100.h" +#include "instance/tc0_100.h" +#include "instance/tc1_100.h" +#include "instance/tc4_100.h" +#include "instance/tcc0_200.h" +#include "instance/tcc1_200.h" +#include "instance/tcc2_200.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ +/** \defgroup SAML21E18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081000A) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E18A_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/saml21g18a.h b/cpu/sam0_common/include/vendor/saml21/include/saml21g18a.h index a5769a6018..4e1cae186a 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/saml21g18a.h +++ b/cpu/sam0_common/include/vendor/saml21/include/saml21g18a.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21G18A - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21G18A_ -#define _SAML21G18A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G18A_definitions SAML21G18A definitions - * This file defines all structures and symbols for SAML21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G18A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G18A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G18A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G18A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G18A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G18A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G18A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G18A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G18A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G18A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G18A Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G18A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G18A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G18A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G18A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc_100.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic_100.h" -#include "component/evsys.h" -#include "component/gclk_100.h" -#include "component/mclk_100.h" -#include "component/mtb.h" -#include "component/nvmctrl_301.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac_100.h" -#include "component/pm_100.h" -#include "component/port.h" -#include "component/rstc_100.h" -#include "component/rtc_100.h" -#include "component/sercom.h" -#include "component/supc_100.h" -#include "component/tal.h" -#include "component/tc_100.h" -#include "component/tcc_200.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc_100.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic_100.h" -#include "instance/evsys.h" -#include "instance/gclk_100.h" -#include "instance/mclk_100.h" -#include "instance/mtb.h" -#include "instance/nvmctrl_301.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac_100.h" -#include "instance/pm_100.h" -#include "instance/port.h" -#include "instance/rstc_100.h" -#include "instance/rtc_100.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc_100.h" -#include "instance/tal.h" -#include "instance/tc0_100.h" -#include "instance/tc1_100.h" -#include "instance/tc4_100.h" -#include "instance/tcc0_200.h" -#include "instance/tcc1_200.h" -#include "instance/tcc2_200.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ -/** \defgroup SAML21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810005UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G18A_H */ +/** + * \file + * + * \brief Header file for SAML21G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21G18A_ +#define _SAML21G18A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G18A_definitions SAML21G18A definitions + * This file defines all structures and symbols for SAML21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21G18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G18A Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G18A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G18A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G18A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G18A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc_100.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic_100.h" +#include "component/evsys.h" +#include "component/gclk_100.h" +#include "component/mclk_100.h" +#include "component/mtb.h" +#include "component/nvmctrl_301.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac_100.h" +#include "component/pm_100.h" +#include "component/port.h" +#include "component/rstc_100.h" +#include "component/rtc_100.h" +#include "component/sercom.h" +#include "component/supc_100.h" +#include "component/tc_100.h" +#include "component/tcc_200.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc_100.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic_100.h" +#include "instance/evsys.h" +#include "instance/gclk_100.h" +#include "instance/mclk_100.h" +#include "instance/mtb.h" +#include "instance/nvmctrl_301.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac_100.h" +#include "instance/pm_100.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc_100.h" +#include "instance/rtc_100.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc_100.h" +#include "instance/tc0_100.h" +#include "instance/tc1_100.h" +#include "instance/tc4_100.h" +#include "instance/tcc0_200.h" +#include "instance/tcc1_200.h" +#include "instance/tcc2_200.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ +/** \defgroup SAML21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810005) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G18A_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/saml21j18a.h b/cpu/sam0_common/include/vendor/saml21/include/saml21j18a.h index 1de9bddafb..fd77a5592e 100644 --- a/cpu/sam0_common/include/vendor/saml21/include/saml21j18a.h +++ b/cpu/sam0_common/include/vendor/saml21/include/saml21j18a.h @@ -1,649 +1,636 @@ -/** - * \file - * - * \brief Header file for SAML21J18A - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21J18A_ -#define _SAML21J18A_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J18A_definitions SAML21J18A definitions - * This file defines all structures and symbols for SAML21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J18A-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J18A System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J18A Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J18A Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J18A 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J18A Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J18A Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J18A Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J18A Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J18A Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J18A Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J18A Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J18A Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J18A Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J18A True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc_100.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic_100.h" -#include "component/evsys.h" -#include "component/gclk_100.h" -#include "component/mclk_100.h" -#include "component/mtb.h" -#include "component/nvmctrl_301.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac_100.h" -#include "component/pm_100.h" -#include "component/port.h" -#include "component/rstc_100.h" -#include "component/rtc_100.h" -#include "component/sercom.h" -#include "component/supc_100.h" -#include "component/tal.h" -#include "component/tc_100.h" -#include "component/tcc_200.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc_100.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic_100.h" -#include "instance/evsys.h" -#include "instance/gclk_100.h" -#include "instance/mclk_100.h" -#include "instance/mtb.h" -#include "instance/nvmctrl_301.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac_100.h" -#include "instance/pm_100.h" -#include "instance/port.h" -#include "instance/rstc_100.h" -#include "instance/rtc_100.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc_100.h" -#include "instance/tal.h" -#include "instance/tc0_100.h" -#include "instance/tc1_100.h" -#include "instance/tc2_100.h" -#include "instance/tc3_100.h" -#include "instance/tc4_100.h" -#include "instance/tcc0_200.h" -#include "instance/tcc1_200.h" -#include "instance/tcc2_200.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ -/** \defgroup SAML21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810000UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J18A_H */ +/** + * \file + * + * \brief Header file for SAML21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J18A_ +#define _SAML21J18A_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J18A_definitions SAML21J18A definitions + * This file defines all structures and symbols for SAML21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J18A-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J18A System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J18A Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J18A Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J18A Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J18A Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J18A Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J18A True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc_100.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic_100.h" +#include "component/evsys.h" +#include "component/gclk_100.h" +#include "component/mclk_100.h" +#include "component/mtb.h" +#include "component/nvmctrl_301.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac_100.h" +#include "component/pm_100.h" +#include "component/port.h" +#include "component/rstc_100.h" +#include "component/rtc_100.h" +#include "component/sercom.h" +#include "component/supc_100.h" +#include "component/tc_100.h" +#include "component/tcc_200.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc_100.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic_100.h" +#include "instance/evsys.h" +#include "instance/gclk_100.h" +#include "instance/mclk_100.h" +#include "instance/mtb.h" +#include "instance/nvmctrl_301.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac_100.h" +#include "instance/pm_100.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc_100.h" +#include "instance/rtc_100.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc_100.h" +#include "instance/tc0_100.h" +#include "instance/tc1_100.h" +#include "instance/tc2_100.h" +#include "instance/tc3_100.h" +#include "instance/tc4_100.h" +#include "instance/tcc0_200.h" +#include "instance/tcc1_200.h" +#include "instance/tcc2_200.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ +/** \defgroup SAML21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810000) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J18A_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include/system_saml21.h b/cpu/sam0_common/include/vendor/saml21/include/system_saml21.h new file mode 100644 index 0000000000..51a00d3db5 --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include/system_saml21.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAML21_H_INCLUDED_ +#define _SYSTEM_SAML21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAML21_H_INCLUDED */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component-version.h b/cpu/sam0_common/include/vendor/saml21/include_b/component-version.h new file mode 100644 index 0000000000..ccb89fd918 --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 125 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-08-31 15:02:57" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component/ac.h b/cpu/sam0_common/include/vendor/saml21/include_b/component/ac.h index 5007a415c0..6e32540d61 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/component/ac.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component/ac.h @@ -1,600 +1,586 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_AC_COMPONENT_ -#define _SAML21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAML21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2245 -#define REV_AC 0x101 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK 0x03ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (1 << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (1 << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (0x3ul << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK 0x3313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK 0x03ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (0x1ul << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK 0x01ul /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (0x1ul << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x7ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val 0x4ul /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_MEDLOW_Val 0x1ul /**< \brief (AC_COMPCTRL) Medium low speed */ -#define AC_COMPCTRL_SPEED_MEDHIGH_Val 0x2ul /**< \brief (AC_COMPCTRL) Medium high speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x3ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (0x1ul << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (0x3ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val 0x0ul /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST70_Val 0x1ul /**< \brief (AC_COMPCTRL) 70mV */ -#define AC_COMPCTRL_HYST_HYST90_Val 0x2ul /**< \brief (AC_COMPCTRL) 90mV */ -#define AC_COMPCTRL_HYST_HYST110_Val 0x3ul /**< \brief (AC_COMPCTRL) 110mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK 0x373BF75Eul /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (0x1ul << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (0x1ul << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (0x1ul << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (1 << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (1 << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (0x3ul << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK 0x0000001Ful /**< \brief (AC_SYNCBUSY) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_AC_COMPONENT_ +#define _SAML21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAML21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2245 +#define REV_AC 0x101 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_MEDLOW_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Medium low speed */ +#define AC_COMPCTRL_SPEED_MEDHIGH_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Medium high speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDLOW (AC_COMPCTRL_SPEED_MEDLOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_MEDHIGH (AC_COMPCTRL_SPEED_MEDHIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST70_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 70mV */ +#define AC_COMPCTRL_HYST_HYST90_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 90mV */ +#define AC_COMPCTRL_HYST_HYST110_Val _U_(0x3) /**< \brief (AC_COMPCTRL) 110mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST70 (AC_COMPCTRL_HYST_HYST70_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST90 (AC_COMPCTRL_HYST_HYST90_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST110 (AC_COMPCTRL_HYST_HYST110_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AC_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component/adc.h b/cpu/sam0_common/include/vendor/saml21/include_b/component/adc.h index 6cd03e0a93..0a0ff3f95a 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/component/adc.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component/adc.h @@ -1,760 +1,728 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_ADC_COMPONENT_ -#define _SAML21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAML21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2247 -#define REV_ADC 0x110 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (0x1ul << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_MASK 0xC3ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x00ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV2_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x07ul /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val 0x0ul /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC2_Val 0x5ul /**< \brief (ADC_REFCTRL) VCCANA */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (0x1ul << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (0x1ul << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (0x1ul << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x3Ful /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK 0x07ul /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK 0x07ul /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK 0x07ul /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ - uint8_t :2; /*!< bit: 5.. 6 Reserved */ - uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SEQSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ -#define ADC_SEQSTATUS_RESETVALUE 0x00ul /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ - -#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ -#define ADC_SEQSTATUS_SEQSTATE_Msk (0x1Ful << ADC_SEQSTATUS_SEQSTATE_Pos) -#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) -#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ -#define ADC_SEQSTATUS_SEQBUSY (0x1ul << ADC_SEQSTATUS_SEQBUSY_Pos) -#define ADC_SEQSTATUS_MASK 0x9Ful /**< \brief (ADC_SEQSTATUS) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :3; /*!< bit: 13..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x0000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val 0x14ul /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val 0x15ul /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val 0x16ul /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val 0x17ul /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val 0x1Dul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP01_Val 0x1Eul /**< \brief (ADC_INPUTCTRL) OPAMP0 or OPAMP1 output */ -#define ADC_INPUTCTRL_MUXPOS_OPAMP2_Val 0x1Ful /**< \brief (ADC_INPUTCTRL) OPAMP2 output */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP01 (ADC_INPUTCTRL_MUXPOS_OPAMP01_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_OPAMP2 (ADC_INPUTCTRL_MUXPOS_OPAMP2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MASK 0x1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ -#define ADC_CTRLC_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLC reset_value) Control C */ - -#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ -#define ADC_CTRLC_DIFFMODE (0x1ul << ADC_CTRLC_DIFFMODE_Pos) -#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ -#define ADC_CTRLC_LEFTADJ (0x1ul << ADC_CTRLC_LEFTADJ_Pos) -#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ -#define ADC_CTRLC_FREERUN (0x1ul << ADC_CTRLC_FREERUN_Pos) -#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ -#define ADC_CTRLC_CORREN (0x1ul << ADC_CTRLC_CORREN_Pos) -#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ -#define ADC_CTRLC_RESSEL_Msk (0x3ul << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) -#define ADC_CTRLC_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLC) 12-bit result */ -#define ADC_CTRLC_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLC) For averaging mode output */ -#define ADC_CTRLC_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLC) 10-bit result */ -#define ADC_CTRLC_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLC) 8-bit result */ -#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) -#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ -#define ADC_CTRLC_WINMODE_Msk (0x7ul << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) -#define ADC_CTRLC_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_CTRLC) No window mode (default) */ -#define ADC_CTRLC_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_CTRLC) RESULT > WINLT */ -#define ADC_CTRLC_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_CTRLC) RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ -#define ADC_CTRLC_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) -#define ADC_CTRLC_MASK 0x073Ful /**< \brief (ADC_CTRLC) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (0x1ul << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK 0xBFul /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ - uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ - uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ - uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ - uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ - uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ - uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ - uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ - uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE 0x0000ul /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (0x1ul << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (0x1ul << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (0x1ul << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLC (0x1ul << ADC_SYNCBUSY_CTRLC_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (0x1ul << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (0x1ul << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (0x1ul << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (0x1ul << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (0x1ul << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (0x1ul << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (0x1ul << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK 0x07FFul /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ -#define ADC_SEQCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ - -#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ -#define ADC_SEQCTRL_SEQEN_Msk (0xFFFFFFFFul << ADC_SEQCTRL_SEQEN_Pos) -#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) -#define ADC_SEQCTRL_MASK 0xFFFFFFFFul /**< \brief (ADC_SEQCTRL) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (0x7ul << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (0x7ul << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK 0x0707ul /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ - __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ - RoReg8 Reserved1[0x2]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x3]; - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ - RoReg8 Reserved3[0x3]; - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ - RoReg8 Reserved4[0x2]; - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ - RoReg8 Reserved5[0x2]; - __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_ADC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_ADC_COMPONENT_ +#define _SAML21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAML21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2247 +#define REV_ADC 0x111 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run during Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_MASK _U_(0xC3) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */ +#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VCCANA */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */ + uint8_t :2; /*!< bit: 5.. 6 Reserved */ + uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SEQSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */ +#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */ + +#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */ +#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos) +#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos)) +#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */ +#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos) +#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :3; /*!< bit: 13..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */ +#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */ + +#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */ +#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos) +#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */ +#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos) +#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */ +#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos) +#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */ +#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos) +#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */ +#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos)) +#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */ +#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */ +#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */ +#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */ +#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos) +#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */ +#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos)) +#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */ +#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */ +#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */ +#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos) +#define ADC_CTRLC_MASK _U_(0x073F) /**< \brief (ADC_CTRLC) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */ + uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */ + uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */ + uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */ + uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */ + uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */ + uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ + uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */ + uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */ +#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */ + +#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */ +#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos) +#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos)) +#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */ + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */ + __IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */ + RoReg8 Reserved1[0x2]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x3]; + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */ + RoReg8 Reserved3[0x3]; + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */ + RoReg8 Reserved4[0x2]; + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */ + RoReg8 Reserved5[0x2]; + __IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_ADC_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component/aes.h b/cpu/sam0_common/include/vendor/saml21/include_b/component/aes.h index 34151f0507..b1cab7f1d9 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/component/aes.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component/aes.h @@ -1,347 +1,325 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_AES_COMPONENT_ -#define _SAML21_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAML21_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x200 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ - uint32_t LOD:1; /*!< bit: 12 LOD Enable */ - uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ - uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE 0x00000000ul /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (0x1ul << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (0x1ul << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (0x7ul << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ -#define AES_CTRLA_CFBS_Msk (0x7ul << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ -#define AES_CTRLA_KEYSIZE_Msk (0x3ul << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ -#define AES_CTRLA_CIPHER (0x1ul << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ -#define AES_CTRLA_STARTMODE (0x1ul << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ -#define AES_CTRLA_LOD (0x1ul << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ -#define AES_CTRLA_KEYGEN (0x1ul << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ -#define AES_CTRLA_XORKEY (0x1ul << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ -#define AES_CTRLA_CTYPE_Msk (0xFul << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK 0x000F7FFFul /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Manual Start */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE 0x00ul /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ -#define AES_CTRLB_START (0x1ul << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (0x1ul << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (0x1ul << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (0x1ul << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK 0x0Ful /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE 0x00ul /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ -#define AES_INTENCLR_ENCCMP (0x1ul << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_0_Val 0x0ul /**< \brief (AES_INTENCLR) 1 (no division) */ -#define AES_INTENCLR_ENCCMP_1_Val 0x1ul /**< \brief (AES_INTENCLR) 2 */ -#define AES_INTENCLR_ENCCMP_2_Val 0x2ul /**< \brief (AES_INTENCLR) 4 */ -#define AES_INTENCLR_ENCCMP_3_Val 0x3ul /**< \brief (AES_INTENCLR) 8 */ -#define AES_INTENCLR_ENCCMP_0 (AES_INTENCLR_ENCCMP_0_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_1 (AES_INTENCLR_ENCCMP_1_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_2 (AES_INTENCLR_ENCCMP_2_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_ENCCMP_3 (AES_INTENCLR_ENCCMP_3_Val << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ -#define AES_INTENCLR_GFMCMP (0x1ul << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK 0x03ul /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE 0x00ul /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ -#define AES_INTENSET_ENCCMP (0x1ul << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ -#define AES_INTENSET_GFMCMP (0x1ul << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK 0x03ul /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE 0x00ul /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (0x1ul << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (0x1ul << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK 0x03ul /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE 0x00ul /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (0x3ul << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK 0x03ul /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE 0x00ul /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (0x1ul << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK 0x01ul /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE 0x00000000ul /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK 0xFFFFFFFFul /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE 0x00000000ul /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK 0xFFFFFFFFul /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE 0x00000000ul /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK 0xFFFFFFFFul /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE 0x00000000ul /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK 0xFFFFFFFFul /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE 0x00000000ul /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK 0xFFFFFFFFul /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE 0x00000000ul /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK 0xFFFFFFFFul /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE 0x00000000ul /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK 0xFFFFFFFFul /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_AES_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_AES_COMPONENT_ +#define _SAML21_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAML21_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x200 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 CFB Types */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Keysize */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start mode */ + uint32_t LOD:1; /*!< bit: 12 LOD Enable */ + uint32_t KEYGEN:1; /*!< bit: 13 Last key generation */ + uint32_t XORKEY:1; /*!< bit: 14 Xor Key operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter measure types */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) CFB Types */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Keysize */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start mode */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) LOD Enable */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last key generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) Xor Key operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter measure types */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Manual Start */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Manual Start */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) ( /W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __O AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 ( /W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_AES_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component/ccl.h b/cpu/sam0_common/include/vendor/saml21/include_b/component/ccl.h index 8db6d1d0a9..18121fba21 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/component/ccl.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component/ccl.h @@ -1,202 +1,188 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_CCL_COMPONENT_ -#define _SAML21_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAML21_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x101 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE 0x00ul /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (0x1ul << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (0x1ul << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ -#define CCL_CTRL_RUNSTDBY (0x1ul << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK 0x43ul /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE 0x00ul /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (0xFul << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val 0x0ul /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val 0x1ul /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val 0x2ul /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val 0x3ul /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val 0x4ul /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK 0x0Ful /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ - uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE 0x00000000ul /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (0x1ul << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (0x3ul << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val 0x0ul /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val 0x1ul /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val 0x2ul /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (0x1ul << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (0xFul << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val 0x0ul /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val 0x1ul /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val 0x2ul /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val 0x3ul /**< \brief (CCL_LUTCTRL) Event in put source */ -#define CCL_LUTCTRL_INSEL0_IO_Val 0x4ul /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val 0x5ul /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val 0x6ul /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val 0x7ul /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val 0x8ul /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val 0x9ul /**< \brief (CCL_LUTCTRL) SERCOM inout source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (0xFul << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (0xFul << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ -#define CCL_LUTCTRL_INVEI (0x1ul << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (0x1ul << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (0x1ul << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (0xFFul << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK 0xFF7FFFB2ul /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAML21_CCL_COMPONENT_ */ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21_CCL_COMPONENT_ +#define _SAML21_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAML21_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x101 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ + uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAML21_CCL_COMPONENT_ */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/component/dac.h b/cpu/sam0_common/include/vendor/saml21/include_b/component/dac.h index f54f2a1d67..17d19da090 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/component/dac.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/component/dac.h @@ -1,471 +1,455 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21_DAC_COMPONENT_ -#define _SAML21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAML21_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2244 -#define REV_DAC 0x111 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK 0x03ul /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (0x1ul << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val 0x0ul /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val 0x1ul /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val 0x2ul /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val 0x3ul /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK 0x07ul /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (1 << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (1 << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (0x3ul << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (1 << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (1 << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (0x3ul << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (1 << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (1 << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (0x3ul << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_MASK 0x3Ful /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENCLR_UNDERRUN0 (1 << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENCLR_UNDERRUN1 (1 << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENCLR_UNDERRUN_Msk (0x3ul << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (1 << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (1 << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (0x3ul << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_MASK 0x0Ful /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ -#define DAC_INTENSET_UNDERRUN0 (1 << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ -#define DAC_INTENSET_UNDERRUN1 (1 << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ -#define DAC_INTENSET_UNDERRUN_Msk (0x3ul << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (1 << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (1 << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (0x3ul << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_MASK 0x0Ful /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (1 << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (1 << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (0x3ul << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (1 << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (1 << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (0x3ul << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_MASK 0x0Ful /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (1 << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (1 << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (0x3ul << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (1 << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (1 << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (0x3ul << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK 0x0Ful /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (0x1ul << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (0x1ul << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (1 << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (1 << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (0x3ul << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (1 << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (1 << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (0x3ul << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK 0x0000003Ful /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :2; /*!< bit: 4.. 5 Reserved */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE 0x0000ul /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (0x1ul << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (0x1ul << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (0x3ul << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC12M_Val 0x0ul /**< \brief (DAC_DACCTRL) 1MHz -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E15B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E15B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E15B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E15B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E15B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E15B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E15B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E15B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E15B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E15B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E15B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21E15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21E15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21E15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E15B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E15B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E15B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E15B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E15B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E15B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E15B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E15B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E15B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E15B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ -/** \defgroup SAML21E15B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x1000UL /* 4 kB */ -#define LPRAM_SIZE 0x800UL /* 2 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1081011CUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E15B_H */ +/** + * \file + * + * \brief Header file for SAML21E15B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21E15B_ +#define _SAML21E15B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E15B_definitions SAML21E15B definitions + * This file defines all structures and symbols for SAML21E15B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21E15B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E15B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21E15B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E15B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E15B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E15B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E15B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E15B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E15B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E15B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E15B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E15B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E15B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21E15B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21E15B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21E15B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E15B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E15B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E15B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E15B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E15B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E15B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E15B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E15B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E15B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E15B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E15B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ +/** \defgroup SAML21E15B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e15b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */ +#define LPRAM_SIZE _UL_(0x00000800) /* 2 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081021C) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E15B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E15B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e16b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e16b.h index 80cd07b4da..9445b8b35b 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e16b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e16b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21E16B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21E16B_ -#define _SAML21E16B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E16B_definitions SAML21E16B definitions - * This file defines all structures and symbols for SAML21E16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E16B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E16B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E16B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E16B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E16B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E16B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E16B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E16B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E16B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E16B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E16B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21E16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21E16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21E16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E16B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E16B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E16B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E16B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E16B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E16B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E16B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E16B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E16B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E16B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ -/** \defgroup SAML21E16B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1081011BUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E16B_H */ +/** + * \file + * + * \brief Header file for SAML21E16B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21E16B_ +#define _SAML21E16B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E16B_definitions SAML21E16B definitions + * This file defines all structures and symbols for SAML21E16B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21E16B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E16B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21E16B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E16B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E16B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21E16B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21E16B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21E16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E16B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E16B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E16B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E16B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E16B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E16B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E16B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E16B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E16B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E16B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ +/** \defgroup SAML21E16B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e16b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define LPRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081021B) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E16B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E16B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e17b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e17b.h index 4d67042125..35ddcbdc2e 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e17b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e17b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21E17B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21E17B_ -#define _SAML21E17B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E17B_definitions SAML21E17B definitions - * This file defines all structures and symbols for SAML21E17B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E17B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E17B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E17B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E17B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E17B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E17B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E17B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E17B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E17B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E17B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E17B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E17B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E17B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E17B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E17B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E17B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E17B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E17B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E17B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E17B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21E17B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21E17B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21E17B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E17B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E17B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E17B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E17B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E17B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E17B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E17B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E17B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E17B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E17B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E17B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ -/** \defgroup SAML21E17B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e17b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1081011AUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E17B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E17B_H */ +/** + * \file + * + * \brief Header file for SAML21E17B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21E17B_ +#define _SAML21E17B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E17B_definitions SAML21E17B definitions + * This file defines all structures and symbols for SAML21E17B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21E17B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E17B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21E17B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E17B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E17B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E17B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E17B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E17B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E17B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E17B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E17B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E17B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E17B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21E17B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21E17B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21E17B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E17B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E17B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E17B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E17B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E17B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E17B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E17B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E17B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E17B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E17B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E17B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ +/** \defgroup SAML21E17B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e17b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081021A) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E17B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E17B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e18b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e18b.h index 3656ab28c2..8e37d5ebb7 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21e18b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21e18b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21E18B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21E18B_ -#define _SAML21E18B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21E18B_definitions SAML21E18B definitions - * This file defines all structures and symbols for SAML21E18B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21E18B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21E18B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21E18B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21E18B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21E18B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21E18B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21E18B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21E18B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21E18B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21E18B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21E18B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21E18B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21E18B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21E18B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21E18B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21E18B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21E18B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21E18B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21E18B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21E18B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21E18B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21E18B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21E18B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21E18B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21E18B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21E18B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21E18B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21E18B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21E18B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21E18B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21E18B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21E18B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21E18B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21E18B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ -/** \defgroup SAML21E18B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21e18b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810119UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 1 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21E18B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21E18B_H */ +/** + * \file + * + * \brief Header file for SAML21E18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21E18B_ +#define _SAML21E18B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21E18B_definitions SAML21E18B definitions + * This file defines all structures and symbols for SAML21E18B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21E18B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21E18B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21E18B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21E18B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21E18B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21E18B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21E18B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21E18B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21E18B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21E18B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21E18B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21E18B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21E18B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21E18B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21E18B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21E18B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21E18B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21E18B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21E18B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21E18B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21E18B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21E18B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21E18B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21E18B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21E18B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21E18B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21E18B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ +/** \defgroup SAML21E18B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21e18b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810219) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 1 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21E18B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21E18B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g16b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g16b.h index 4e63be88e4..dabdf83c69 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g16b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g16b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21G16B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21G16B_ -#define _SAML21G16B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G16B_definitions SAML21G16B definitions - * This file defines all structures and symbols for SAML21G16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G16B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G16B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G16B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G16B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G16B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G16B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G16B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G16B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G16B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G16B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G16B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G16B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G16B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G16B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G16B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G16B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G16B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G16B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G16B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G16B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G16B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ -/** \defgroup SAML21G16B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810116UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G16B_H */ +/** + * \file + * + * \brief Header file for SAML21G16B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21G16B_ +#define _SAML21G16B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G16B_definitions SAML21G16B definitions + * This file defines all structures and symbols for SAML21G16B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21G16B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G16B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21G16B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G16B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G16B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G16B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G16B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G16B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G16B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G16B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G16B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G16B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G16B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G16B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G16B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G16B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G16B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ +/** \defgroup SAML21G16B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g16b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define LPRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810216) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G16B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G16B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g17b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g17b.h index 53dcce6224..bfdfb6dc10 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g17b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g17b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21G17B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21G17B_ -#define _SAML21G17B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G17B_definitions SAML21G17B definitions - * This file defines all structures and symbols for SAML21G17B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G17B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G17B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G17B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G17B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G17B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G17B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G17B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G17B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G17B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G17B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G17B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G17B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G17B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G17B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G17B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G17B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G17B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G17B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G17B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G17B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G17B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G17B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G17B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G17B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G17B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G17B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G17B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G17B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G17B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G17B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G17B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G17B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G17B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G17B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ -/** \defgroup SAML21G17B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g17b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810115UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G17B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G17B_H */ +/** + * \file + * + * \brief Header file for SAML21G17B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21G17B_ +#define _SAML21G17B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G17B_definitions SAML21G17B definitions + * This file defines all structures and symbols for SAML21G17B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21G17B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G17B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21G17B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G17B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G17B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G17B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G17B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G17B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G17B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G17B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G17B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G17B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G17B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G17B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G17B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G17B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G17B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G17B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G17B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G17B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G17B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G17B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G17B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G17B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G17B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G17B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G17B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ +/** \defgroup SAML21G17B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g17b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810215) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G17B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G17B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g18b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g18b.h index c6815a9c5f..1f43c2c4a8 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21g18b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21g18b.h @@ -1,637 +1,624 @@ -/** - * \file - * - * \brief Header file for SAML21G18B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21G18B_ -#define _SAML21G18B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21G18B_definitions SAML21G18B definitions - * This file defines all structures and symbols for SAML21G18B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21G18B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21G18B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21G18B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21G18B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21G18B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21G18B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21G18B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21G18B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21G18B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21G18B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21G18B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21G18B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21G18B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21G18B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21G18B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21G18B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21G18B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21G18B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21G18B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21G18B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21G18B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21G18B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21G18B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21G18B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21G18B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21G18B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21G18B Basic Timer Counter 1 (TC1) */ - TC4_IRQn = 21, /**< 21 SAML21G18B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21G18B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21G18B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21G18B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21G18B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21G18B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21G18B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnReserved19; - void* pfnReserved20; - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ -/** \defgroup SAML21G18B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21g18b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810114UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21G18B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21G18B_H */ +/** + * \file + * + * \brief Header file for SAML21G18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21G18B_ +#define _SAML21G18B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21G18B_definitions SAML21G18B definitions + * This file defines all structures and symbols for SAML21G18B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21G18B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21G18B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21G18B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21G18B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21G18B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21G18B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21G18B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21G18B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21G18B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21G18B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21G18B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21G18B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21G18B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21G18B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21G18B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21G18B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21G18B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21G18B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21G18B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21G18B Basic Timer Counter 1 (TC1) */ + TC4_IRQn = 21, /**< 21 SAML21G18B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21G18B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21G18B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21G18B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21G18B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21G18B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21G18B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pvReserved19; + void* pvReserved20; + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ +/** \defgroup SAML21G18B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21g18b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810214) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21G18B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21G18B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j16b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j16b.h index 6cce9948c3..6c9df93965 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j16b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j16b.h @@ -1,649 +1,636 @@ -/** - * \file - * - * \brief Header file for SAML21J16B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21J16B_ -#define _SAML21J16B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J16B_definitions SAML21J16B definitions - * This file defines all structures and symbols for SAML21J16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J16B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J16B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J16B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J16B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J16B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J16B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J16B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J16B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J16B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J16B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J16B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J16B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J16B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J16B Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J16B Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J16B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J16B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J16B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J16B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J16B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J16B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J16B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ -/** \defgroup SAML21J16B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x2000UL /* 8 kB */ -#define LPRAM_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810111UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J16B_H */ +/** + * \file + * + * \brief Header file for SAML21J16B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J16B_ +#define _SAML21J16B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J16B_definitions SAML21J16B definitions + * This file defines all structures and symbols for SAML21J16B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J16B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J16B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J16B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J16B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J16B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J16B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J16B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J16B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J16B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J16B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J16B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J16B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J16B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J16B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J16B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J16B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J16B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J16B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J16B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J16B Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J16B Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J16B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J16B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J16B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J16B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J16B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J16B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J16B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J16B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ +/** \defgroup SAML21J16B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j16b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define LPRAM_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810211) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J16B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J16B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17b.h index f5780e6bca..09cae16f86 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17b.h @@ -1,649 +1,636 @@ -/** - * \file - * - * \brief Header file for SAML21J17B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21J17B_ -#define _SAML21J17B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J17B_definitions SAML21J17B definitions - * This file defines all structures and symbols for SAML21J17B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J17B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J17B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J17B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J17B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J17B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J17B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J17B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J17B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J17B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J17B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J17B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J17B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J17B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J17B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J17B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J17B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J17B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J17B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J17B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J17B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J17B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J17B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J17B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J17B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J17B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J17B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J17B Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J17B Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J17B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J17B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J17B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J17B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J17B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J17B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J17B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J17B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ -/** \defgroup SAML21J17B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j17b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x4000UL /* 16 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10810110UL -#define NVMCTRL_RWW_EEPROM_SIZE 0x1000UL /* 4 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J17B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J17B_H */ +/** + * \file + * + * \brief Header file for SAML21J17B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J17B_ +#define _SAML21J17B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J17B_definitions SAML21J17B definitions + * This file defines all structures and symbols for SAML21J17B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J17B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J17B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J17B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J17B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J17B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J17B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J17B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J17B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J17B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J17B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J17B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J17B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J17B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J17B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J17B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J17B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J17B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J17B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J17B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J17B Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J17B Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J17B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J17B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J17B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J17B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J17B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J17B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J17B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J17B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ +/** \defgroup SAML21J17B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j17b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810210) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J17B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J17B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17bu.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17bu.h new file mode 100644 index 0000000000..f229df166b --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j17bu.h @@ -0,0 +1,636 @@ +/** + * \file + * + * \brief Header file for SAML21J17BU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J17BU_ +#define _SAML21J17BU_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J17BU_definitions SAML21J17BU definitions + * This file defines all structures and symbols for SAML21J17BU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J17BU-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J17BU System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J17BU Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J17BU Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J17BU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J17BU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J17BU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J17BU Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J17BU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J17BU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J17BU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J17BU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J17BU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J17BU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J17BU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J17BU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J17BU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J17BU Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J17BU Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J17BU Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J17BU Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J17BU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J17BU Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J17BU Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J17BU Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J17BU Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J17BU Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J17BU Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J17BU True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J17BU_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j17bu.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10810210) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J17BU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J17BU_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18b.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18b.h index 670abd4e1e..62707e9938 100644 --- a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18b.h +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18b.h @@ -1,649 +1,636 @@ -/** - * \file - * - * \brief Header file for SAML21J18B - * - * Copyright (c) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAML21J18B_ -#define _SAML21J18B_ - -/** - * \ingroup SAML21_definitions - * \addtogroup SAML21J18B_definitions SAML21J18B definitions - * This file defines all structures and symbols for SAML21J18B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAML21J18B-specific Interrupt Numbers ***********************/ - SYSTEM_IRQn = 0, /**< 0 SAML21J18B System Interrupts */ - MCLK_IRQn = 0, /**< 0 SAML21J18B Main Clock (MCLK) */ - OSCCTRL_IRQn = 0, /**< 0 SAML21J18B Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 0, /**< 0 SAML21J18B 32k Oscillators Control (OSC32KCTRL) */ - PAC_IRQn = 0, /**< 0 SAML21J18B Peripheral Access Controller (PAC) */ - PM_IRQn = 0, /**< 0 SAML21J18B Power Manager (PM) */ - SUPC_IRQn = 0, /**< 0 SAML21J18B Supply Controller (SUPC) */ - TAL_IRQn = 0, /**< 0 SAML21J18B Trigger Allocator (TAL) */ - WDT_IRQn = 1, /**< 1 SAML21J18B Watchdog Timer (WDT) */ - RTC_IRQn = 2, /**< 2 SAML21J18B Real-Time Counter (RTC) */ - EIC_IRQn = 3, /**< 3 SAML21J18B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 4, /**< 4 SAML21J18B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 5, /**< 5 SAML21J18B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 6, /**< 6 SAML21J18B Universal Serial Bus (USB) */ - EVSYS_IRQn = 7, /**< 7 SAML21J18B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 8, /**< 8 SAML21J18B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 9, /**< 9 SAML21J18B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 10, /**< 10 SAML21J18B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 11, /**< 11 SAML21J18B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 12, /**< 12 SAML21J18B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 13, /**< 13 SAML21J18B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 14, /**< 14 SAML21J18B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 15, /**< 15 SAML21J18B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 16, /**< 16 SAML21J18B Timer Counter Control 2 (TCC2) */ - TC0_IRQn = 17, /**< 17 SAML21J18B Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 18, /**< 18 SAML21J18B Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 19, /**< 19 SAML21J18B Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 20, /**< 20 SAML21J18B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 21, /**< 21 SAML21J18B Basic Timer Counter 4 (TC4) */ - ADC_IRQn = 22, /**< 22 SAML21J18B Analog Digital Converter (ADC) */ - AC_IRQn = 23, /**< 23 SAML21J18B Analog Comparators (AC) */ - DAC_IRQn = 24, /**< 24 SAML21J18B Digital-to-Analog Converter (DAC) */ - PTC_IRQn = 25, /**< 25 SAML21J18B Peripheral Touch Controller (PTC) */ - AES_IRQn = 26, /**< 26 SAML21J18B Advanced Encryption Standard (AES) */ - TRNG_IRQn = 27, /**< 27 SAML21J18B True Random Generator (TRNG) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnReservedM12; - void* pfnReservedM11; - void* pfnReservedM10; - void* pfnReservedM9; - void* pfnReservedM8; - void* pfnReservedM7; - void* pfnReservedM6; - void* pfnSVC_Handler; - void* pfnReservedM4; - void* pfnReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnSYSTEM_Handler; /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ - void* pfnWDT_Handler; /* 1 Watchdog Timer */ - void* pfnRTC_Handler; /* 2 Real-Time Counter */ - void* pfnEIC_Handler; /* 3 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 6 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 7 Event System Interface */ - void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ - void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ - void* pfnADC_Handler; /* 22 Analog Digital Converter */ - void* pfnAC_Handler; /* 23 Analog Comparators */ - void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ - void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ - void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 27 True Random Generator */ - void* pfnReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void SYSTEM_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_saml21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/mclk.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/opamp.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/mclk.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/opamp.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PM 0 /**< \brief Power Manager (PM) */ -#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ -#define ID_PORT 10 /**< \brief Port Module (PORT) */ -#define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ - -// Peripheral instances on HPB2 bridge -#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ -#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ - -// Peripheral instances on HPB3 bridge -#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 100 /**< \brief Analog Comparators (AC) */ -#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ -#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB4 bridge -#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x43001000UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define AES (0x42003400UL) /**< \brief (AES) APB Base Address */ -#define CCL (0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define DAC (0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define MCLK (0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define OPAMP (0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OSCCTRL (0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PM (0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RSTC (0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TCC0 (0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ -#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ -#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ -#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 33 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ -/** \defgroup SAML21J18B_port PORT Definitions */ -/*@{*/ - -#include "pio/saml21j18b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HSRAM_SIZE 0x8000UL /* 32 kB */ -#define LPRAM_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HSRAM_ADDR (0x20000000u) /**< HSRAM base address */ -#define LPRAM_ADDR (0x30000000u) /**< LPRAM base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define HPB3_ADDR (0x43000000u) /**< HPB3 base address */ -#define HPB4_ADDR (0x44000000u) /**< HPB4 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1081010FUL -#define NVMCTRL_RWW_EEPROM_SIZE 0x2000UL /* 8 kB */ -#define PORT_GROUPS 2 -#define USB_HOST_IMPLEMENTED 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAML21J18B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAML21J18B_H */ +/** + * \file + * + * \brief Header file for SAML21J18B + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J18B_ +#define _SAML21J18B_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J18B_definitions SAML21J18B definitions + * This file defines all structures and symbols for SAML21J18B: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J18B-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J18B System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J18B Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J18B Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J18B External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J18B Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J18B Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J18B Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J18B Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J18B Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J18B Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J18B Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J18B Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J18B Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J18B Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J18B Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J18B Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J18B Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J18B Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J18B Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J18B Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J18B Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J18B Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J18B Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J18B Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J18B Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J18B Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J18B Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J18B True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ +/** \defgroup SAML21J18B_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j18b.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081020F) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J18B */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J18B_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18bu.h b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18bu.h new file mode 100644 index 0000000000..aca398037c --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include_b/saml21j18bu.h @@ -0,0 +1,636 @@ +/** + * \file + * + * \brief Header file for SAML21J18BU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAML21J18BU_ +#define _SAML21J18BU_ + +/** + * \ingroup SAML21_definitions + * \addtogroup SAML21J18BU_definitions SAML21J18BU definitions + * This file defines all structures and symbols for SAML21J18BU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAML21J18BU-specific Interrupt Numbers *********************/ + SYSTEM_IRQn = 0, /**< 0 SAML21J18BU System Interrupts */ + WDT_IRQn = 1, /**< 1 SAML21J18BU Watchdog Timer (WDT) */ + RTC_IRQn = 2, /**< 2 SAML21J18BU Real-Time Counter (RTC) */ + EIC_IRQn = 3, /**< 3 SAML21J18BU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 4, /**< 4 SAML21J18BU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 5, /**< 5 SAML21J18BU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 6, /**< 6 SAML21J18BU Universal Serial Bus (USB) */ + EVSYS_IRQn = 7, /**< 7 SAML21J18BU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 8, /**< 8 SAML21J18BU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 9, /**< 9 SAML21J18BU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 10, /**< 10 SAML21J18BU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 11, /**< 11 SAML21J18BU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 12, /**< 12 SAML21J18BU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 13, /**< 13 SAML21J18BU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 14, /**< 14 SAML21J18BU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 15, /**< 15 SAML21J18BU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 16, /**< 16 SAML21J18BU Timer Counter Control 2 (TCC2) */ + TC0_IRQn = 17, /**< 17 SAML21J18BU Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 18, /**< 18 SAML21J18BU Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 19, /**< 19 SAML21J18BU Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 20, /**< 20 SAML21J18BU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 21, /**< 21 SAML21J18BU Basic Timer Counter 4 (TC4) */ + ADC_IRQn = 22, /**< 22 SAML21J18BU Analog Digital Converter (ADC) */ + AC_IRQn = 23, /**< 23 SAML21J18BU Analog Comparators (AC) */ + DAC_IRQn = 24, /**< 24 SAML21J18BU Digital-to-Analog Converter (DAC) */ + PTC_IRQn = 25, /**< 25 SAML21J18BU Peripheral Touch Controller (PTC) */ + AES_IRQn = 26, /**< 26 SAML21J18BU Advanced Encryption Standard (AES) */ + TRNG_IRQn = 27, /**< 27 SAML21J18BU True Random Generator (TRNG) */ + + PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ + void* pfnWDT_Handler; /* 1 Watchdog Timer */ + void* pfnRTC_Handler; /* 2 Real-Time Counter */ + void* pfnEIC_Handler; /* 3 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 6 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 7 Event System Interface */ + void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ + void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ + void* pfnADC_Handler; /* 22 Analog Digital Converter */ + void* pfnAC_Handler; /* 23 Analog Comparators */ + void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ + void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ + void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 27 True Random Generator */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void SYSTEM_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_saml21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/mclk.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/opamp.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/mclk.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/opamp.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PM 0 /**< \brief Power Manager (PM) */ +#define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ +#define ID_PORT 10 /**< \brief Port Module (PORT) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ + +// Peripheral instances on HPB2 bridge +#define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ +#define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ + +// Peripheral instances on HPB3 bridge +#define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 100 /**< \brief Analog Comparators (AC) */ +#define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ +#define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB4 bridge +#define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x43001000) /**< \brief (AC) APB Base Address */ +#define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ +#define AES (0x42003400) /**< \brief (AES) APB Base Address */ +#define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ +#define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ +#define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ +#define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ +#define PM (0x40000000) /**< \brief (PM) APB Base Address */ +#define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ +#define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ +#define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ +#define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ +#define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ +#define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 33 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ +/** \defgroup SAML21J18BU_port PORT Definitions */ +/*@{*/ + +#include "pio/saml21j18bu.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ +#define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1081020F) +#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ +#define PORT_GROUPS 2 +#define USB_HOST_IMPLEMENTED 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAML21J18BU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAML21J18BU_H */ diff --git a/cpu/sam0_common/include/vendor/saml21/include_b/system_saml21.h b/cpu/sam0_common/include/vendor/saml21/include_b/system_saml21.h new file mode 100644 index 0000000000..51a00d3db5 --- /dev/null +++ b/cpu/sam0_common/include/vendor/saml21/include_b/system_saml21.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAML21_H_INCLUDED_ +#define _SYSTEM_SAML21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAML21_H_INCLUDED */ diff --git a/cpu/saml21/periph/pm.c b/cpu/saml21/periph/pm.c index 7ad31c4289..af839e5bd9 100644 --- a/cpu/saml21/periph/pm.c +++ b/cpu/saml21/periph/pm.c @@ -41,7 +41,7 @@ void pm_set(unsigned mode) default: /* Falls through */ case 2: DEBUG_PUTS("pm_set(): setting IDLE mode."); -#if defined(CPU_MODEL_SAMR30G18A) || defined(CPU_MODEL_SAMR34J18B) +#if !defined(PM_SLEEPCFG_SLEEPMODE_IDLE2) _mode = PM_SLEEPCFG_SLEEPMODE_IDLE; #else _mode = PM_SLEEPCFG_SLEEPMODE_IDLE2;