From cc7acaaef056502aa484946d33da60edcd73b586 Mon Sep 17 00:00:00 2001 From: Joakim Gebart Date: Tue, 20 Jan 2015 09:06:16 +0100 Subject: [PATCH] periph/spi: Update clock polarity and phase documentation for clarity. Signed-off-by: Joakim Gebart --- drivers/include/periph/spi.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/include/periph/spi.h b/drivers/include/periph/spi.h index c9ae13bd18..2dc520f561 100644 --- a/drivers/include/periph/spi.h +++ b/drivers/include/periph/spi.h @@ -57,10 +57,30 @@ typedef enum { * clock phase. */ typedef enum { - SPI_CONF_FIRST_RISING = 0, /**< first data bit is transacted on the first rising SCK edge */ - SPI_CONF_SECOND_RISING, /**< first data bit is transacted on the second rising SCK edge */ - SPI_CONF_FIRST_FALLING, /**< first data bit is transacted on the first falling SCK edge */ - SPI_CONF_SECOND_FALLING /**< first data bit is transacted on the second falling SCK edge */ + /** + * The first data bit is sampled by the receiver on the first SCK edge. The + * first edge of SCK is rising. This is sometimes also referred to as SPI + * mode 0, or (CPOL=0, CPHA=0). + */ + SPI_CONF_FIRST_RISING = 0, + /** + * The first data bit is sampled by the receiver on the second SCK edge. The + * first edge of SCK is rising, i.e. the sampling edge is falling. This is + * sometimes also referred to as SPI mode 1, or (CPOL=0, CPHA=1). + */ + SPI_CONF_SECOND_RISING = 1, + /** + * The first data bit is sampled by the receiver on the first SCK edge. The + * first edge of SCK is falling. This is sometimes also referred to as SPI + * mode 2, or (CPOL=1, CPHA=0). + */ + SPI_CONF_FIRST_FALLING = 2, + /** + * The first data bit is sampled by the receiver on the second SCK edge. The + * first edge of SCK is falling, i.e. the sampling edge is rising. This is + * sometimes also referred to as SPI mode 3, or (CPOL=1, CPHA=1). + */ + SPI_CONF_SECOND_FALLING = 3 } spi_conf_t; /**