* changed to struct based register access for mc1322x
This commit is contained in:
Oliver Hahm
parent
9556ca3e7c
commit
ce294b4249
@ -21,24 +21,31 @@
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#define CO_INIT 0 /* other counters cannot force a re-initialization of this counter */
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#define OUT_MODE 0 /* OFLAG is asserted while counter is active */
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/* High level interrupt handler */
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static void (*int_handler)(int);
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) {
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int_handler = handler;
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/* Reset the timer */
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TMR_ENBL = 0;
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TMR0->ENBL = 0;
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/* Clear status */
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TMR0_SCTRL = 0;
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TMR0->SCTRL = 0;
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/* disable interrupt */
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TMR0_CSCTRL =0x0000;
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TMR0->CSCTRL =0x0000;
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/* Reload/initialize to zero */
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TMR0_LOAD = 0;
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TMR0->LOAD = 0;
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/* disable comparison */
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TMR0_COMP_UP = 0;
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TMR0_CMPLD1 = 0;
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TMR0->COMP1 = 0;
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TMR0->CMPLD1 = 0;
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/* set counter to zero */
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TMR0_CNTR = 0;
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TMR0->CNTR = 0;
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TMR0_CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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TMR_ENBL = 0xf; /* enable all the timers --- why not? */
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/* TODO: do scaling voodoo */
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(void) fcpu;
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/* TODO: use struct */
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TMR0->CTRL = (COUNT_MODE<<13) | (PRIME_SRC<<9) | (SEC_SRC<<7) | (ONCE<<6) | (LEN<<5) | (DIR<<4) | (CO_INIT<<3) | (OUT_MODE);
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TMR0->ENBL = 0xf; /* enable all the timers --- why not? */
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}
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@ -10,6 +10,7 @@
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#define CPU_H
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#include <stdint.h>
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#include "arm_cpu.h"
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#include "mc1322x.h"
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extern uintptr_t __stack_start; ///< end of user stack memory space
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@ -11,6 +11,198 @@
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#ifndef MC1322X_H
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#define MC1322X_H
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#include <stdint.h>
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/*-----------------------------------------------------------------*/
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/* System Management */
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#define SW_RST_VAL (0x87651234)
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#define CRM_BASE (0x80003000)
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/* Structure-based CRM access */
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struct CRM_struct {
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union {
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uint32_t SYS_CNTL;
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struct CRM_SYS_CNTL {
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uint32_t PWR_SOURCE:2;
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uint32_t PADS_1P8V_SEL:1;
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uint32_t :1;
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uint32_t JTAG_SECU_OFF:1;
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uint32_t XTAL32_EXISTS:1;
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uint32_t :2;
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uint32_t XTAL_CLKDIV:6;
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uint32_t :18;
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} SYS_CNTLbits;
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};
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union {
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uint32_t WU_CNTL;
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struct CRM_WU_CNTL {
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uint32_t TIMER_WU_EN:1;
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uint32_t RTC_WU_EN:1;
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uint32_t HOST_WAKE:1;
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uint32_t AUTO_ADC:1;
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uint32_t EXT_WU_EN:4;
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uint32_t EXT_WU_EDGE:4;
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uint32_t EXT_WU_POL:4;
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uint32_t TIMER_WU_IEN:1;
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uint32_t RTC_WU_IEN:1;
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uint32_t :2;
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uint32_t EXT_WU_IEN:4;
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uint32_t :4;
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uint32_t EXT_OUT_POL:4;
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} WU_CNTLbits;
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};
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union {
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uint32_t SLEEP_CNTL;
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struct CRM_SLEEP_CNTL {
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uint32_t HIB:1;
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uint32_t DOZE:1;
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uint32_t :2;
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uint32_t RAM_RET:2;
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uint32_t MCU_RET:1;
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uint32_t DIG_PAD_EN:1;
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uint32_t :24;
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} SLEEP_CNTLbits;
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};
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union {
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uint32_t BS_CNTL;
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struct CRM_BS_CNTL {
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uint32_t BS_EN:1;
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uint32_t WAIT4IRQ:1;
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uint32_t BS_MAN_EN:1;
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uint32_t :2;
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uint32_t ARM_OFF_TIME:6;
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uint32_t :18;
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} BS_CNTLbits;
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};
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union {
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uint32_t COP_CNTL;
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struct CRM_COP_CNTL {
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uint32_t COP_EN:1;
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uint32_t COP_OUT:1;
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uint32_t COP_WP:1;
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uint32_t :5;
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uint32_t COP_TIMEOUT:7;
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uint32_t :1;
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uint32_t COP_COUNT:7;
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uint32_t :9;
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} COP_CNTLbits;
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};
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uint32_t COP_SERVICE;
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union {
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uint32_t STATUS;
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struct CRM_STATUS {
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uint32_t SLEEP_SYNC:1;
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uint32_t HIB_WU_EVT:1;
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uint32_t DOZE_WU_EVT:1;
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uint32_t RTC_WU_EVT:1;
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uint32_t EXT_WU_EVT:4;
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uint32_t :1;
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uint32_t CAL_DONE:1;
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uint32_t COP_EVT:1;
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uint32_t :6;
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uint32_t VREG_BUCK_RDY:1;
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uint32_t VREG_1P8V_RDY:1;
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uint32_t VREG_1P5V_RDY:1;
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uint32_t :12;
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} STATUSbits;
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};
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union {
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uint32_t MOD_STATUS;
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struct CRM_MOD_STATUS {
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uint32_t ARM_EN:1;
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uint32_t MACA_EN:1;
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uint32_t ASM_EN:1;
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uint32_t SPI_EN:1;
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uint32_t GPIO_EN:1;
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uint32_t UART1_EN:1;
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uint32_t UART2_EN:1;
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uint32_t TMR_EN:1;
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uint32_t RIF_EN:1;
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uint32_t I2C_EN:1;
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uint32_t SSI_EN:1;
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uint32_t SPIF_EN:1;
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uint32_t ADC_EN:1;
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uint32_t :1;
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uint32_t JTA_EN:1;
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uint32_t NEX_EN:1;
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uint32_t :1;
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uint32_t AIM_EN:1;
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uint32_t :14;
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} MOD_STATUSbits;
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};
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uint32_t WU_COUNT;
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uint32_t WU_TIMEOUT;
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uint32_t RTC_COUNT;
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uint32_t RTC_TIMEOUT;
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uint32_t reserved1;
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union {
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uint32_t CAL_CNTL;
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struct CRM_CAL_CNTL {
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uint32_t CAL_TIMEOUT:16;
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uint32_t CAL_EN:1;
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uint32_t CAL_IEN:1;
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uint32_t :14;
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} CAL_CNTLbits;
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};
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uint32_t CAL_COUNT;
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union {
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uint32_t RINGOSC_CNTL;
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struct CRM_RINGOSC_CNTL {
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uint32_t ROSC_EN:1;
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uint32_t :3;
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uint32_t ROSC_FTUNE:5;
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uint32_t ROSC_CTUNE:4;
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uint32_t :19;
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} RINGOSC_CNTLbits;
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};
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union {
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uint32_t XTAL_CNTL;
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struct CRM_XTAL_CNTL {
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uint32_t :8;
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uint32_t XTAL_IBIAS_SEL:4;
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uint32_t :4;
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uint32_t XTAL_FTUNE:5;
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uint32_t XTAL_CTUNE:5;
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uint32_t :6;
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} XTAL_CNTLbits;
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};
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union {
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uint32_t XTAL32_CNTL;
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struct CRM_XTAL32_CNTL {
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uint32_t XTAL32_EN:1;
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uint32_t :3;
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uint32_t XTAL32_GAIN:2;
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uint32_t :26;
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} XTAL32_CNTLbits;
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};
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union {
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uint32_t VREG_CNTL;
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struct CRM_VREG_CNTL {
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uint32_t BUCK_EN:1;
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uint32_t BUCK_SYNC_REC_EN:1;
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uint32_t BUCK_BYPASS_EN:1;
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uint32_t VREG_1P5V_EN:2;
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uint32_t VREG_1P5V_SEL:2;
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uint32_t VREG_1P8V_EN:1;
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uint32_t BUCK_CLKDIV:4;
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uint32_t :20;
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} VREG_CNTLbits;
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};
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uint32_t reserved2;
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uint32_t SW_RST;
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uint32_t reserved3;
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uint32_t reserved4;
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uint32_t reserved5;
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uint32_t reserved6;
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};
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static volatile struct CRM_struct * const CRM = (void*) (CRM_BASE);
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/*-----------------------------------------------------------------*/
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/* TIMERS */
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#define F_CPU (24000000) ///< CPU target speed in Hz
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/* Timer registers are all 16-bit wide with 16-bit access only */
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@ -21,16 +213,6 @@
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#define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
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#define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
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/* Structure-based register definitions */
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/* Example use:
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TMR2->CTRL = 0x1234;
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TMR2->CTRLbits = (struct TMR_CTRL) {
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.DIR = 1,
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.OUTPUT_MODE = 2,
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};
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TMR2->CTRLbits.PRIMARY_CNT_SOURCE = 3;
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*/
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struct TMR_struct {
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uint16_t COMP1;
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uint16_t COMP2;
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@ -120,91 +302,85 @@ static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
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/* Get timer number from the timer pointer. */
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#define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
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/* Used to compute which enable bit to set for a particular timer, e.g.
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TMR0.ENBL |= TMR_ENABLE_BIT(TMR2);
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Helpful when you're using macros to define timers
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*/
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#define TMR_ENABLE_BIT(x) (1 << TMR_NUM(x))
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/*-----------------------------------------------------------------*/
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/* UART */
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#define UART1_BASE (0x80005000)
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#define UART2_BASE (0x8000B000)
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#define TMR0_PIN GPIO_08
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#define TMR1_PIN GPIO_09
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#define TMR2_PIN GPIO_10
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#define TMR3_PIN GPIO_11
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struct UART_struct {
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union {
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uint32_t CON;
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struct UART_CON {
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uint32_t :16;
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uint32_t TST:1;
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uint32_t MRXR:1;
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uint32_t MTXR:1;
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uint32_t FCE:1;
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uint32_t FCP:1;
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uint32_t XTIM:1;
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uint32_t :2;
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uint32_t TXOENB:1;
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uint32_t CONTX:1;
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uint32_t SB:1;
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uint32_t ST2:1;
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uint32_t EP:1;
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uint32_t PEN:1;
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uint32_t RXE:1;
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uint32_t TXE:1;
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} CONbits;
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};
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union {
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uint32_t STAT;
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struct UART_STAT {
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uint32_t :24;
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uint32_t TXRDY:1;
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uint32_t RXRDY:1;
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uint32_t RUE:1;
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uint32_t ROE:1;
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uint32_t TOE:1;
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uint32_t FE:1;
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uint32_t PE:1;
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uint32_t SE:1;
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} USTATbits;
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};
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union {
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uint32_t DATA;
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struct UART_DATA {
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uint32_t :24;
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uint32_t DATA:8;
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} DATAbits;
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};
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union {
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uint32_t RXCON;
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struct UART_URXCON {
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uint32_t :26;
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uint32_t LVL:6;
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} RXCONbits;
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};
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union {
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uint32_t TXCON;
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struct UART_TXCON {
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uint32_t :26;
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uint32_t LVL:6;
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} TXCONbits;
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};
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union {
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uint32_t CTS;
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struct UART_CTS {
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uint32_t :27;
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uint32_t LVL:5;
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} CTSbits;
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};
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union {
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uint32_t BR;
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struct UART_BR {
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uint32_t INC:16;
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uint32_t MOD:16;
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} BRbits;
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};
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};
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#define TMR_REGOFF_COMP1 (0x0)
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#define TMR_REGOFF_COMP2 (0x2)
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#define TMR_REGOFF_CAPT (0x4)
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#define TMR_REGOFF_LOAD (0x6)
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#define TMR_REGOFF_HOLD (0x8)
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#define TMR_REGOFF_CNTR (0xa)
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#define TMR_REGOFF_CTRL (0xc)
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#define TMR_REGOFF_SCTRL (0xe)
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#define TMR_REGOFF_CMPLD1 (0x10)
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#define TMR_REGOFF_CMPLD2 (0x12)
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#define TMR_REGOFF_CSCTRL (0x14)
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#define TMR_REGOFF_ENBL (0x1e)
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static volatile struct UART_struct * const UART1 = (void *) (UART1_BASE);
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static volatile struct UART_struct * const UART2 = (void *) (UART2_BASE);
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/* one enable register to rule them all */
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#define TMR_ENBL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_ENBL))
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/* Timer 0 registers */
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#define TMR0_COMP1 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
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#define TMR0_COMP_UP TMR0_COMP1
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#define TMR0_COMP2 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP2))
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#define TMR0_COMP_DOWN TMR0_COMP2
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#define TMR0_CAPT (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
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#define TMR0_LOAD (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
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#define TMR0_HOLD (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
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#define TMR0_CNTR (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CNTR))
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#define TMR0_CTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
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#define TMR0_SCTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
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#define TMR0_CMPLD1 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
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#define TMR0_CMPLD2 (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
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#define TMR0_CSCTRL (*(volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 1 registers */
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#define TMR1_COMP1 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
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#define TMR1_COMP_UP TMR1_COMP1
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#define TMR1_COMP2 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
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#define TMR1_COMP_DOWN TMR1_COMP2
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#define TMR1_CAPT (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
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#define TMR1_LOAD (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
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#define TMR1_HOLD (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
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#define TMR1_CNTR (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CNTR))
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#define TMR1_CTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
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#define TMR1_SCTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
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#define TMR1_CMPLD1 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
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#define TMR1_CMPLD2 (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
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#define TMR1_CSCTRL (*(volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 2 registers */
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#define TMR2_COMP1 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
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#define TMR2_COMP_UP TMR2_COMP1
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#define TMR2_COMP2 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
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#define TMR2_COMP_DOWN TMR2_COMP2
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#define TMR2_CAPT (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
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#define TMR2_LOAD (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
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#define TMR2_HOLD (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
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#define TMR2_CNTR (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CNTR))
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#define TMR2_CTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
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#define TMR2_SCTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
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#define TMR2_CMPLD1 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
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#define TMR2_CMPLD2 (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
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#define TMR2_CSCTRL (*(volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
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/* Timer 3 registers */
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#define TMR3_COMP1 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
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#define TMR3_COMP_UP TMR3_COMP1
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#define TMR3_COMP2 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
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#define TMR3_COMP_DOWN TMR3_COMP2
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#define TMR3_CAPT (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
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#define TMR3_LOAD (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
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#define TMR3_HOLD (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
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#define TMR3_CNTR (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CNTR))
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#define TMR3_CTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
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#define TMR3_SCTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
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#define TMR3_CMPLD1 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
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#define TMR3_CMPLD2 (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
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#define TMR3_CSCTRL (*(volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
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#define TMR(num, reg) CAT2(TMR,num,_##reg)
|
||||
#endif /* MC1322X_H */
|
||||
|
||||
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Reference in New Issue
Block a user