cpu/cortexm_common: define ISR stacksize in cpu.h

cpu/cortexm_common/include/cpu.h

@@ -64,6 +64,15 @@ extern "C" {
 #endif
 /** @} */
 
+/**
+ * @brief   Stack size used for the exception (ISR) stack
+ * @{
+ */
+#ifndef ISR_STACKSIZE
+#define ISR_STACKSIZE                   (512U)
+#endif
+/** @} */
+
 /**
  * @brief   Some members of the Cortex-M family have architecture specific
  *          atomic operations in atomic_arch.c

cpu/cortexm_common/ldscripts/cortexm_base.ld

@@ -31,11 +31,6 @@ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 SEARCH_DIR(.)
 
-/* Define the default stack size for interrupt mode. As no context is
-   saved on this stack and ISRs are supposed to be short, it can be fairly
-   small. 512 byte should be a save assumption here */
-STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200; /* 512 byte */
-
 /* Section Definitions */
 SECTIONS
 {
@@ -134,7 +129,7 @@ SECTIONS
     {
         . = ALIGN(8);
         _sstack = .;
-        . = . + STACK_SIZE;
+        KEEP (*(.isr_stack))
         . = ALIGN(8);
         _estack = .;
     } > ram

cpu/cortexm_common/vectors_cortexm.c

@@ -55,6 +55,11 @@ extern uint32_t _eram;
  */
 #define STACK_CANARY_WORD 0xE7FEE7FEu
 
+/**
+ * @brief   Allocation of the interrupt stack
+ */
+__attribute__((used,section(".isr_stack"))) uint8_t isr_stack[ISR_STACKSIZE];
+
 /**
  * @brief   Pre-start routine for CPU-specific settings
  */