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boards/nucleo-f767zi: Use shared clock settings

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Use boards/common/stm32/include/f7/cfg_clock_216_8_1.h for core clock settings
This commit is contained in:
Marian Buschsieweke 2019-03-25 13:05:17 +01:00
parent 17fd6941ce
commit d00becbc4b
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GPG Key ID: 61F64C6599B1539F
1 changed files with 1 additions and 31 deletions
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32
boards/nucleo-f767zi/include/periph_conf.h
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@ -22,43 +22,13 @@
#define PERIPH_CONF_H #define PERIPH_CONF_H
#include "periph_cpu.h" #include "periph_cpu.h"
#include "f7/cfg_clock_216_8_1.h"
#include "cfg_i2c1_pb8_pb9.h" #include "cfg_i2c1_pb8_pb9.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz */
#define CLOCK_CORECLOCK (216000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (216)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (9)
/** @} */
/** /**
* @name DMA streams configuration * @name DMA streams configuration
* @{ * @{