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Merge pull request #2993 from gebart/pr/kinetis-bitband-reg

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kinetis: remove ambiguous BITBAND_REG macro
This commit is contained in:
Oleg Hahm 2015-05-21 19:18:33 +02:00
commit d0790ad034
6 changed files with 114 additions and 97 deletions
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18
boards/mulle/include/board.h
View File

@ -74,15 +74,15 @@
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED_RED_ON (BITBAND_REG(LED_RED_PORT->PSOR, LED_RED_PIN) = 1)
#define LED_RED_OFF (BITBAND_REG(LED_RED_PORT->PCOR, LED_RED_PIN) = 1)
#define LED_RED_TOGGLE (BITBAND_REG(LED_RED_PORT->PTOR, LED_RED_PIN) = 1)
#define LED_YELLOW_ON (BITBAND_REG(LED_YELLOW_PORT->PSOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_OFF (BITBAND_REG(LED_YELLOW_PORT->PCOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_TOGGLE (BITBAND_REG(LED_YELLOW_PORT->PTOR, LED_YELLOW_PIN) = 1)
#define LED_GREEN_ON (BITBAND_REG(LED_GREEN_PORT->PSOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_OFF (BITBAND_REG(LED_GREEN_PORT->PCOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_TOGGLE (BITBAND_REG(LED_GREEN_PORT->PTOR, LED_GREEN_PIN) = 1)
#define LED_RED_ON (BITBAND_REG32(LED_RED_PORT->PSOR, LED_RED_PIN) = 1)
#define LED_RED_OFF (BITBAND_REG32(LED_RED_PORT->PCOR, LED_RED_PIN) = 1)
#define LED_RED_TOGGLE (BITBAND_REG32(LED_RED_PORT->PTOR, LED_RED_PIN) = 1)
#define LED_YELLOW_ON (BITBAND_REG32(LED_YELLOW_PORT->PSOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_OFF (BITBAND_REG32(LED_YELLOW_PORT->PCOR, LED_YELLOW_PIN) = 1)
#define LED_YELLOW_TOGGLE (BITBAND_REG32(LED_YELLOW_PORT->PTOR, LED_YELLOW_PIN) = 1)
#define LED_GREEN_ON (BITBAND_REG32(LED_GREEN_PORT->PSOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_OFF (BITBAND_REG32(LED_GREEN_PORT->PCOR, LED_GREEN_PIN) = 1)
#define LED_GREEN_TOGGLE (BITBAND_REG32(LED_GREEN_PORT->PTOR, LED_GREEN_PIN) = 1)
/** @} */
#ifdef __cplusplus

124
boards/mulle/include/periph_conf.h
View File

@ -67,7 +67,7 @@ extern "C"
#define TIMER_DEV PIT
#define TIMER_MAX_VALUE (0xffffffff)
#define TIMER_CLOCK SystemBusClock
#define TIMER_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT) = 1)
#define TIMER_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT) = 1)
/* Timer 0 configuration */
#define TIMER_0_PRESCALER_CH 0
@ -98,13 +98,13 @@ extern "C"
/* UART 0 device configuration */
#define UART_0_DEV UART1
#define UART_0_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
#define UART_0_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
#define UART_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
#define UART_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
#define UART_0_CLK (SystemSysClock)
#define UART_0_IRQ_CHAN UART1_RX_TX_IRQn
#define UART_0_ISR isr_uart1_status
/* UART 0 pin configuration */
#define UART_0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define UART_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define UART_0_PORT PORTC
#define UART_0_TX_PIN 4
#define UART_0_RX_PIN 3
@ -116,13 +116,13 @@ extern "C"
/* UART 1 device configuration */
#define UART_1_DEV UART0
#define UART_1_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
#define UART_1_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
#define UART_1_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
#define UART_1_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
#define UART_1_CLK (SystemSysClock)
#define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
#define UART_1_ISR isr_uart0_status
/* UART 1 pin configuration */
#define UART_1_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
#define UART_1_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
#define UART_1_PORT PORTA
#define UART_1_TX_PIN 14
#define UART_1_RX_PIN 15
@ -147,8 +147,8 @@ extern "C"
/* ADC 0 configuration */
#define ADC_0_DEV ADC0
#define ADC_0_CHANNELS 4
#define ADC_0_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 1)
#define ADC_0_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 0)
#define ADC_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 1)
#define ADC_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 0)
#define ADC_0_PORT_CLKEN() /* no PORT pins configured */
#define ADC_0_MODULE_CLOCK SystemBusClock
/* ADC 0 channel 0 pin config */
@ -185,8 +185,8 @@ extern "C"
/* ADC 1 configuration */
#define ADC_1_DEV ADC1
#define ADC_1_CHANNELS 2
#define ADC_1_CLKEN() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 1)
#define ADC_1_CLKDIS() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 0)
#define ADC_1_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 1)
#define ADC_1_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 0)
#define ADC_1_PORT_CLKEN() /* no PORT pins configured */
#define ADC_1_MODULE_CLOCK SystemBusClock
/* ADC 1 channel 0 pin config */
@ -256,8 +256,8 @@ extern "C"
#define SPI_0_INDEX 0
#define SPI_0_CTAS 0
#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
#define SPI_0_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
#define SPI_0_IRQ_PRIO 1
@ -265,19 +265,19 @@ extern "C"
/* SPI 0 pin configuration */
#define SPI_0_SCK_PORT PORTD
#define SPI_0_SCK_PIN 1
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SCK_AF 2
#define SPI_0_SIN_PORT PORTD
#define SPI_0_SIN_PIN 3
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SIN_AF 2
#define SPI_0_SOUT_PORT PORTD
#define SPI_0_SOUT_PIN 2
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_SOUT_AF 2
#define SPI_0_PCS0_PORT PORTD
#define SPI_0_PCS0_PIN 0
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_0_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_0_PCS0_ACTIVE_LOW 1
@ -290,8 +290,8 @@ extern "C"
#define SPI_1_INDEX 1
#define SPI_1_CTAS 0
#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
#define SPI_1_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
#define SPI_1_IRQ_PRIO 1
@ -299,19 +299,19 @@ extern "C"
/* SPI 0 pin configuration */
#define SPI_1_SCK_PORT PORTE
#define SPI_1_SCK_PIN 2
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SCK_AF 2
#define SPI_1_SIN_PORT PORTE
#define SPI_1_SIN_PIN 3
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SIN_AF 2
#define SPI_1_SOUT_PORT PORTE
#define SPI_1_SOUT_PIN 1
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_SOUT_AF 2
#define SPI_1_PCS0_PORT PORTE
#define SPI_1_PCS0_PIN 4
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define SPI_1_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_1_PCS0_ACTIVE_LOW 1
@ -324,8 +324,8 @@ extern "C"
#define SPI_2_INDEX 0
#define SPI_2_CTAS 1
#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
#define SPI_2_CLKEN() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
#define SPI_2_IRQ_PRIO 1
@ -334,19 +334,19 @@ extern "C"
* hardware module */
#define SPI_2_SCK_PORT PORTD
#define SPI_2_SCK_PIN 1
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SCK_AF 2
#define SPI_2_SIN_PORT PORTD
#define SPI_2_SIN_PIN 3
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SIN_AF 2
#define SPI_2_SOUT_PORT PORTD
#define SPI_2_SOUT_PIN 2
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_SOUT_AF 2
#define SPI_2_PCS0_PORT PORTD
#define SPI_2_PCS0_PIN 0
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define SPI_2_PCS0_AF 2
/* SPI chip select polarity */
#define SPI_2_PCS0_ACTIVE_LOW 1
@ -409,13 +409,13 @@ extern "C"
/* I2C 0 device configuration */
#define I2C_0_DEV I2C0
#define I2C_0_CLKEN() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
#define I2C_0_CLKDIS() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
#define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
#define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
#define I2C_0_IRQ I2C0_IRQn
#define I2C_0_IRQ_HANDLER isr_i2c0
/* I2C 0 pin configuration */
#define I2C_0_PORT PORTB
#define I2C_0_PORT_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define I2C_0_PIN_AF 2
#define I2C_0_SDA_PIN 1
#define I2C_0_SCL_PIN 2
@ -463,7 +463,7 @@ extern "C"
#define GPIO_0_PORT_BASE PORTC_BASE
#define GPIO_0_DEV PTC
#define GPIO_0_PIN 15
#define GPIO_0_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_0_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_0_IRQ PORTC_IRQn
#define GPIO_0_ISR isr_portc_pin_detect
@ -473,7 +473,7 @@ extern "C"
#define GPIO_1_PORT_BASE PORTC_BASE
#define GPIO_1_DEV PTC
#define GPIO_1_PIN 14
#define GPIO_1_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_1_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_1_IRQ PORTC_IRQn
#define GPIO_1_ISR isr_portc_pin_detect
@ -483,7 +483,7 @@ extern "C"
#define GPIO_2_PORT_BASE PORTC_BASE
#define GPIO_2_DEV PTC
#define GPIO_2_PIN 13
#define GPIO_2_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_2_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_2_IRQ PORTC_IRQn
#define GPIO_2_ISR isr_portc_pin_detect
@ -493,7 +493,7 @@ extern "C"
#define GPIO_3_PORT_BASE PORTC_BASE
#define GPIO_3_DEV PTC
#define GPIO_3_PIN 18
#define GPIO_3_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_3_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_3_IRQ PORTC_IRQn
#define GPIO_3_ISR isr_portc_pin_detect
@ -503,7 +503,7 @@ extern "C"
#define GPIO_4_PORT_BASE PORTC_BASE
#define GPIO_4_DEV PTC
#define GPIO_4_PIN 17
#define GPIO_4_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_4_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_4_IRQ PORTC_IRQn
#define GPIO_4_ISR isr_portc_pin_detect
@ -513,7 +513,7 @@ extern "C"
#define GPIO_5_PORT_BASE PORTB_BASE
#define GPIO_5_DEV PTB
#define GPIO_5_PIN 16
#define GPIO_5_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_5_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_5_IRQ PORTB_IRQn
#define GPIO_5_ISR isr_portb_pin_detect
@ -523,7 +523,7 @@ extern "C"
#define GPIO_6_PORT_BASE PORTB_BASE
#define GPIO_6_DEV PTB
#define GPIO_6_PIN 17
#define GPIO_6_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_6_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_6_IRQ PORTB_IRQn
#define GPIO_6_ISR isr_portb_pin_detect
@ -533,7 +533,7 @@ extern "C"
#define GPIO_7_PORT_BASE PORTD_BASE
#define GPIO_7_DEV PTD
#define GPIO_7_PIN 7
#define GPIO_7_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_7_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_7_IRQ PORTD_IRQn
#define GPIO_7_ISR isr_portd_pin_detect
@ -543,7 +543,7 @@ extern "C"
#define GPIO_8_PORT_BASE PORTB_BASE
#define GPIO_8_DEV PTB
#define GPIO_8_PIN 23
#define GPIO_8_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_8_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_8_IRQ PORTB_IRQn
#define GPIO_8_ISR isr_portb_pin_detect
@ -553,7 +553,7 @@ extern "C"
#define GPIO_9_PORT_BASE PORTB_BASE
#define GPIO_9_DEV PTB
#define GPIO_9_PIN 22
#define GPIO_9_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_9_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_9_IRQ PORTB_IRQn
#define GPIO_9_ISR isr_portb_pin_detect
@ -563,7 +563,7 @@ extern "C"
#define GPIO_10_PORT_BASE PORTB_BASE
#define GPIO_10_DEV PTB
#define GPIO_10_PIN 21
#define GPIO_10_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_10_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_10_IRQ PORTB_IRQn
#define GPIO_10_ISR isr_portb_pin_detect
@ -573,7 +573,7 @@ extern "C"
#define GPIO_11_PORT_BASE PORTB_BASE
#define GPIO_11_DEV PTB
#define GPIO_11_PIN 20
#define GPIO_11_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_11_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_11_IRQ PORTB_IRQn
#define GPIO_11_ISR isr_portb_pin_detect
@ -583,7 +583,7 @@ extern "C"
#define GPIO_12_PORT_BASE PORTB_BASE
#define GPIO_12_DEV PTB
#define GPIO_12_PIN 9
#define GPIO_12_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_12_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_12_IRQ PORTB_IRQn
#define GPIO_12_ISR isr_portb_pin_detect
@ -593,7 +593,7 @@ extern "C"
#define GPIO_13_PORT_BASE PORTE_BASE
#define GPIO_13_DEV PTE
#define GPIO_13_PIN 6
#define GPIO_13_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_13_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_13_IRQ PORTE_IRQn
#define GPIO_13_ISR isr_porte_pin_detect
@ -603,7 +603,7 @@ extern "C"
#define GPIO_14_PORT_BASE PORTD_BASE
#define GPIO_14_DEV PTD
#define GPIO_14_PIN 4
#define GPIO_14_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_14_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_14_IRQ PORTD_IRQn
#define GPIO_14_ISR isr_portd_pin_detect
@ -613,7 +613,7 @@ extern "C"
#define GPIO_15_PORT_BASE PORTD_BASE
#define GPIO_15_DEV PTD
#define GPIO_15_PIN 0
#define GPIO_15_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_15_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_15_IRQ PORTD_IRQn
#define GPIO_15_ISR isr_portd_pin_detect
@ -623,7 +623,7 @@ extern "C"
#define GPIO_16_PORT_BASE PORTD_BASE
#define GPIO_16_DEV PTD
#define GPIO_16_PIN 6
#define GPIO_16_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_16_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_16_IRQ PORTD_IRQn
#define GPIO_16_ISR isr_portd_pin_detect
@ -633,7 +633,7 @@ extern "C"
#define GPIO_17_PORT_BASE PORTD_BASE
#define GPIO_17_DEV PTD
#define GPIO_17_PIN 5
#define GPIO_17_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_17_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
#define GPIO_17_IRQ PORTD_IRQn
#define GPIO_17_ISR isr_portd_pin_detect
@ -643,7 +643,7 @@ extern "C"
#define GPIO_18_PORT_BASE PORTB_BASE
#define GPIO_18_DEV PTB
#define GPIO_18_PIN 18
#define GPIO_18_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_18_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_18_IRQ PORTB_IRQn
#define GPIO_18_ISR isr_portb_pin_detect
@ -653,7 +653,7 @@ extern "C"
#define GPIO_19_PORT_BASE PORTB_BASE
#define GPIO_19_DEV PTB
#define GPIO_19_PIN 19
#define GPIO_19_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_19_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
#define GPIO_19_IRQ PORTB_IRQn
#define GPIO_19_ISR isr_portb_pin_detect
@ -663,7 +663,7 @@ extern "C"
#define GPIO_20_PORT_BASE PORTC_BASE
#define GPIO_20_DEV PTC
#define GPIO_20_PIN 0
#define GPIO_20_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_20_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_20_IRQ PORTC_IRQn
#define GPIO_20_ISR isr_portc_pin_detect
@ -673,7 +673,7 @@ extern "C"
#define GPIO_21_PORT_BASE PORTC_BASE
#define GPIO_21_DEV PTC
#define GPIO_21_PIN 1
#define GPIO_21_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_21_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_21_IRQ PORTC_IRQn
#define GPIO_21_ISR isr_portc_pin_detect
@ -683,7 +683,7 @@ extern "C"
#define GPIO_22_PORT_BASE PORTC_BASE
#define GPIO_22_DEV PTC
#define GPIO_22_PIN 2
#define GPIO_22_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_22_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_22_IRQ PORTC_IRQn
#define GPIO_22_ISR isr_portc_pin_detect
@ -693,7 +693,7 @@ extern "C"
#define GPIO_23_PORT_BASE PORTC_BASE
#define GPIO_23_DEV PTC
#define GPIO_23_PIN 5
#define GPIO_23_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_23_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_23_IRQ PORTC_IRQn
#define GPIO_23_ISR isr_portc_pin_detect
@ -703,7 +703,7 @@ extern "C"
#define GPIO_24_PORT_BASE PORTC_BASE
#define GPIO_24_DEV PTC
#define GPIO_24_PIN 6
#define GPIO_24_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_24_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_24_IRQ PORTC_IRQn
#define GPIO_24_ISR isr_portc_pin_detect
@ -713,7 +713,7 @@ extern "C"
#define GPIO_25_PORT_BASE PORTC_BASE
#define GPIO_25_DEV PTC
#define GPIO_25_PIN 7
#define GPIO_25_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_25_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
#define GPIO_25_IRQ PORTC_IRQn
#define GPIO_25_ISR isr_portc_pin_detect
@ -723,7 +723,7 @@ extern "C"
#define GPIO_26_PORT_BASE PORTE_BASE
#define GPIO_26_DEV PTE
#define GPIO_26_PIN 4
#define GPIO_26_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_26_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
#define GPIO_26_IRQ PORTE_IRQn
#define GPIO_26_ISR isr_porte_pin_detect
/** @} */
@ -746,7 +746,7 @@ extern "C"
#define RTT_IRQ RTC_IRQn
#define RTT_ISR isr_rtc_alarm
#define RTT_DEV RTC
#define RTT_UNLOCK() (BITBAND_REG(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
#define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (1) /* in Hz */
@ -763,8 +763,8 @@ extern "C"
* @{
*/
#define RANDOM_NUMOF (1U)
#define RANDOM_CLKEN() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
#define RANDOM_CLKDIS() (BITBAND_REG(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
#define RANDOM_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
#define RANDOM_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
/** @} */
#ifdef __cplusplus

7
cpu/k60/include/MK60D10.h
View File

@ -68,14 +68,16 @@
** Update of startup files - possibility to override DefaultISR added.
** - rev. 1.8 (2014-10-14)
** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0
** - rev. 1.8-jg (2015-05-18)
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
/*!
* @file MK60D10.h
* @version 1.8
* @date 2014-10-14
* @version 1.8-jg
* @date 2015-05-18
* @brief CMSIS Peripheral Access Layer for MK60D10
*
* CMSIS Peripheral Access Layer for MK60D10
@ -127,7 +129,6 @@ extern "C"
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can

39
cpu/k60/include/MK60DZ10.h
View File

@ -44,14 +44,17 @@
** - rev. 1.2 (2011-09-08)
** Cortex_Core_Configuration extended with additional parameters.
** Gap between end of interrupt vector table and flash configuration field filled by default ISR.
** - rev. 1.2-jg (2015-05-18)
** Added BITBAND_REG32, BITBAND_REG16, BITBAND_REG8, BITBAND_REGADDR macros from MK60D10.h.
** Removed BITBAND_REG macro.
**
** ###################################################################
*/
/**
* @file MK60DZ10.h
* @version 1.2
* @date 2011-09-08
* @version 1.2-jg
* @date 2015-05-18
* @brief CMSIS Peripheral Access Layer for MK60DZ10
*
* CMSIS Peripheral Access Layer for MK60DZ10
@ -68,14 +71,42 @@ extern "C"
/** Memory map version 1.2 */
#define MCU_MEM_MAP_VERSION 0x0102u
/**
* @brief Macro to calculate address of an aliased word in the peripheral
* bitband area for a peripheral register and bit (bit band region 0x40000000 to
* 0x400FFFFF).
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Address of the aliased word in the peripheral bitband area.
*/
#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 32bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 16bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/**
* @brief Macro to access a single bit of a peripheral register (bit band region
* 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
* be used for peripherals with 8bit access allowed.
* @param Reg Register to access.
* @param Bit Bit number to access.
* @return Value of the targeted bit in the bit band region.
*/
#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers

21
cpu/k60/include/cpu-conf.h
View File

@ -121,8 +121,8 @@ extern "C"
* @{
*/
#define LPTIMER_DEV (LPTMR0) /**< LPTIMER hardware module */
#define LPTIMER_CLKEN() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1) /**< Enable LPTMR0 clock gate */
#define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0) /**< Disable LPTMR0 clock gate */
#define LPTIMER_CLKSRC_MCGIRCLK 0 /**< internal reference clock (4MHz) */
#define LPTIMER_CLKSRC_LPO 1 /**< PMC 1kHz output */
#define LPTIMER_CLKSRC_ERCLK32K 2 /**< RTC clock 32768Hz */
@ -213,7 +213,7 @@ extern "C"
/**
* @brief Enable clock gate on LLWU module.
*/
#define LLWU_UNLOCK() (BITBAND_REG(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
#define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
/**
* @brief Internal modules whose interrupts are mapped to LLWU wake up sources.
@ -309,21 +309,6 @@ typedef enum llwu_wakeup_pin {
*/
#define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
/**
* @brief Bitband 32 bit access to peripheral register
*/
#define BITBAND_PERIPH32(reg, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 16 bit access to peripheral register
*/
#define BITBAND_PERIPH16(reg, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/**
* @brief Bitband 8 bit access to peripheral register
*/
#define BITBAND_PERIPH8(reg, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(reg), (bit))))
/** @} */
#ifdef __cplusplus
}

2
cpu/kinetis_common/random_rngb.c
View File

@ -67,7 +67,7 @@ void random_poweron(void)
}
/* Software reset, bit is self-clearing */
BITBAND_REG(KINETIS_RNGB->CMD, RNG_CMD_SR_SHIFT) = 1;
BITBAND_REG32(KINETIS_RNGB->CMD, RNG_CMD_SR_SHIFT) = 1;
/* Set up automatic reseed */
KINETIS_RNGB->CR = RNG_CR_AR_MASK | RNG_CR_MASKERR_MASK | RNG_CR_MASKDONE_MASK;
}