diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h index 395c851745..95e29f2e11 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg990f1024.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32GG990F1024 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -144,42 +144,42 @@ typedef enum IRQn{ #define PART_NUMBER "EFM32GG990F1024" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ -#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ -#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ -#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ -#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ -#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */ -#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */ -#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */ -#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */ -#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */ -#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */ -#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */ -#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */ -#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ -#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */ -#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */ -#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */ +#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ +#define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ +#define AES_MEM_SIZE (0x400UL) /**< AES available address space */ +#define AES_MEM_END (0x400E03FFUL) /**< AES end address */ +#define AES_MEM_BITS (0x10UL) /**< AES used bits */ +#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ +#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ +#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ +#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ +#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x20UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFM32GG990F1024 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h index ffe1f96f13..f2cf7ad0c5 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h index 6a101b31c1..aa442c2199 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h index 6534b8910f..0ca7e8b557 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_aes.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_AES register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h index 7b9959b24d..caaa5ed13e 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h index dfee221b51..9357f03cf8 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h index 9c099f86f6..00babb40d3 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_BURTC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h index d9103419d2..e8ee898b6f 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_burtc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_BURTC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h index 05d25e50cd..760c93bf47 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_calibrate.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_CALIBRATE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h index dff7bdd631..a4644151af 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h index 625551d181..4230b74094 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h index ddabf6af4d..9e0b713d9a 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h index 8859cdcbe3..baee81ed09 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h index d7a760c2ae..02ed0916a3 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h index 7a22d3eb73..e8a74b8f19 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h index 2b637c493d..f9252bcb83 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmactrl.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DMACTRL register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h index 4948f7b39a..840b21fd32 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h index 5e0db1ddc2..e4fbb93de7 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_ebi.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_EBI register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h index 8acb8a6f3f..d666bbca6e 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h index 42d6bf4ad1..ba88876680 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_etm.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_ETM register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h index 7fc414683c..5de4413545 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h index ca7e92fd2a..6af475d3ad 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h index 0c21359c3a..94916cf8fa 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h index 8277489a58..7bf18bf28c 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lcd.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LCD register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h index 1712fcef89..68a0fc2756 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LESENSE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h index 5856277f47..239ecf175e 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_buf.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LESENSE_BUF register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h index ae9a813f7a..7c84f83596 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LESENSE_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h index 662a9f94da..abeac3eba1 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_lesense_st.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LESENSE_ST register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h index d0dd8196a0..263840b46f 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h index 65d2020621..2c72fcb542 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h index ef21149d40..2251bef218 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h index f79b4a807a..4cc4e39a04 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h index 22e76f8845..6dc440847b 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h index 789a789502..ffe86f282e 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h index 27635a6f6f..8172b2afdf 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h index da2a253be8..6df3af9a53 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h index 6c3d5e39d0..6ae4ae9ff0 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h index 061c7a0285..3db7271815 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_rtc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_RTC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h index 1011cb7e33..0bbe102d4c 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h index 15fd065094..f2470f63f9 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h index 22acac2813..4322ec2ee6 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_uart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_UART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h index fed42b7157..3d6f2cea80 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h index 3479921c1d..aab1cd709d 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_USB register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h index 4dd3d6b284..ec6796cf0a 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_diep.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_USB_DIEP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h index 0912196b59..76093b6d7c 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_doep.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_USB_DOEP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h index dcd25031e7..43d1aad99e 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_usb_hc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_USB_HC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h index d59f339a3f..8b7a4d0bad 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_vcmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_VCMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h index 6b0f9f5111..9afbe560a2 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h +++ b/cpu/efm32/families/efm32gg/include/vendor/efm32gg_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32GG_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/em_device.h b/cpu/efm32/families/efm32gg/include/vendor/em_device.h index 33e5ab07c6..c8d1d02469 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/em_device.h +++ b/cpu/efm32/families/efm32gg/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h b/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h index 52e86b9293..62f608dfd1 100644 --- a/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h +++ b/cpu/efm32/families/efm32gg/include/vendor/system_efm32gg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32gg/system.c b/cpu/efm32/families/efm32gg/system.c index b9de495509..f90288911d 100644 --- a/cpu/efm32/families/efm32gg/system.c +++ b/cpu/efm32/families/efm32gg/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h index c79b67b9e1..b39ab20074 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg990f256.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32LG990F256 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -145,42 +145,42 @@ typedef enum IRQn{ #define PART_NUMBER "EFM32LG990F256" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */ -#define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */ -#define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */ -#define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */ -#define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */ -#define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */ -#define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */ -#define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */ -#define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */ -#define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */ -#define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */ -#define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */ -#define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */ -#define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */ -#define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */ -#define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */ -#define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */ +#define FLASH_MEM_BASE (0x0UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0xFFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x28UL) /**< FLASH used bits */ +#define AES_MEM_BASE (0x400E0000UL) /**< AES base address */ +#define AES_MEM_SIZE (0x400UL) /**< AES available address space */ +#define AES_MEM_END (0x400E03FFUL) /**< AES end address */ +#define AES_MEM_BITS (0x10UL) /**< AES used bits */ +#define USBC_MEM_BASE (0x40100000UL) /**< USBC base address */ +#define USBC_MEM_SIZE (0x40000UL) /**< USBC available address space */ +#define USBC_MEM_END (0x4013FFFFUL) /**< USBC end address */ +#define USBC_MEM_BITS (0x18UL) /**< USBC used bits */ +#define EBI_CODE_MEM_BASE (0x12000000UL) /**< EBI_CODE base address */ +#define EBI_CODE_MEM_SIZE (0xE000000UL) /**< EBI_CODE available address space */ +#define EBI_CODE_MEM_END (0x1FFFFFFFUL) /**< EBI_CODE end address */ +#define EBI_CODE_MEM_BITS (0x28UL) /**< EBI_CODE used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE0000UL) /**< PER available address space */ +#define PER_MEM_END (0x400DFFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x20UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x40000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2003FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x18UL) /**< RAM used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x20000UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x1001FFFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x17UL) /**< RAM_CODE used bits */ +#define EBI_MEM_BASE (0x80000000UL) /**< EBI base address */ +#define EBI_MEM_SIZE (0x40000000UL) /**< EBI available address space */ +#define EBI_MEM_END (0xBFFFFFFFUL) /**< EBI end address */ +#define EBI_MEM_BITS (0x30UL) /**< EBI used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFM32LG990F256 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h index 0f02fd7f1f..c6ed0f7cab 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h index 0f0de5fe89..6fe73cd442 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h index 6822e08df9..a7c38f5896 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_aes.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_AES register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h index d3d66cbcf8..d22688ce82 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h index 7b00fa11f6..39797c4372 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h index c0e45924c5..c45dbf9ea6 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_BURTC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h index eaa7c7cc1f..be133e875d 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_burtc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_BURTC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h index 62d4eb96e1..b68e4c6c69 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_calibrate.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_CALIBRATE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h index 432c41c6a8..a858092644 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h index 2cbea3c3bb..362b8835e7 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h index 68aac65dae..b913471944 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h index b5b15177b0..b5c5a82f0c 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h index 18c38a7437..e170b33295 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h index c965815a5c..7426740cf6 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h index 5568733457..e59b214047 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmactrl.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DMACTRL register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h index 2214717bc1..99cceaac9f 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h index 5553021c8d..969309a628 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_ebi.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_EBI register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h index f8893fa7a3..2c312a3fc3 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h index b09f075199..165eeddb2e 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_etm.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_ETM register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h index d30bfd710d..9197fd6ce8 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h index a24950d753..0fa7feb05e 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h index cf2a460a1d..63d9819030 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h index 30e5812797..99a2d435dd 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lcd.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LCD register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h index 3cdca97224..237ad6e9bf 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LESENSE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h index 689122e29f..c0ce33fe11 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_buf.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LESENSE_BUF register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h index 8b7d6c579e..5d4bde3e22 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LESENSE_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h index e0177e2acb..40a8874152 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_lesense_st.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LESENSE_ST register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h index c7fb84ec1a..a63d2eb2c3 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h index 8e06ef1287..5e95d94dc8 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h index 4695b11ff9..19eb585a3f 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h index c2d1d8248a..b408dd60ab 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h index 6095ff2cf4..d92852ef1f 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h index 5742b6554c..2a8dda5d6e 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h index add367e07e..561abc8786 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h index 9bed427ad6..7343af1551 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h index bda3420bab..ca6cdce68d 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h index 7640839897..e03049ef34 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_rtc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_RTC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h index 2bde3f415f..7c6494141e 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h index b1847df409..bfde025d71 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h index 1ad9e6e7c2..ab3338b3bd 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_uart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_UART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h index 291686892b..e5ac6bde48 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h index 7b1baf13c4..f1a6fb9cc1 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_USB register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h index c994c02f34..cb757a4886 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_diep.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_USB_DIEP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h index de1be680be..3509f3fd63 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_doep.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_USB_DOEP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h index 95d9a81a49..10187be768 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_usb_hc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_USB_HC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h index 94a6d092f6..39d851d054 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_vcmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_VCMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h index 7f2a9e63f2..eeec5ebd78 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h +++ b/cpu/efm32/families/efm32lg/include/vendor/efm32lg_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32LG_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/em_device.h b/cpu/efm32/families/efm32lg/include/vendor/em_device.h index ae80b69ba0..dcc70312e4 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/em_device.h +++ b/cpu/efm32/families/efm32lg/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h b/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h index b57f241347..af0082a603 100644 --- a/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h +++ b/cpu/efm32/families/efm32lg/include/vendor/system_efm32lg.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32lg/system.c b/cpu/efm32/families/efm32lg/system.c index 1cd863a2be..0bb00132d1 100644 --- a/cpu/efm32/families/efm32lg/system.c +++ b/cpu/efm32/families/efm32lg/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3 System Layer for EFM32LG devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h index 4f1ecbaf01..bd69b24150 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b500f1024gl125.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG12B500F1024GL125 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -153,86 +153,86 @@ typedef enum IRQn{ #define PART_NUMBER "EFM32PG12B500F1024GL125" /**< Part Number */ /** Memory Base addresses and limits */ -#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ -#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ -#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ -#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ -#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ -#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ -#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ -#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ -#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ -#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ -#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ -#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ -#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ -#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ -#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ -#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ -#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ -#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ -#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ -#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ -#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ -#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ -#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ -#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ -#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ -#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ -#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ -#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ -#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ -#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ -#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ -#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ -#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ -#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ -#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ -#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ -#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ -#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ -#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ -#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ -#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ -#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ -#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ -#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ -#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ -#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ -#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ -#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ -#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ -#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ -#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ -#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */ +#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFM32PG12B500F1024GL125 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h index bbbce5da65..16bf24e52a 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h index d87856f7a6..1950a1745f 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h index f1bbb0633b..98f58eed71 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h index 3f334e6d3e..26e7c0ef88 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h index 5bf7efdd16..b7ba43c26c 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -1578,7 +1578,7 @@ typedef struct { #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CRYOTIMER Clock Enable */ #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h index 713c964f44..0a73c46a41 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_cryotimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_CRYOTIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h index ce2ff6563e..655ad14b6a 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_crypto.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_CRYPTO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h index c104e3a84b..77f22c9d24 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_csen.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_CSEN register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h index d6ab79e617..644b2fa8fd 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h index 0b9b3a36aa..4dbb8fe194 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h index 3866261945..4c90eef020 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h index 8504342974..5bda130578 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h index 91c8177374..ff63788a4b 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_etm.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_ETM register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h index 445ca3214b..7e384a7742 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_fpueh.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_FPUEH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h index d55b080194..29e08600d2 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpcrc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_GPCRC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h index 0f3efa49c2..5828b3b723 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h index 6895a5700b..74ae321ac7 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h index ac0522fa5d..796be1544b 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h index f38878232b..ae727657b6 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_idac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_IDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h index 3127ef3b4c..32d7ff7007 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LDMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h index 0f1c14fb32..81e2c28f38 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_ldma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LDMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h index c488adf757..e7b26c1a83 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LESENSE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h index 190dd76ba8..d618b6d502 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_buf.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LESENSE_BUF register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h index c97428c3df..62efd790fb 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LESENSE_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h index bdb5556200..6177f7af83 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_lesense_st.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LESENSE_ST register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h index b4081ee9f3..84240ab314 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h index 0f09aeecbb..b4940c9c97 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h index ede6dfd330..e994dd58d0 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h index 3634830080..61809ec546 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h index b8913436eb..4c91043c6b 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h index 6509635876..a89a3cc780 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h index 4901e74140..dce6e98322 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h index 3502eba06f..3b8b4df279 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h index 6777b35567..e6e7cddc2e 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h index f375a05f35..d3e8e137fb 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_RTCC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h index 056e9480e5..d1f50b5c33 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_RTCC_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h index 66672de3fc..e50afb6d92 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_rtcc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_RTCC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h index c2dafb727e..d590949053 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_smu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_SMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -142,7 +142,7 @@ typedef struct { #define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CRYOTIMER access control bit */ #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h index 132b46c6e4..f00d1ec99c 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h index de20311875..b10c048695 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h index 5d7c9444af..98394911ff 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_trng.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_TRNG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h index 45c34bcae3..8ec6de9d97 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h index 60a889ab3b..9ee9e867f7 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_VDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h index 698e3f2947..ef29e50b31 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_vdac_opa.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_VDAC_OPA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h index ee6642b45c..6942f200c4 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h index 9378f7f20c..833e8daf99 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/efm32pg12b_wdog_pch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG12B_WDOG_PCH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h b/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h index 4c42b17ea8..76606cac3a 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h b/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h index 9ae4652856..54e28e3599 100644 --- a/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h +++ b/cpu/efm32/families/efm32pg12b/include/vendor/system_efm32pg12b.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg12b/system.c b/cpu/efm32/families/efm32pg12b/system.c index bfd77e8c95..0be22db05c 100644 --- a/cpu/efm32/families/efm32pg12b/system.c +++ b/cpu/efm32/families/efm32pg12b/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h index f3896103ee..b47d110f78 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b200f256gm48.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFM32PG1B200F256GM48 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -135,46 +135,46 @@ typedef enum IRQn{ #define PART_NUMBER "EFM32PG1B200F256GM48" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ -#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ -#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ -#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ -#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ -#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ -#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ -#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ -#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */ +#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */ +#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */ +#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */ +#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */ +#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */ +#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */ +#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */ +#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */ +#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */ +#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */ +#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */ +#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFM32PG1B200F256GM48 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h index 0d672e56fc..7fcff6014d 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h index 94f664fe5f..e9abcfc606 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h index 1e8af04e6a..abb30d40d5 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h index 0f2745cc3d..3064fa3425 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h index 11b2cd1f42..e0e84395a2 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -1438,7 +1438,7 @@ typedef struct { #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CryoTimer Clock Enable */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CRYOTIMER Clock Enable */ #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h index acceca4ceb..0853538028 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_cryotimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_CRYOTIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h index 3fa96aa708..7c3620879e 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_crypto.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_CRYPTO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h index 7d59df4685..b57d79517c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h index 8151cc2e21..921a7d77fd 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h index f5c87bfb53..d97ed8e342 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h index 818c9c3f95..504dacccaa 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h index c64638bff6..fda35d44c6 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_fpueh.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_FPUEH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h index 0d20e349e6..4dbddc1fd6 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpcrc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_GPCRC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h index 684c88411b..4733558f6d 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h index f08289dc0e..3a0fca1c0c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h index 643fb50c6e..7628b68d4e 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h index beb89be1c1..4768fe48d8 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_idac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_IDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h index 985016c0ba..8beabde46c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_LDMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h index 4dafd98bf5..7b78b090f4 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_ldma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_LDMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h index 7b8ad3ec4d..69d126584a 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h index 08249538a4..422cfa73c0 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h index 7cdfc813fb..3eca4993f1 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h index 3b9f23b0a8..4097232288 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h index eec104137d..271bf6806b 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h index 28d24e6487..48f1846076 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h index 666c0b6f7b..1cbc4f3004 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h index 4746f8cd81..a23d13503c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h index a4b3d26df4..6b115637f6 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h index 0bf362af7e..5aed970b6c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_RTCC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h index cdbb2463c4..095f0c0e55 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_RTCC_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h index 3aa59802d5..54b750150c 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_rtcc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_RTCC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h index 967ab1fa96..3560dc97b9 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h index cc77b76653..00af3b76f3 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h index f1cbdd878f..76254db0c1 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h index c4462ba121..9758cd6efb 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h index a786f9cc9d..95a57c6b60 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/efm32pg1b_wdog_pch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFM32PG1B_WDOG_PCH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h b/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h index b81d2ee81a..6369dd1e4d 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h b/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h index 77e9cca3d3..947ee96268 100644 --- a/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h +++ b/cpu/efm32/families/efm32pg1b/include/vendor/system_efm32pg1b.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efm32pg1b/system.c b/cpu/efm32/families/efm32pg1b/system.c index bfd77e8c95..0be22db05c 100644 --- a/cpu/efm32/families/efm32pg1b/system.c +++ b/cpu/efm32/families/efm32pg1b/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFM32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h index 6ee0b39e53..6abd26b3b7 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p332f1024gl125.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG12P332F1024GL125 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -167,86 +167,86 @@ typedef enum IRQn{ #define PART_NUMBER "EFR32MG12P332F1024GL125" /**< Part Number */ /** Memory Base addresses and limits */ -#define RAM0_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM0_CODE base address */ -#define RAM0_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM0_CODE available address space */ -#define RAM0_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM0_CODE end address */ -#define RAM0_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM0_CODE used bits */ -#define RAM2_MEM_BASE ((uint32_t) 0x20040000UL) /**< RAM2 base address */ -#define RAM2_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2 available address space */ -#define RAM2_MEM_END ((uint32_t) 0x200407FFUL) /**< RAM2 end address */ -#define RAM2_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2 used bits */ -#define RAM1_MEM_BASE ((uint32_t) 0x20020000UL) /**< RAM1 base address */ -#define RAM1_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1 available address space */ -#define RAM1_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM1 end address */ -#define RAM1_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1 used bits */ -#define CRYPTO1_BITCLR_MEM_BASE ((uint32_t) 0x440F0400UL) /**< CRYPTO1_BITCLR base address */ -#define CRYPTO1_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITCLR available address space */ -#define CRYPTO1_BITCLR_MEM_END ((uint32_t) 0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ -#define CRYPTO1_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400EFFFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM1_CODE_MEM_BASE ((uint32_t) 0x10020000UL) /**< RAM1_CODE base address */ -#define RAM1_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM1_CODE available address space */ -#define RAM1_CODE_MEM_END ((uint32_t) 0x1003FFFFUL) /**< RAM1_CODE end address */ -#define RAM1_CODE_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM1_CODE used bits */ -#define CRYPTO1_MEM_BASE ((uint32_t) 0x400F0400UL) /**< CRYPTO1 base address */ -#define CRYPTO1_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1 available address space */ -#define CRYPTO1_MEM_END ((uint32_t) 0x400F07FFUL) /**< CRYPTO1 end address */ -#define CRYPTO1_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1 used bits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define CRYPTO0_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO0 base address */ -#define CRYPTO0_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0 available address space */ -#define CRYPTO0_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO0 end address */ -#define CRYPTO0_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0 used bits */ -#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ -#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ -#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ -#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440EFFFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO0_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO0_BITSET base address */ -#define CRYPTO0_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITSET available address space */ -#define CRYPTO0_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO0_BITSET end address */ -#define CRYPTO0_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITSET used bits */ -#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ -#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ -#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ -#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ -#define CRYPTO0_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO0_BITCLR base address */ -#define CRYPTO0_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO0_BITCLR available address space */ -#define CRYPTO0_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ -#define CRYPTO0_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ -#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ -#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ -#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ -#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xF0000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460EFFFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define CRYPTO1_BITSET_MEM_BASE ((uint32_t) 0x460F0400UL) /**< CRYPTO1_BITSET base address */ -#define CRYPTO1_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO1_BITSET available address space */ -#define CRYPTO1_BITSET_MEM_END ((uint32_t) 0x460F07FFUL) /**< CRYPTO1_BITSET end address */ -#define CRYPTO1_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO1_BITSET used bits */ -#define RAM2_CODE_MEM_BASE ((uint32_t) 0x10040000UL) /**< RAM2_CODE base address */ -#define RAM2_CODE_MEM_SIZE ((uint32_t) 0x800UL) /**< RAM2_CODE available address space */ -#define RAM2_CODE_MEM_END ((uint32_t) 0x100407FFUL) /**< RAM2_CODE end address */ -#define RAM2_CODE_MEM_BITS ((uint32_t) 0x0000000BUL) /**< RAM2_CODE used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x2001FFFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x00000011UL) /**< RAM used bits */ +#define RAM0_CODE_MEM_BASE (0x10000000UL) /**< RAM0_CODE base address */ +#define RAM0_CODE_MEM_SIZE (0x20000UL) /**< RAM0_CODE available address space */ +#define RAM0_CODE_MEM_END (0x1001FFFFUL) /**< RAM0_CODE end address */ +#define RAM0_CODE_MEM_BITS (0x00000011UL) /**< RAM0_CODE used bits */ +#define RAM2_MEM_BASE (0x20040000UL) /**< RAM2 base address */ +#define RAM2_MEM_SIZE (0x800UL) /**< RAM2 available address space */ +#define RAM2_MEM_END (0x200407FFUL) /**< RAM2 end address */ +#define RAM2_MEM_BITS (0x0000000BUL) /**< RAM2 used bits */ +#define RAM1_MEM_BASE (0x20020000UL) /**< RAM1 base address */ +#define RAM1_MEM_SIZE (0x20000UL) /**< RAM1 available address space */ +#define RAM1_MEM_END (0x2003FFFFUL) /**< RAM1 end address */ +#define RAM1_MEM_BITS (0x00000011UL) /**< RAM1 used bits */ +#define CRYPTO1_BITCLR_MEM_BASE (0x440F0400UL) /**< CRYPTO1_BITCLR base address */ +#define CRYPTO1_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO1_BITCLR available address space */ +#define CRYPTO1_BITCLR_MEM_END (0x440F07FFUL) /**< CRYPTO1_BITCLR end address */ +#define CRYPTO1_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITCLR used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xF0000UL) /**< PER available address space */ +#define PER_MEM_END (0x400EFFFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM1_CODE_MEM_BASE (0x10020000UL) /**< RAM1_CODE base address */ +#define RAM1_CODE_MEM_SIZE (0x20000UL) /**< RAM1_CODE available address space */ +#define RAM1_CODE_MEM_END (0x1003FFFFUL) /**< RAM1_CODE end address */ +#define RAM1_CODE_MEM_BITS (0x00000011UL) /**< RAM1_CODE used bits */ +#define CRYPTO1_MEM_BASE (0x400F0400UL) /**< CRYPTO1 base address */ +#define CRYPTO1_MEM_SIZE (0x400UL) /**< CRYPTO1 available address space */ +#define CRYPTO1_MEM_END (0x400F07FFUL) /**< CRYPTO1 end address */ +#define CRYPTO1_MEM_BITS (0x0000000AUL) /**< CRYPTO1 used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define CRYPTO0_MEM_BASE (0x400F0000UL) /**< CRYPTO0 base address */ +#define CRYPTO0_MEM_SIZE (0x400UL) /**< CRYPTO0 available address space */ +#define CRYPTO0_MEM_END (0x400F03FFUL) /**< CRYPTO0 end address */ +#define CRYPTO0_MEM_BITS (0x0000000AUL) /**< CRYPTO0 used bits */ +#define CRYPTO_MEM_BASE CRYPTO0_MEM_BASE /**< Alias for CRYPTO0_MEM_BASE */ +#define CRYPTO_MEM_SIZE CRYPTO0_MEM_SIZE /**< Alias for CRYPTO0_MEM_SIZE */ +#define CRYPTO_MEM_END CRYPTO0_MEM_END /**< Alias for CRYPTO0_MEM_END */ +#define CRYPTO_MEM_BITS CRYPTO0_MEM_BITS /**< Alias for CRYPTO0_MEM_BITS */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xF0000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440EFFFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO0_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO0_BITSET base address */ +#define CRYPTO0_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO0_BITSET available address space */ +#define CRYPTO0_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO0_BITSET end address */ +#define CRYPTO0_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITSET used bits */ +#define CRYPTO_BITSET_MEM_BASE CRYPTO0_BITSET_MEM_BASE /**< Alias for CRYPTO0_BITSET_MEM_BASE */ +#define CRYPTO_BITSET_MEM_SIZE CRYPTO0_BITSET_MEM_SIZE /**< Alias for CRYPTO0_BITSET_MEM_SIZE */ +#define CRYPTO_BITSET_MEM_END CRYPTO0_BITSET_MEM_END /**< Alias for CRYPTO0_BITSET_MEM_END */ +#define CRYPTO_BITSET_MEM_BITS CRYPTO0_BITSET_MEM_BITS /**< Alias for CRYPTO0_BITSET_MEM_BITS */ +#define CRYPTO0_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO0_BITCLR base address */ +#define CRYPTO0_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO0_BITCLR available address space */ +#define CRYPTO0_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO0_BITCLR end address */ +#define CRYPTO0_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO0_BITCLR used bits */ +#define CRYPTO_BITCLR_MEM_BASE CRYPTO0_BITCLR_MEM_BASE /**< Alias for CRYPTO0_BITCLR_MEM_BASE */ +#define CRYPTO_BITCLR_MEM_SIZE CRYPTO0_BITCLR_MEM_SIZE /**< Alias for CRYPTO0_BITCLR_MEM_SIZE */ +#define CRYPTO_BITCLR_MEM_END CRYPTO0_BITCLR_MEM_END /**< Alias for CRYPTO0_BITCLR_MEM_END */ +#define CRYPTO_BITCLR_MEM_BITS CRYPTO0_BITCLR_MEM_BITS /**< Alias for CRYPTO0_BITCLR_MEM_BITS */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xF0000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460EFFFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define CRYPTO1_BITSET_MEM_BASE (0x460F0400UL) /**< CRYPTO1_BITSET base address */ +#define CRYPTO1_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO1_BITSET available address space */ +#define CRYPTO1_BITSET_MEM_END (0x460F07FFUL) /**< CRYPTO1_BITSET end address */ +#define CRYPTO1_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO1_BITSET used bits */ +#define RAM2_CODE_MEM_BASE (0x10040000UL) /**< RAM2_CODE base address */ +#define RAM2_CODE_MEM_SIZE (0x800UL) /**< RAM2_CODE available address space */ +#define RAM2_CODE_MEM_END (0x100407FFUL) /**< RAM2_CODE end address */ +#define RAM2_CODE_MEM_BITS (0x0000000BUL) /**< RAM2_CODE used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x20000UL) /**< RAM available address space */ +#define RAM_MEM_END (0x2001FFFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x00000011UL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFR32MG12P332F1024GL125 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h index 4e29e6109d..98c22f8506 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h index 55ab9882a2..7b8561619b 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h index 8a45367bfd..3503e8101c 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h index 8d9482a8ef..9cd3c1985f 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h index 3855f838c8..a968208af3 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -1578,7 +1578,7 @@ typedef struct { #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x800UL /**< Bit mask for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CryoTimer Clock Enable */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 12) /**< CRYOTIMER Clock Enable */ #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 12 /**< Shift value for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x1000UL /**< Bit mask for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h index 10dc650ba1..75079c701e 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_cryotimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_CRYOTIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h index b8ab345706..c87cf08037 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_crypto.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_CRYPTO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h index ff7138c3ae..7030b843e8 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_csen.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_CSEN register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h index b366e8124c..d3f8855548 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h index 4b381e4c9b..a3e002f158 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h index 9a7e5ffab6..7d51485c1a 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h index 0bbac615e1..f5398889c9 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h index da526bafb1..11e53ad2c0 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_etm.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_ETM register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h index 65eea4e07f..4e57f395e3 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_fpueh.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_FPUEH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h index bc938530f8..524763f350 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpcrc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_GPCRC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h index 6a84a333bc..2d5e8e23cb 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h index 7b92033d1e..13bda82a09 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h index 09ee8f7c25..412ad36eb7 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h index 8e575f11b2..cd57f96ea9 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_idac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_IDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h index a8ee2f2b44..104a031605 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LDMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h index 147516a9d3..a7b4f2762c 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_ldma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LDMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h index 5f11540abb..d280ee0086 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h index f84662b9bf..a3410bf4b5 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_buf.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_BUF register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h index 696fa1fb9b..9b5ad3e545 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h index 61b7f27bba..15a4e15abc 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_lesense_st.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LESENSE_ST register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h index 4a98ce99ad..24ccf6b55e 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h index 2fbc1cfd21..ac7e6777d9 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h index b794f9a591..abe906b75b 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h index 695329511d..0244745cf1 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h index d8ec32c661..3f93c92679 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h index a25e8e68dc..7e748f8c77 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h index 5a92efbd3f..e988832c1b 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h index bb3edd77ef..65b98dab01 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h index c6ef24959d..ff59b976f6 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h index ee0b554cc1..c97cde7568 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_RTCC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h index 09aea64715..4d3f20accc 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_RTCC_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h index 02e6d3bd05..53643b042f 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_rtcc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_RTCC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h index 99626834c4..9b566895b2 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_smu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_SMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -142,7 +142,7 @@ typedef struct { #define _SMU_PPUPATD0_CMU_MASK 0x20UL /**< Bit mask for SMU_CMU */ #define _SMU_PPUPATD0_CMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ #define SMU_PPUPATD0_CMU_DEFAULT (_SMU_PPUPATD0_CMU_DEFAULT << 5) /**< Shifted mode DEFAULT for SMU_PPUPATD0 */ -#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CryoTimer access control bit */ +#define SMU_PPUPATD0_CRYOTIMER (0x1UL << 7) /**< CRYOTIMER access control bit */ #define _SMU_PPUPATD0_CRYOTIMER_SHIFT 7 /**< Shift value for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_MASK 0x80UL /**< Bit mask for SMU_CRYOTIMER */ #define _SMU_PPUPATD0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for SMU_PPUPATD0 */ diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h index a1e8cb9590..82af4ff18e 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h index c4dc8cc0a8..ef234634ab 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h index f601967b63..9c92a3a0d8 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_trng.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_TRNG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h index 8ed402037d..36a7838c60 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h index e8853b1298..3aef190a9a 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_VDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h index 555bdeaae6..5edc0f440a 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_vdac_opa.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_VDAC_OPA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h index 37c70e9f2a..817212c48b 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h index bfe4ef1c1e..4e75f54c9f 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/efr32mg12p_wdog_pch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG12P_WDOG_PCH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h b/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h index 45c430f638..e097d7965c 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h b/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h index 9c73722a26..9938edaebb 100644 --- a/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h +++ b/cpu/efm32/families/efr32mg12p/include/vendor/system_efr32mg12p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg12p/system.c b/cpu/efm32/families/efr32mg12p/system.c index a74ab0d853..d536d23dfc 100644 --- a/cpu/efm32/families/efr32mg12p/system.c +++ b/cpu/efm32/families/efr32mg12p/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h index 06dacce8f2..991e2953ab 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm32.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM32 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -149,46 +149,46 @@ typedef enum IRQn{ #define PART_NUMBER "EFR32MG1P132F256GM32" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ -#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ -#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ -#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ -#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ -#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ -#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ -#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ -#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */ +#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */ +#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */ +#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */ +#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */ +#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */ +#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */ +#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */ +#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */ +#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */ +#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */ +#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */ +#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFR32MG1P132F256GM32 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h index f0d651f539..f41d360eb3 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p132f256gm48.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P132F256GM48 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -149,46 +149,46 @@ typedef enum IRQn{ #define PART_NUMBER "EFR32MG1P132F256GM48" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ -#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ -#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ -#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ -#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ -#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ -#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ -#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ -#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */ +#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */ +#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */ +#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */ +#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */ +#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */ +#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */ +#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */ +#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */ +#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */ +#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */ +#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */ +#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFR32MG1P132F256GM48 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h index 9a62484e5b..0e6f3ed9ae 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p233f256gm48.h @@ -2,10 +2,10 @@ * @file * @brief CMSIS Cortex-M Peripheral Access Layer Header File * for EFR32MG1P233F256GM48 - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -149,46 +149,46 @@ typedef enum IRQn{ #define PART_NUMBER "EFR32MG1P233F256GM48" /**< Part Number */ /** Memory Base addresses and limits */ -#define FLASH_MEM_BASE ((uint32_t) 0x00000000UL) /**< FLASH base address */ -#define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */ -#define FLASH_MEM_END ((uint32_t) 0x0FFFFFFFUL) /**< FLASH end address */ -#define FLASH_MEM_BITS ((uint32_t) 0x0000001CUL) /**< FLASH used bits */ -#define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */ -#define RAM_CODE_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM_CODE available address space */ -#define RAM_CODE_MEM_END ((uint32_t) 0x10007BFFUL) /**< RAM_CODE end address */ -#define RAM_CODE_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM_CODE used bits */ -#define PER_BITCLR_MEM_BASE ((uint32_t) 0x44000000UL) /**< PER_BITCLR base address */ -#define PER_BITCLR_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITCLR available address space */ -#define PER_BITCLR_MEM_END ((uint32_t) 0x440E7FFFUL) /**< PER_BITCLR end address */ -#define PER_BITCLR_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITCLR used bits */ -#define CRYPTO_BITSET_MEM_BASE ((uint32_t) 0x460F0000UL) /**< CRYPTO_BITSET base address */ -#define CRYPTO_BITSET_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITSET available address space */ -#define CRYPTO_BITSET_MEM_END ((uint32_t) 0x460F03FFUL) /**< CRYPTO_BITSET end address */ -#define CRYPTO_BITSET_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITSET used bits */ -#define CRYPTO_MEM_BASE ((uint32_t) 0x400F0000UL) /**< CRYPTO base address */ -#define CRYPTO_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO available address space */ -#define CRYPTO_MEM_END ((uint32_t) 0x400F03FFUL) /**< CRYPTO end address */ -#define CRYPTO_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO used bits */ -#define CRYPTO_BITCLR_MEM_BASE ((uint32_t) 0x440F0000UL) /**< CRYPTO_BITCLR base address */ -#define CRYPTO_BITCLR_MEM_SIZE ((uint32_t) 0x400UL) /**< CRYPTO_BITCLR available address space */ -#define CRYPTO_BITCLR_MEM_END ((uint32_t) 0x440F03FFUL) /**< CRYPTO_BITCLR end address */ -#define CRYPTO_BITCLR_MEM_BITS ((uint32_t) 0x0000000AUL) /**< CRYPTO_BITCLR used bits */ -#define PER_BITSET_MEM_BASE ((uint32_t) 0x46000000UL) /**< PER_BITSET base address */ -#define PER_BITSET_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER_BITSET available address space */ -#define PER_BITSET_MEM_END ((uint32_t) 0x460E7FFFUL) /**< PER_BITSET end address */ -#define PER_BITSET_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER_BITSET used bits */ -#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */ -#define PER_MEM_SIZE ((uint32_t) 0xE8000UL) /**< PER available address space */ -#define PER_MEM_END ((uint32_t) 0x400E7FFFUL) /**< PER end address */ -#define PER_MEM_BITS ((uint32_t) 0x00000014UL) /**< PER used bits */ -#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */ -#define RAM_MEM_SIZE ((uint32_t) 0x7C00UL) /**< RAM available address space */ -#define RAM_MEM_END ((uint32_t) 0x20007BFFUL) /**< RAM end address */ -#define RAM_MEM_BITS ((uint32_t) 0x0000000FUL) /**< RAM used bits */ +#define FLASH_MEM_BASE (0x00000000UL) /**< FLASH base address */ +#define FLASH_MEM_SIZE (0x10000000UL) /**< FLASH available address space */ +#define FLASH_MEM_END (0x0FFFFFFFUL) /**< FLASH end address */ +#define FLASH_MEM_BITS (0x0000001CUL) /**< FLASH used bits */ +#define RAM_CODE_MEM_BASE (0x10000000UL) /**< RAM_CODE base address */ +#define RAM_CODE_MEM_SIZE (0x7C00UL) /**< RAM_CODE available address space */ +#define RAM_CODE_MEM_END (0x10007BFFUL) /**< RAM_CODE end address */ +#define RAM_CODE_MEM_BITS (0x0000000FUL) /**< RAM_CODE used bits */ +#define PER_BITCLR_MEM_BASE (0x44000000UL) /**< PER_BITCLR base address */ +#define PER_BITCLR_MEM_SIZE (0xE8000UL) /**< PER_BITCLR available address space */ +#define PER_BITCLR_MEM_END (0x440E7FFFUL) /**< PER_BITCLR end address */ +#define PER_BITCLR_MEM_BITS (0x00000014UL) /**< PER_BITCLR used bits */ +#define CRYPTO_BITSET_MEM_BASE (0x460F0000UL) /**< CRYPTO_BITSET base address */ +#define CRYPTO_BITSET_MEM_SIZE (0x400UL) /**< CRYPTO_BITSET available address space */ +#define CRYPTO_BITSET_MEM_END (0x460F03FFUL) /**< CRYPTO_BITSET end address */ +#define CRYPTO_BITSET_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITSET used bits */ +#define CRYPTO_MEM_BASE (0x400F0000UL) /**< CRYPTO base address */ +#define CRYPTO_MEM_SIZE (0x400UL) /**< CRYPTO available address space */ +#define CRYPTO_MEM_END (0x400F03FFUL) /**< CRYPTO end address */ +#define CRYPTO_MEM_BITS (0x0000000AUL) /**< CRYPTO used bits */ +#define CRYPTO_BITCLR_MEM_BASE (0x440F0000UL) /**< CRYPTO_BITCLR base address */ +#define CRYPTO_BITCLR_MEM_SIZE (0x400UL) /**< CRYPTO_BITCLR available address space */ +#define CRYPTO_BITCLR_MEM_END (0x440F03FFUL) /**< CRYPTO_BITCLR end address */ +#define CRYPTO_BITCLR_MEM_BITS (0x0000000AUL) /**< CRYPTO_BITCLR used bits */ +#define PER_BITSET_MEM_BASE (0x46000000UL) /**< PER_BITSET base address */ +#define PER_BITSET_MEM_SIZE (0xE8000UL) /**< PER_BITSET available address space */ +#define PER_BITSET_MEM_END (0x460E7FFFUL) /**< PER_BITSET end address */ +#define PER_BITSET_MEM_BITS (0x00000014UL) /**< PER_BITSET used bits */ +#define PER_MEM_BASE (0x40000000UL) /**< PER base address */ +#define PER_MEM_SIZE (0xE8000UL) /**< PER available address space */ +#define PER_MEM_END (0x400E7FFFUL) /**< PER end address */ +#define PER_MEM_BITS (0x00000014UL) /**< PER used bits */ +#define RAM_MEM_BASE (0x20000000UL) /**< RAM base address */ +#define RAM_MEM_SIZE (0x7C00UL) /**< RAM available address space */ +#define RAM_MEM_END (0x20007BFFUL) /**< RAM end address */ +#define RAM_MEM_BITS (0x0000000FUL) /**< RAM used bits */ /** Bit banding area */ -#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */ -#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */ +#define BITBAND_PER_BASE (0x42000000UL) /**< Peripheral Address Space bit-band area */ +#define BITBAND_RAM_BASE (0x22000000UL) /**< SRAM Address Space bit-band area */ /** Flash and SRAM limits for EFR32MG1P233F256GM48 */ #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */ diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h index 104b9ebeab..5e133ff282 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_acmp.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_ACMP register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h index f6d7b86d79..520b9e0215 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_adc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_ADC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h index d9afeb8547..714cd29ae3 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_pins.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_AF_PINS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h index 2428dfd2a3..67464a4234 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_af_ports.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_AF_PORTS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h index 6f310fa639..1078fa2375 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_CMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib @@ -1438,7 +1438,7 @@ typedef struct { #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x20UL /**< Bit mask for CMU_ACMP1 */ #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CryoTimer Clock Enable */ +#define CMU_HFPERCLKEN0_CRYOTIMER (0x1UL << 6) /**< CRYOTIMER Clock Enable */ #define _CMU_HFPERCLKEN0_CRYOTIMER_SHIFT 6 /**< Shift value for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_MASK 0x40UL /**< Bit mask for CMU_CRYOTIMER */ #define _CMU_HFPERCLKEN0_CRYOTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */ diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h index c54cbb3a52..6139f7a8da 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_cryotimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_CRYOTIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h index c3741ace5e..79fc62c3ef 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_crypto.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_CRYPTO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h index 9c2cf4807e..21ca64d139 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_devinfo.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_DEVINFO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h index fe1a8c1d82..14419ac2d8 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dma_descriptor.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_DMA_DESCRIPTOR register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h index 7e47f8eb9b..7779fa3131 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_dmareq.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_DMAREQ register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h index 32d7c4a32e..9e346164f5 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_emu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_EMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h index e6a5928d6d..762e559561 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_fpueh.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_FPUEH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h index 7abbfe04e2..2c2a2be776 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpcrc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_GPCRC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h index 33f13a8d21..be6abd2fcc 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_GPIO register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h index 9e64d4bfe9..7ec5a3cdf4 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_gpio_p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_GPIO_P register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h index 0ca6b4b971..1efd280d00 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_i2c.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_I2C register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h index 2394b5bb53..d469180d03 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_idac.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_IDAC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h index be7b13dd38..079317b830 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_LDMA register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h index a44a46fd05..95d05b2f37 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_ldma_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_LDMA_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h index 70d5d81af7..0fa3857728 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_letimer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_LETIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h index cfb6851e28..5f194ffa01 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_leuart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_LEUART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h index 1c840cf97f..d22d478a56 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_msc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_MSC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h index cc50001542..7748520357 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_pcnt.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_PCNT register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h index 3e25fb90cc..173ec9d4b9 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_PRS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h index a53ad8ee35..801f4a22a5 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_ch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_PRS_CH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h index 80e5dd153d..ed463658d9 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_prs_signals.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_PRS_SIGNALS register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h index 082d1af56d..bbb8609870 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rmu.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_RMU register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h index a2891ac6cd..c38585cb4e 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_romtable.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_ROMTABLE register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h index 3b6528745b..0c821775ab 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_RTCC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h index 788a0ebdf7..fdcb0fd530 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_RTCC_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h index c1bf4f42fb..d8bda66c1f 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_rtcc_ret.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_RTCC_RET register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h index 3e3be68eab..c5981da94a 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_TIMER register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h index e582307a6b..947c2deeba 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_timer_cc.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_TIMER_CC register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h index c506c6c998..17a5cdfe07 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_usart.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_USART register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h index 3ac17a3da0..975c28b8e5 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_WDOG register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h index 88aac9326b..c5f4d242a7 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/efr32mg1p_wdog_pch.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief EFR32MG1P_WDOG_PCH register and bit field definitions - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h b/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h index 1580c95857..0058e02bf0 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/em_device.h @@ -11,10 +11,10 @@ * Add "#include "em_device.h" to your source files * @endverbatim * - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h b/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h index 4d7c394a18..3997bd2e64 100644 --- a/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h +++ b/cpu/efm32/families/efr32mg1p/include/vendor/system_efr32mg1p.h @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib diff --git a/cpu/efm32/families/efr32mg1p/system.c b/cpu/efm32/families/efr32mg1p/system.c index 33afd976e2..7a71aa3ac3 100644 --- a/cpu/efm32/families/efr32mg1p/system.c +++ b/cpu/efm32/families/efr32mg1p/system.c @@ -1,10 +1,10 @@ /***************************************************************************//** * @file * @brief CMSIS Cortex-M3/M4 System Layer for EFR32 devices. - * @version 5.7.0 + * @version 5.8.3 ******************************************************************************* * # License - * Copyright 2018 Silicon Laboratories Inc. www.silabs.com + * Copyright 2019 Silicon Laboratories Inc. www.silabs.com ******************************************************************************* * * SPDX-License-Identifier: Zlib