cpu/stm32_common: unify stmclk for stm32f[2|4|7] and adapt to use clk_conf
This commit is contained in:
Vincent Dupont
parent
400158537f
commit
d2a4acecd9
179
cpu/stm32_common/stmclk.c
Normal file
179
cpu/stm32_common/stmclk.c
Normal file
@ -0,0 +1,179 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32_common
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#ifndef CLOCK_CORECLOCK
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#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#if (CLOCK_ENABLE_PLL_I2S)
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#ifdef RCC_PLLI2SCFGR_PLLI2SM_Pos
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#define PLLI2S_M (CLOCK_PLL_I2S_M << RCC_PLLI2SCFGR_PLLI2SM_Pos)
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#else
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#define PLLI2S_M (0)
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#endif
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#define PLLI2S_N (CLOCK_PLL_I2S_N << RCC_PLLI2SCFGR_PLLI2SN_Pos)
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#ifdef RCC_PLLI2SCFGR_PLLI2SP_Pos
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#define PLLI2S_P (((CLOCK_PLL_I2S_P / 2) - 1) << RCC_PLLI2SCFGR_PLLI2SP_Pos)
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#else
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#define PLLI2S_P (0)
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#endif
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#define PLLI2S_Q (CLOCK_PLL_I2S_Q << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
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#endif /* CLOCK_ENABLE_PLLI_2S */
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#if (CLOCK_ENABLE_PLL_SAI)
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#ifdef RCC_PLLSAICFGR_PLLSAIN_Pos
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#define PLLSAI_M (CLOCK_PLL_SAI_M << RCC_PLLSAICFGR_PLLSAIN_Pos)
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#else
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#define PLLSAI_M (0)
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#endif
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#define PLLSAI_N (CLOCK_PLL_SAI_N << RCC_PLLSAICFGR_PLLSAIN_Pos)
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#ifdef RCC_PLLSAICFGR_PLLSAIP_Pos
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#define PLLSAI_P (((CLOCK_PLL_SAI_P / 2) - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
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#else
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#define PLLSAI_P (0)
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#endif
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#define PLLSAI_Q (CLOCK_PLL_SAI_Q << RCC_PLLSAICFGR_PLLSAIQ_Pos)
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#endif /* CLOCK_ENABLE_PLL_SAI */
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#if defined(CPU_FAM_STM32F2)
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#define RCC_PLLCFGR_PLLP_Pos (16U)
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#define RCC_PLLCFGR_PLLM_Pos (0U)
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#define RCC_PLLCFGR_PLLN_Pos (6U)
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#define RCC_PLLCFGR_PLLQ_Pos (24U)
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#endif
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/* now we get the actual bitfields */
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#define PLL_P (((CLOCK_PLL_P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos)
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#elif defined(CPU_FAM_STM32F7)
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#define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES)
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#endif
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* Flash config */
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FLASH->ACR = FLASH_ACR_CONFIG;
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
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#if (CLOCK_MCO1_SRC)
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#ifndef RCC_CFGR_MCO1
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#error "stmclk: no MCO1 on this device"
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#endif
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RCC->CFGR |= CLOCK_MCO1_SRC | CLOCK_MCO1_PRE;
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#endif
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#if (CLOCK_MCO2_SRC)
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#ifndef RCC_CFGR_MCO2
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#error "stmclk: no MCO2 on this device"
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#endif
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RCC->CFGR |= CLOCK_MCO2_SRC | CLOCK_MCO2_PRE;
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#endif
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/* if configured, we need to enable the HSE clock now */
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#if (CLOCK_HSE)
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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#if CLOCK_USE_ALT_48MHZ
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RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL;
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#endif
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/* now we can safely configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now that the PLL is running, we use it as system clock */
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RCC->CFGR |= (RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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stmclk_disable_hsi();
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#if (CLOCK_ENABLE_PLLI2S)
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RCC->PLLI2SCFGR = (PLLI2S_SRC | PLLI2S_M | PLLI2S_N | PLLI2s_P | PLLI2S_Q);
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RCC->CR |= (RCC_CR_PLLI2SON);
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while (!(RCC->CR & RCC_CR_PLLI2SRDY)) {}
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#endif /* CLOCK_ENABLE_PLLI2S */
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#if (CLOCK_ENABLE_PLLSAI)
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RCC->PLLSAICFGR = (PLLSAI_M | PLLSAI_N | PLLSAI_P | PLLSAI_Q);
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RCC->CR |= (RCC_CR_PLLSAION);
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while (!(RCC->CR & RCC_CR_PLLSAIRDY)) {}
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#endif
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irq_restore(is);
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}
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#else
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typedef int dont_be_pedantic;
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#endif /* defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */
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@ -1,147 +0,0 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32f2
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (16000000U) /* HSI fixed @ 16MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#ifndef P
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/* we fix P to 2 (so the PLL output equals 2 * CLOCK_CORECLOCK) */
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#define P (2U)
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#if ((P != 2) && (P != 4) && (P != 6) && (P != 8))
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#error "PLL configuration: PLL P value is invalid"
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#endif
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#endif /* P */
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/* the recommended input clock for the PLL should be 2MHz */
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#define M (PLL_IN / 2000000U)
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#if ((M < 2) || (M > 63))
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#error "PLL configuration: PLL M value is out of range"
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#endif
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/* next we multiply the input freq to 2 * CORECLOCK */
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#define N (P * CLOCK_CORECLOCK / 2000000U)
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#if ((N < 50) || (N > 432))
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#error "PLL configuration: PLL N value is out of range"
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#endif
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/* finally we need to set Q, so that the USB clock is 48MHz */
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#define Q ((P * CLOCK_CORECLOCK) / 48000000U)
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#if ((Q * 48000000U) != (P * CLOCK_CORECLOCK))
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#error "PLL configuration: USB frequency is not 48MHz"
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#endif
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#define RCC_PLLCFGR_PLLP_Pos (16U)
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#define RCC_PLLCFGR_PLLM_Pos (0U)
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#define RCC_PLLCFGR_PLLN_Pos (6U)
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#define RCC_PLLCFGR_PLLQ_Pos (24U)
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/* now we get the actual bitfields */
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#define PLL_P (((P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_M (M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_Q (Q << RCC_PLLCFGR_PLLQ_Pos)
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {}
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/* we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
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/* disable all active clocks except HSI -> resets the clk configuration */
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RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
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/* if configured, we need to enable the HSE clock now */
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#if (CLOCK_HSE)
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RCC->CR |= (RCC_CR_HSEON);
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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#ifdef ENABLE_PLLI2S_MCO2
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/* reset PLL I2S config register */
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RCC->PLLI2SCFGR = 0x00000000U;
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/* set PLL I2S division factor */
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RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_R & 0x07) << 28;
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/* set PLL I2S multiplication factor */
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RCC->PLLI2SCFGR |= (CLOCK_PLL_I2S_N & 0x1FF) << 6;
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/* MCO2 output is PLLI2S */
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RCC->CFGR |= (uint32_t) RCC_CFGR_MCO2_0;
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RCC->CFGR &= ~(uint32_t) RCC_CFGR_MCO2_1;
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/* MCO2 prescaler div by 5 */
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RCC->CFGR |= (uint32_t) ((CLOCK_MC02_PRE + 4 - 2) & 0x7) << 27;
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/* enable PLL I2S clock */
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RCC->CR |= RCC_CR_PLLI2SON;
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/* wait till PLL I2S clock is ready */
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while ((RCC->CR & RCC_CR_PLLI2SRDY) == 0) {}
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#endif
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/* now we can safely configure and start the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
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RCC->CR |= (RCC_CR_PLLON);
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now that the PLL is running, we use it as system clock */
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RCC->CFGR |= (RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
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stmclk_disable_hsi();
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irq_restore(is);
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}
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@ -1,124 +0,0 @@
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/*
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* Copyright (C) 2017 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
|
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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||||
*/
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/**
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* @ingroup cpu_stm32f4
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* @{
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*
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* @file
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* @brief Implementation of STM32 clock configuration
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @}
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*/
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#include "cpu.h"
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#include "stmclk.h"
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#include "periph_conf.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (16000000U) /* HSI fixed @ 16MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
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#endif
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#ifndef P
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/* we fix P to 2 (so the PLL output equals 2 * CLOCK_CORECLOCK) */
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#define P (2U)
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#if ((P != 2) && (P != 4) && (P != 6) && (P != 8))
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#error "PLL configuration: PLL P value is invalid"
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#endif
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#endif /* P */
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/* the recommended input clock for the PLL should be 2MHz */
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#define M (PLL_IN / 2000000U)
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#if ((M < 2) || (M > 63))
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#error "PLL configuration: PLL M value is out of range"
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#endif
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/* next we multiply the input freq to 2 * CORECLOCK */
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#define N (P * CLOCK_CORECLOCK / 2000000U)
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#if ((N < 50) || (N > 432))
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#error "PLL configuration: PLL N value is out of range"
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#endif
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/* finally we need to set Q, so that the USB clock is 48MHz */
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#define Q ((P * CLOCK_CORECLOCK) / 48000000U)
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#if ((Q * 48000000U) != (P * CLOCK_CORECLOCK))
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#error "PLL configuration: USB frequency is not 48MHz"
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#endif
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/* now we get the actual bitfields */
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#define PLL_P (((P / 2) - 1) << RCC_PLLCFGR_PLLP_Pos)
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#define PLL_M (M << RCC_PLLCFGR_PLLM_Pos)
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#define PLL_N (N << RCC_PLLCFGR_PLLN_Pos)
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#define PLL_Q (Q << RCC_PLLCFGR_PLLQ_Pos)
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
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/** @} */
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void stmclk_init_sysclk(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIR = 0;
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/* enable HSI clock for the duration of initialization */
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stmclk_enable_hsi();
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/* use HSI as system clock while we do any further configuration and
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||||
* configure the AHB and APB clock dividers as configure by the board */
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
|
||||
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_HSI) {}
|
||||
|
||||
/* we enable I+D cashes, pre-fetch, and we set the actual number of
|
||||
* needed flash wait states */
|
||||
FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
|
||||
|
||||
/* disable all active clocks except HSI -> resets the clk configuration */
|
||||
RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
|
||||
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
#if (CLOCK_HSE)
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
#endif
|
||||
|
||||
/* now we can safely configure and start the PLL */
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
/* now that the PLL is running, we use it as system clock */
|
||||
RCC->CFGR |= (RCC_CFGR_SW_PLL);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
|
||||
|
||||
stmclk_disable_hsi();
|
||||
irq_restore(is);
|
||||
}
|
||||
@ -1,117 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_stm32f7
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of STM32 clock configuration
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
#include "stmclk.h"
|
||||
#include "periph_conf.h"
|
||||
|
||||
/* make sure we have all needed information about the clock configuration */
|
||||
#ifndef CLOCK_HSE
|
||||
#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
|
||||
#endif
|
||||
#ifndef CLOCK_LSE
|
||||
#error "Please provide CLOCK_LSE in your board's periph_conf.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name PLL configuration
|
||||
* @{
|
||||
*/
|
||||
/* figure out which input to use */
|
||||
#if (CLOCK_HSE)
|
||||
#define PLL_IN CLOCK_HSE
|
||||
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
|
||||
#else
|
||||
#define PLL_IN (16000000U) /* HSI fixed @ 16MHz */
|
||||
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
|
||||
#endif
|
||||
|
||||
/* we fix P to 2 (so the PLL output equals 2 * CLOCK_CORECLOCK) */
|
||||
#define P (2U)
|
||||
/* the recommended input clock for the PLL should be 2MHz > ref. man. p. 143 */
|
||||
#define M (PLL_IN / 2000000U)
|
||||
#if ((M < 2) || (M > 63))
|
||||
#error "PLL configuration: PLL M value is out of range"
|
||||
#endif
|
||||
/* next we multiply the input freq to 2 * CORECLOCK */
|
||||
#define N (P * CLOCK_CORECLOCK / 2000000U)
|
||||
#if ((N < 50) || (N > 432))
|
||||
#error "PLL configuration: PLL N value is out of range"
|
||||
#endif
|
||||
/* finally we need to set Q, so that the USB clock is 48MHz */
|
||||
#define Q ((P * CLOCK_CORECLOCK) / 48000000U)
|
||||
#if ((Q * 48000000U) != (P * CLOCK_CORECLOCK))
|
||||
#error "PLL configuration: USB frequency is not 48MHz"
|
||||
#endif
|
||||
|
||||
/* now we get the actual bitfields */
|
||||
#define PLL_P (0)
|
||||
#define PLL_M (M << RCC_PLLCFGR_PLLM_Pos)
|
||||
#define PLL_N (N << RCC_PLLCFGR_PLLN_Pos)
|
||||
#define PLL_Q (Q << RCC_PLLCFGR_PLLQ_Pos)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Deduct the needed flash wait states from the core clock frequency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U)
|
||||
/** @} */
|
||||
|
||||
void stmclk_init_sysclk(void)
|
||||
{
|
||||
/* disable any interrupts. Global interrupts could be enabled if this is
|
||||
* called from some kind of bootloader... */
|
||||
unsigned is = irq_disable();
|
||||
RCC->CIR = 0;
|
||||
|
||||
/* enable HSI clock for the duration of initialization */
|
||||
stmclk_enable_hsi();
|
||||
|
||||
/* use HSI as system clock while we do any further configuration and
|
||||
* configure the AHB and APB clock dividers as configure by the board */
|
||||
RCC->CFGR = (RCC_CFGR_SW_HSI | CLOCK_AHB_DIV |
|
||||
CLOCK_APB1_DIV | CLOCK_APB2_DIV);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_HSI) {}
|
||||
|
||||
/* we enable I+D cashes, pre-fetch, and we set the actual number of
|
||||
* needed flash wait states */
|
||||
FLASH->ACR = (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
|
||||
|
||||
/* disable all active clocks except HSI -> resets the clk configuration */
|
||||
RCC->CR = (RCC_CR_HSION | RCC_CR_HSITRIM_4);
|
||||
|
||||
/* if configured, we need to enable the HSE clock now */
|
||||
#if (CLOCK_HSE)
|
||||
RCC->CR |= (RCC_CR_HSEON);
|
||||
while (!(RCC->CR & RCC_CR_HSERDY)) {}
|
||||
#endif
|
||||
|
||||
/* now we can safely configure and start the PLL */
|
||||
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q);
|
||||
RCC->CR |= (RCC_CR_PLLON);
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
|
||||
|
||||
/* now that the PLL is running, we use it as system clock */
|
||||
RCC->CFGR |= (RCC_CFGR_SW_PLL);
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
|
||||
|
||||
stmclk_disable_hsi();
|
||||
irq_restore(is);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user