From d6b8df1ff716570610760b82db0fe62691742e11 Mon Sep 17 00:00:00 2001 From: Benjamin Valentin Date: Wed, 12 Jun 2019 18:19:30 +0200 Subject: [PATCH] cpu/samd21: allow to use XOSC32K for GCLK2 GCLK2 is needed by RTC/RTT, so make it possible to configure it with XOSC32K as source. --- cpu/samd21/cpu.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/cpu/samd21/cpu.c b/cpu/samd21/cpu.c index 9590e9fccd..5c0481c7fc 100644 --- a/cpu/samd21/cpu.c +++ b/cpu/samd21/cpu.c @@ -187,14 +187,20 @@ static void clk_init(void) /* make sure we synchronize clock generator 0 before we go on */ while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {} -#if GEN2_ULP32K /* Setup Clock generator 2 with divider 1 (32.768kHz) */ GCLK->GENDIV.reg = (GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(0)); - GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN | - GCLK_GENCTRL_RUNSTDBY | - GCLK_GENCTRL_SRC_OSCULP32K); + GCLK->GENCTRL.reg = (GCLK_GENCTRL_ID(2) | GCLK_GENCTRL_GENEN + | GCLK_GENCTRL_RUNSTDBY +#if GEN2_ULP32K + | GCLK_GENCTRL_SRC_OSCULP32K); +#else + | GCLK_GENCTRL_SRC_XOSC32K); - while (GCLK->STATUS.bit.SYNCBUSY) {} + SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_ONDEMAND + | SYSCTRL_XOSC32K_EN32K + | SYSCTRL_XOSC32K_XTALEN + | SYSCTRL_XOSC32K_STARTUP(6) + | SYSCTRL_XOSC32K_ENABLE; #endif /* redirect all peripherals to a disabled clock generator (7) by default */