diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h
new file mode 100644
index 0000000000..cc668aab03
--- /dev/null
+++ b/cpu/stm32/include/clk/clk_conf.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2020 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           Main header for STM32 clock configuration
+ *
+ * @author          Alexandre Abadie <alexandre.abadie@inria.fr>
+*/
+
+#ifndef CLK_CLK_CONF_H
+#define CLK_CLK_CONF_H
+
+#include "kernel_defines.h"
+#include "macros/units.h"
+
+#if defined(CPU_FAM_STM32F0)
+#include "f0/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3)
+#include "f1f3/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
+      defined(CPU_FAM_STM32F7)
+#include "f2f4f7/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32G0)
+#include "g0/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32G4)
+#include "g4/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
+#include "l0l1/cfg_clock_default.h"
+#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
+      defined(CPU_FAM_STM32WB)
+#include "l4/cfg_clock_default.h"
+#else
+#error "No clock configuration available"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CLK_CLK_CONF_H */
+/** @} */
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
new file mode 100644
index 0000000000..cfe930b674
--- /dev/null
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2020 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser General
+ * Public License v2.1. See the file LICENSE in the top level directory for more
+ * details.
+ */
+
+/**
+ * @ingroup         cpu_stm32
+ * @{
+ *
+ * @file
+ * @brief           Main header for STM32F2/F4/F7 clock configuration
+ *
+ * @author          Alexandre Abadie <alexandre.abadie@inria.fr>
+*/
+
+#ifndef CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
+#define CLK_F2F4F7_CFG_CLOCK_DEFAULT_H
+
+#if defined(CPU_FAM_STM32F2)
+#include "f2f4f7/cfg_clock_default_120.h"
+#elif defined(CPU_FAM_STM32F4)
+#if defined(CPU_LINE_STM32F401xC) || defined(CPU_LINE_STM32F401xE)
+#include "f2f4f7/cfg_clock_default_84.h"
+#elif defined(CPU_LINE_STM32F410Cx) || defined(CPU_LINE_STM32F410Rx) || \
+      defined(CPU_LINE_STM32F410Tx) || defined(CPU_LINE_STM32F411xE) || \
+      defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
+      defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
+      defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)
+#include "f2f4f7/cfg_clock_default_100.h"
+#elif defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
+      defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
+      defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F437xx) || \
+      defined(CPU_LINE_STM32F429xx) || defined(CPU_LINE_STM32F439xx) || \
+      defined(CPU_LINE_STM32F446xx) || defined(CPU_LINE_STM32F469xx) || \
+      defined(CPU_LINE_STM32F479xx)
+#include "f2f4f7/cfg_clock_default_180.h"
+#else
+#error "No clock configuration available for this F4 line"
+#endif
+#elif defined(CPU_FAM_STM32F7)
+#include "f2f4f7/cfg_clock_default_216.h"
+#else
+#error "No clock configuration available for this family"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CLK_F2F4F7_CFG_CLOCK_DEFAULT_H */
+/** @} */