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cpu: boards: stm32gx: compile code for all possible clock modes

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This commit is contained in:
Alexandre Abadie 2020-08-29 19:44:11 +02:00
parent d4f576f677
commit d78a316139
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GPG Key ID: 1C919A403CAE1405
2 changed files with 61 additions and 56 deletions
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3
boards/common/stm32/include/g0/cfg_clock_default.h
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@ -88,10 +88,11 @@ extern "C" {
#define CLOCK_HSI MHZ(16) #define CLOCK_HSI MHZ(16)
#if CONFIG_USE_CLOCK_HSI
#ifndef CONFIG_CLOCK_HSISYS_DIV #ifndef CONFIG_CLOCK_HSISYS_DIV
#define CONFIG_CLOCK_HSISYS_DIV (1) #define CONFIG_CLOCK_HSISYS_DIV (1)
#endif #endif
#if CONFIG_USE_CLOCK_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) #define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#elif CONFIG_USE_CLOCK_HSE #elif CONFIG_USE_CLOCK_HSE

48
cpu/stm32/stmclk/stmclk_gx.c
View File

@ -37,7 +37,6 @@
#define PLL_R_MAX (8) #define PLL_R_MAX (8)
#endif #endif
#if CONFIG_USE_CLOCK_PLL
#if (CONFIG_CLOCK_PLL_M < PLL_M_MIN || CONFIG_CLOCK_PLL_M > PLL_M_MAX) #if (CONFIG_CLOCK_PLL_M < PLL_M_MIN || CONFIG_CLOCK_PLL_M > PLL_M_MAX)
#error "PLL configuration: PLL M value is out of range" #error "PLL configuration: PLL M value is out of range"
#endif #endif
@ -66,14 +65,11 @@
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#endif #endif
#endif /* CONFIG_USE_CLOCK_PLL */
#if defined(CPU_FAM_STM32G0) #if defined(CPU_FAM_STM32G0)
#define RCC_CFGR_SW_HSI (0) #define RCC_CFGR_SW_HSI (0)
#define RCC_CFGR_SW_HSE (RCC_CFGR_SW_0) #define RCC_CFGR_SW_HSE (RCC_CFGR_SW_0)
#define RCC_CFGR_SW_PLL (RCC_CFGR_SW_1) #define RCC_CFGR_SW_PLL (RCC_CFGR_SW_1)
#if CONFIG_USE_CLOCK_HSI
#if CONFIG_CLOCK_HSISYS_DIV == 1 #if CONFIG_CLOCK_HSISYS_DIV == 1
#define CLOCK_HSI_DIV (0) #define CLOCK_HSI_DIV (0)
#elif CONFIG_CLOCK_HSISYS_DIV == 2 #elif CONFIG_CLOCK_HSISYS_DIV == 2
@ -91,7 +87,6 @@
#elif CONFIG_CLOCK_HSISYS_DIV == 128 #elif CONFIG_CLOCK_HSISYS_DIV == 128
#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) #define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
#endif #endif
#endif /* CONFIG_USE_CLOCK_HSI */
#define CLOCK_AHB_DIV (0) #define CLOCK_AHB_DIV (0)
@ -195,12 +190,15 @@ void stmclk_init_sysclk(void)
stmclk_enable_lfclk(); stmclk_enable_lfclk();
#endif #endif
#if CONFIG_USE_CLOCK_HSI && defined(CPU_FAM_STM32G0) #if defined(CPU_FAM_STM32G0)
if (CONFIG_USE_CLOCK_HSI && CONFIG_CLOCK_HSISYS_DIV != 1) {
/* configure HSISYS divider, only available on G0 */ /* configure HSISYS divider, only available on G0 */
RCC->CR |= CLOCK_HSI_DIV; RCC->CR |= CLOCK_HSI_DIV;
while (!(RCC->CR & RCC_CR_HSIRDY)) {} while (!(RCC->CR & RCC_CR_HSIRDY)) {}
}
#endif
#elif CONFIG_USE_CLOCK_HSE if (CONFIG_USE_CLOCK_HSE) {
/* if configured, we need to enable the HSE clock now */ /* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {} while (!(RCC->CR & RCC_CR_HSERDY)) {}
@ -211,53 +209,59 @@ void stmclk_init_sysclk(void)
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV); RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
#endif #endif
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {} while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
}
#elif CONFIG_USE_CLOCK_PLL else if (CONFIG_USE_CLOCK_PLL) {
#if CONFIG_BOARD_HAS_HSE if (CONFIG_BOARD_HAS_HSE) {
/* if configured, we need to enable the HSE clock now */ /* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {} while (!(RCC->CR & RCC_CR_HSERDY)) {}
#endif }
/* now we can safely configure and start the PLL */ /* now we can safely configure and start the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN); RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {} while (!(RCC->CR & RCC_CR_PLLRDY)) {}
#if CLOCK_AHB > MHZ(80) #if defined(CPU_FAM_STM32G4)
if (CLOCK_AHB > MHZ(80)) {
/* Divide HCLK by before enabling the PLL */ /* Divide HCLK by before enabling the PLL */
RCC->CFGR |= RCC_CFGR_HPRE_DIV2; RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
}
#endif #endif
/* now that the PLL is running, we use it as system clock */ /* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL; RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
#if CLOCK_AHB > MHZ(80) #if defined(CPU_FAM_STM32G4)
if (CLOCK_AHB > MHZ(80)) {
/* Wait 1us before switching back to full speed */ /* Wait 1us before switching back to full speed */
/* Use volatile to prevent the compiler from optimizing the loop */ /* Use volatile to prevent the compiler from optimizing the loop */
volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1); volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
while (count--) {} while (count--) {}
RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2; RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
}
#endif #endif
}
#endif
stmclk_disable_hsi(); stmclk_disable_hsi();
irq_restore(is); irq_restore(is);
#ifdef MODULE_PERIPH_HWRNG #if defined(CPU_FAM_STM32G4)
if (IS_USED(MODULE_PERIPH_HWRNG)) {
/* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */ /* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
RCC->CRRCR |= RCC_CRRCR_HSI48ON; RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {} while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
#endif }
#ifdef MODULE_PERIPH_RTT if (IS_USED(MODULE_PERIPH_RTT)) {
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing /* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
the clock, this is particularly useful after waking up from deep sleep */ the clock, this is particularly useful after waking up from deep sleep */
#if CLOCK_LSE if (CONFIG_BOARD_HAS_LSE) {
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1; RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
#else }
else {
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0; RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
#endif /* CLOCK_LSE */ }
#endif /* MODULE_PERIPH_RTT */ }
#endif
} }