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stm32f1/i2c: remove duplicated code

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This commit is contained in:
Victor Arino 2016-02-03 13:55:32 +01:00
parent be3279f9bc
commit da5b03df5d
1 changed files with 36 additions and 72 deletions
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84
cpu/stm32f1/periph/i2c.c
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@ -180,7 +180,6 @@ int i2c_read_byte(i2c_t dev, uint8_t address, char *data)
int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length) int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length)
{ {
unsigned int state;
int i = 0; int i = 0;
I2C_TypeDef *i2c; I2C_TypeDef *i2c;
@ -194,64 +193,27 @@ int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length)
return -1; return -1;
} }
DEBUG("Send Slave address and wait for ADDR == 1\n");
_start(i2c, address, I2C_FLAG_READ);
DEBUG("Clear ADDR\n");
_clear_addr(i2c);
switch (length) { switch (length) {
case 1: case 1:
DEBUG("Send Slave address and wait for ADDR == 1\n");
_start(i2c, address, I2C_FLAG_READ);
DEBUG("Set ACK = 0\n");
i2c->CR1 &= ~(I2C_CR1_ACK);
DEBUG("Clear ADDR and set STOP = 1\n");
state = disableIRQ();
_clear_addr(i2c);
i2c->CR1 |= (I2C_CR1_STOP);
restoreIRQ(state);
DEBUG("Wait for RXNE == 1\n");
while (!(i2c->SR1 & I2C_SR1_RXNE));
DEBUG("Read received data\n");
*data = (char)i2c->DR;
/* wait until STOP is cleared by hardware */
while (i2c->CR1 & I2C_CR1_STOP);
/* reset ACK to be able to receive new data */
i2c->CR1 |= (I2C_CR1_ACK);
break; break;
case 2:
DEBUG("Send Slave address and wait for ADDR == 1\n");
_start(i2c, address, I2C_FLAG_READ);
DEBUG("Set POS bit\n");
i2c->CR1 |= (I2C_CR1_POS | I2C_CR1_ACK);
DEBUG("Crit block: Clear ADDR bit and clear ACK flag\n");
state = disableIRQ();
_clear_addr(i2c);
i2c->CR1 &= ~(I2C_CR1_ACK);
restoreIRQ(state);
case 2:
DEBUG("Set POS and ACK bit\n");
i2c->CR1 |= (I2C_CR1_POS | I2C_CR1_ACK);
DEBUG("Crit block: clear ACK flag\n");
i2c->CR1 &= ~(I2C_CR1_ACK);
DEBUG("Wait for transfer to be completed\n"); DEBUG("Wait for transfer to be completed\n");
while (!(i2c->SR1 & I2C_SR1_BTF)) ; while (!(i2c->SR1 & I2C_SR1_BTF)) ;
DEBUG("Crit block: set STOP and read first byte\n");
state = disableIRQ();
i2c->CR1 |= (I2C_CR1_STOP);
data[0] = (char)i2c->DR;
restoreIRQ(state);
DEBUG("read second byte\n");
data[1] = (char)i2c->DR;
DEBUG("wait for STOP bit to be cleared again\n");
while (i2c->CR1 & I2C_CR1_STOP);
DEBUG("reset POS = 0 and ACK = 1\n");
i2c->CR1 &= ~(I2C_CR1_POS);
i2c->CR1 |= (I2C_CR1_ACK);
break; break;
default: default:
DEBUG("Send Slave address and wait for ADDR == 1\n");
_start(i2c, address, I2C_FLAG_READ);
_clear_addr(i2c);
i2c->CR1 |= (I2C_CR1_ACK); i2c->CR1 |= (I2C_CR1_ACK);
while (i < (length - 3)) { while (i < (length - 3)) {
@ -264,21 +226,23 @@ int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length)
DEBUG("Reading the last 3 bytes, waiting for BTF flag\n"); DEBUG("Reading the last 3 bytes, waiting for BTF flag\n");
while (!(i2c->SR1 & I2C_SR1_BTF)) ; while (!(i2c->SR1 & I2C_SR1_BTF)) ;
DEBUG("Disable ACK\n"); DEBUG("Read N-3 byte\n");
data[i++] = (char)i2c->DR;
}
DEBUG("Clear ACK\n");
i2c->CR1 &= ~(I2C_CR1_ACK); i2c->CR1 &= ~(I2C_CR1_ACK);
DEBUG("Crit block: set STOP and read N-2 byte\n"); DEBUG("Setting STOP=1\n");
state = disableIRQ();
data[i++] = (char)i2c->DR;
i2c->CR1 |= (I2C_CR1_STOP); i2c->CR1 |= (I2C_CR1_STOP);
restoreIRQ(state);
DEBUG("Read N-1 byte\n");
data[i++] = (char)i2c->DR;
while (i < length) {
DEBUG("Wait for RXNE == 1\n");
while (!(i2c->SR1 & I2C_SR1_RXNE)) ; while (!(i2c->SR1 & I2C_SR1_RXNE)) ;
DEBUG("Read last byte\n");
DEBUG("Read byte\n");
data[i++] = (char)i2c->DR; data[i++] = (char)i2c->DR;
}
DEBUG("wait for STOP bit to be cleared again\n"); DEBUG("wait for STOP bit to be cleared again\n");
while (i2c->CR1 & I2C_CR1_STOP) ; while (i2c->CR1 & I2C_CR1_STOP) ;
@ -286,7 +250,7 @@ int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length)
DEBUG("reset POS = 0 and ACK = 1\n"); DEBUG("reset POS = 0 and ACK = 1\n");
i2c->CR1 &= ~(I2C_CR1_POS); i2c->CR1 &= ~(I2C_CR1_POS);
i2c->CR1 |= (I2C_CR1_ACK); i2c->CR1 |= (I2C_CR1_ACK);
}
return length; return length;
} }