From da89f6ac5fcaf6c39b0c0aa488f05838d093db94 Mon Sep 17 00:00:00 2001 From: Benjamin Valentin Date: Sun, 26 Apr 2020 22:26:01 +0200 Subject: [PATCH] cpu/samd21: don't hard-code number of channels Each TCC can have 8 PWM channels, so don't hard-code 3 channels/TCC. --- cpu/samd21/include/periph_cpu.h | 3 ++- cpu/samd21/periph/pwm.c | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/samd21/include/periph_cpu.h b/cpu/samd21/include/periph_cpu.h index eb36f825db..8c70774a2d 100644 --- a/cpu/samd21/include/periph_cpu.h +++ b/cpu/samd21/include/periph_cpu.h @@ -84,7 +84,8 @@ typedef struct { */ typedef struct { Tcc *dev; /**< TCC device to use */ - pwm_conf_chan_t chan[3]; /**< channel configuration */ + const pwm_conf_chan_t *chan;/**< channel configuration */ + const uint8_t chan_numof; /**< number of channels */ } pwm_conf_t; /** diff --git a/cpu/samd21/periph/pwm.c b/cpu/samd21/periph/pwm.c index d6389c5821..1806df1f13 100644 --- a/cpu/samd21/periph/pwm.c +++ b/cpu/samd21/periph/pwm.c @@ -151,7 +151,7 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res) f_real = (CLOCK_CORECLOCK / (scale * res)); /* configure the used pins */ - for (unsigned i = 0; i < PWM_MAX_CHANNELS; i++) { + for (unsigned i = 0; i < pwm_config[dev].chan_numof; i++) { if (pwm_config[dev].chan[i].pin != GPIO_UNDEF) { gpio_init(pwm_config[dev].chan[i].pin, GPIO_OUT); gpio_init_mux(pwm_config[dev].chan[i].pin, pwm_config[dev].chan[i].mux); @@ -195,12 +195,12 @@ uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res) uint8_t pwm_channels(pwm_t dev) { - return ARRAY_SIZE(pwm_config[dev].chan); + return pwm_config[dev].chan_numof; } void pwm_set(pwm_t dev, uint8_t channel, uint16_t value) { - if ((channel >= PWM_MAX_CHANNELS) || + if ((channel >= pwm_config[dev].chan_numof) || (pwm_config[dev].chan[channel].pin == GPIO_UNDEF)) { return; }