boards/msb-430h: switched to periph/uart driver
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@ -23,6 +23,8 @@
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#include "cpu.h"
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#include "irq.h"
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#include "board.h"
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#include "msp430_stdio.h"
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#include "periph_conf.h"
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#include "kernel_internal.h"
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#include "msp430.h"
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#include "debug.h"
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@ -31,35 +33,6 @@ static volatile uint32_t __msp430_cpu_speed = MSP430_INITIAL_CPU_SPEED;
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void msp430_init_dco(void);
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/*---------------------------------------------------------------------------*/
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static uint8_t calc_umctl(uint16_t br)
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{
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/* from TI slaa049 */
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register uint8_t CMOD = 256 * br - 256 * (br + 1) / 2;
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register uint8_t c = 0;
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register int i = 0;
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register uint8_t a = CMOD;
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a <<= 1;
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do {
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if (a & 0x80) { /* Overflow to integer? */
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a = a - 128 + CMOD; /* Yes, subtract 1.000000 */
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c |= 0x80;
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}
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else {
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a += CMOD; /* No, add fraction */
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}
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if (i == 7) {
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return c;
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}
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i++;
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c >>= 1;
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}
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while (1);
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}
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static void msb_ports_init(void)
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{
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/* Port 1: Free port, for energy saving all outputs are set to zero. */
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@ -79,9 +52,9 @@ static void msb_ports_init(void)
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/* 0 - P2.6 [IN ] - SDC Protect */
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/* 0 - P2.7 [IN ] - SDC Detect */
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P3SEL = 0xC0; /* Port3 Pins 6 & 7 for USART */
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P3OUT = 0x49; /* Port3 Output register: 01001001: 0x49 */
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P3DIR = 0xAB; /* Port3 Direction: 10101011: 0xAB */
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P3SEL = 0x00; /* Port3 Pins 6 & 7 for USART */
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P3OUT = 0x00; /* Port3 Output register: 01001001: 0x49 */
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P3DIR = 0xFF; /* Port3 Direction: 10101011: 0xAB */
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/* 1 - P3.0 */
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/* 1 - P3.1 */
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/* 0 - P3.2 */
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@ -134,21 +107,6 @@ void msp430_set_cpu_speed(uint32_t speed)
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disableIRQ();
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__msp430_cpu_speed = speed;
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msp430_init_dco();
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uint16_t br;
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UCTL1 = SWRST | CHAR; /* 8-bit character */
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UTCTL1 |= SSEL1 | URXSE; /* UCLK = MCLK */
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/* activate */
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U1ME |= UTXE1 | URXE1; /* Enable USART1 TXD/RXD */
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br = (uint16_t)(__msp430_cpu_speed / 115200uL);
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UBR01 = br; /* set baudrate */
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UBR11 = br >> 8;
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UMCTL1 = calc_umctl(br); /* set modulation */
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ME2 |= (UTXE1 | URXE1);
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UCTL1 &= ~SWRST;
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IE2 |= URXIE1;
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//clock_init();
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enableIRQ();
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}
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@ -244,5 +202,8 @@ void board_init(void)
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LED_RED_ON;
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msp430_set_cpu_speed(7372800uL);
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msp430_set_cpu_speed(CLOCK_CORECLOCK);
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/* finally initialize the STDIO */
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msp430_stdio_init();
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}
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@ -1,85 +0,0 @@
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/*
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* Copyright (C) 2014 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards
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* @{
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*/
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/**
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* @file
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* @brief msb-430 common putchar implementation
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*
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#include <stdio.h>
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#include "board.h"
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#include "kernel.h"
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#include "board_uart0.h"
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#define UART1_TX TXBUF1
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#define UART1_WAIT_TXDONE() while( (UTCTL1 & TXEPT) == 0 ) { _NOP(); }
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int getchar(void)
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{
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#ifdef MODULE_UART0
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return uart0_readc();
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#else
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return U1RXBUF;
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#endif
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}
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int putchar(int c)
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{
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UART1_TX = c;
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UART1_WAIT_TXDONE();
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if (c == 10) {
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UART1_WAIT_TXDONE();
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}
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return c;
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}
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void usart0irq(void);
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/**
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* \brief the interrupt function
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*/
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void __attribute__((interrupt(USART1RX_VECTOR))) usart0irq(void)
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{
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U1TCTL &= ~URXSE; /* Clear the URXS signal */
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U1TCTL |= URXSE; /* Re-enable URXS - needed here?*/
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/* Check status register for receive errors. */
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if(U1RCTL & RXERR) {
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if (U1RCTL & FE) {
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puts("rx framing error");
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}
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if (U1RCTL & OE) {
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puts("rx overrun error");
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}
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if (U1RCTL & PE) {
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puts("rx parity error");
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}
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if (U1RCTL & BRK) {
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puts("rx break error");
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}
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/* Clear error flags by forcing a dummy read. */
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volatile int c = U1RXBUF;
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(void) c;
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}
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#ifdef MODULE_UART0
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else if (uart0_handler_pid != KERNEL_PID_UNDEF) {
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volatile int c = U1RXBUF;
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uart0_handle_incoming(c);
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uart0_notify_thread();
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}
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#endif
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}
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@ -46,6 +46,15 @@ extern "C" {
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*/
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#define HW_TIMER (0)
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/**
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* @brief Standard input/output device configuration
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* @{
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*/
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#define STDIO (0)
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#define STDIO_BAUDRATE (115200U)
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#define STDIO_RX_BUFSIZE (64U)
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/** @} */
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//MSB430 core
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#define MSP430_INITIAL_CPU_SPEED 7372800uL
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#define F_CPU MSP430_INITIAL_CPU_SPEED
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@ -25,6 +25,16 @@
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extern "C" {
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#endif
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/**
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* @brief Clock configuration
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*
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* @todo Move all clock configuration code here from the board.h
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*/
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#define CLOCK_CORECLOCK (7372800U)
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#define CLOCK_CMCLK CLOCK_CORECLOCK /* no divider programmed */
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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@ -35,6 +45,27 @@ extern "C" {
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#define TIMER_ISR_CCX (TIMERA1_VECTOR)
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN (1U)
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#define UART_DEV (USART_1)
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#define UART_IE (SFR->IE2)
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#define UART_IF (SFR->IFG2)
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#define UART_IE_RX_BIT (1 << 4)
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#define UART_IE_TX_BIT (1 << 5)
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#define UART_ME (SFR->ME2)
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#define UART_ME_BITS (0x30)
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#define UART_PORT (PORT_3)
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#define UART_RX_PIN (1 << 6)
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#define UART_TX_PIN (1 << 7)
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#define UART_RX_ISR (USART1RX_VECTOR)
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#define UART_TX_ISR (USART1TX_VECTOR)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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