From db2fa33660e064b9cb3ad2af4b71bd477b5ecf0d Mon Sep 17 00:00:00 2001 From: Benjamin Valentin Date: Wed, 30 Oct 2019 19:04:03 +0100 Subject: [PATCH] sam0_common: rtc: use GCLK4 on SAMD21 The RTC expects to be clocked from a 1kHz source. Previously it would re-configure GCLK2 from 32kHz to 1kHz when used. Since GCLK2 is also used by EIC, this would break external interrupts in strange and unexpected ways. Dedicate a 1kHz clock to it to avoid the damage. --- cpu/sam0_common/periph/rtc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/cpu/sam0_common/periph/rtc.c b/cpu/sam0_common/periph/rtc.c index 7ab2a7a35f..d5d39594c1 100644 --- a/cpu/sam0_common/periph/rtc.c +++ b/cpu/sam0_common/periph/rtc.c @@ -65,10 +65,8 @@ static inline void _rtc_set_enabled(bool on) #ifdef CPU_SAMD21 static void _rtc_clock_setup(void) { - /* Setup clock GCLK2 with OSC32K divided by 32 */ - GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(4); - GCLK->GENCTRL.bit.DIVSEL = 1; - GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(2) | GCLK_CLKCTRL_ID_RTC; + /* Use 1024 Hz GCLK4 */ + GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(4) | GCLK_CLKCTRL_ID_RTC; while (GCLK->STATUS.bit.SYNCBUSY) {} } #else