From 4c1b65c67038f5f6eb69253c006813c843c465f8 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 17:11:13 +0200 Subject: [PATCH 01/13] nucleo-f401re: Add DMA config for SPI --- boards/nucleo-f401re/Makefile.features | 1 + boards/nucleo-f401re/include/periph_conf.h | 110 ++++++++++++++------- 2 files changed, 78 insertions(+), 33 deletions(-) diff --git a/boards/nucleo-f401re/Makefile.features b/boards/nucleo-f401re/Makefile.features index d97b3ffc8d..3716648308 100644 --- a/boards/nucleo-f401re/Makefile.features +++ b/boards/nucleo-f401re/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f401re # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f401re/include/periph_conf.h b/boards/nucleo-f401re/include/periph_conf.h index 4c46f9210c..93c89da443 100644 --- a/boards/nucleo-f401re/include/periph_conf.h +++ b/boards/nucleo-f401re/include/periph_conf.h @@ -28,6 +28,32 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ + { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */ + { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */ + { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */ + { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 +#define DMA_2_ISR isr_dma1_stream4 +#define DMA_3_ISR isr_dma1_stream3 +#define DMA_4_ISR isr_dma1_stream5 +#define DMA_5_ISR isr_dma1_stream0 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -163,43 +189,61 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif }, { - .dev = SPI2, - .mosi_pin = GPIO_PIN(PORT_B, 15), - .miso_pin = GPIO_PIN(PORT_B, 14), - .sclk_pin = GPIO_PIN(PORT_B, 13), - .cs_pin = GPIO_PIN(PORT_B, 12), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB1ENR_SPI2EN, - .apbbus = APB1 + .dev = SPI2, + .mosi_pin = GPIO_PIN(PORT_B, 15), + .miso_pin = GPIO_PIN(PORT_B, 14), + .sclk_pin = GPIO_PIN(PORT_B, 13), + .cs_pin = GPIO_PIN(PORT_B, 12), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB1ENR_SPI2EN, + .apbbus = APB1, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 2, + .tx_dma_chan = 0, + .rx_dma = 3, + .rx_dma_chan = 0, +#endif }, { - .dev = SPI3, - .mosi_pin = GPIO_PIN(PORT_C, 12), - .miso_pin = GPIO_PIN(PORT_C, 11), - .sclk_pin = GPIO_PIN(PORT_C, 10), - .cs_pin = GPIO_UNDEF, - .mosi_af = GPIO_AF6, - .miso_af = GPIO_AF6, - .sclk_af = GPIO_AF6, - .cs_af = GPIO_AF6, - .rccmask = RCC_APB1ENR_SPI3EN, - .apbbus = APB1 + .dev = SPI3, + .mosi_pin = GPIO_PIN(PORT_C, 12), + .miso_pin = GPIO_PIN(PORT_C, 11), + .sclk_pin = GPIO_PIN(PORT_C, 10), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF6, + .miso_af = GPIO_AF6, + .sclk_af = GPIO_AF6, + .cs_af = GPIO_AF6, + .rccmask = RCC_APB1ENR_SPI3EN, + .apbbus = APB1, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 4, + .tx_dma_chan = 0, + .rx_dma = 5, + .rx_dma_chan = 0, +#endif } }; From 09831a40a420fff44d5a6cc616998df0a69c6048 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 17:14:01 +0200 Subject: [PATCH 02/13] nucleo-f410rb: Add DMA config for SPI --- boards/nucleo-f410rb/Makefile.features | 1 + boards/nucleo-f410rb/include/periph_conf.h | 46 ++++++++++++++++------ 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/nucleo-f410rb/Makefile.features b/boards/nucleo-f410rb/Makefile.features index cc91cd2a6f..9902c48990 100644 --- a/boards/nucleo-f410rb/Makefile.features +++ b/boards/nucleo-f410rb/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f410rb # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_spi diff --git a/boards/nucleo-f410rb/include/periph_conf.h b/boards/nucleo-f410rb/include/periph_conf.h index fe6eab6f52..cfce33cfce 100644 --- a/boards/nucleo-f410rb/include/periph_conf.h +++ b/boards/nucleo-f410rb/include/periph_conf.h @@ -28,6 +28,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -112,17 +130,23 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif } }; From 1f8bdb73e3ccf556b6f0d9207227348ca1c849c0 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 17:16:16 +0200 Subject: [PATCH 03/13] nucleo-f411re: Add DMA config for SPI --- boards/nucleo-f411re/Makefile.features | 1 + boards/nucleo-f411re/include/periph_conf.h | 46 ++++++++++++++++------ 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/nucleo-f411re/Makefile.features b/boards/nucleo-f411re/Makefile.features index 0858936cca..00d546d441 100644 --- a/boards/nucleo-f411re/Makefile.features +++ b/boards/nucleo-f411re/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f411re # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f411re/include/periph_conf.h b/boards/nucleo-f411re/include/periph_conf.h index ca842ec0fd..9c4b8db0b5 100644 --- a/boards/nucleo-f411re/include/periph_conf.h +++ b/boards/nucleo-f411re/include/periph_conf.h @@ -28,6 +28,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -141,17 +159,23 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif } }; From 70e3bf84b04c752a31f9095cc0a13b28a75e75cb Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:06:26 +0200 Subject: [PATCH 04/13] msbiot: Add DMA config for SPI --- boards/msbiot/Makefile.features | 1 + boards/msbiot/include/periph_conf.h | 46 ++++++++++++++++++++++------- 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/msbiot/Makefile.features b/boards/msbiot/Makefile.features index cdb7339c34..952e45858d 100644 --- a/boards/msbiot/Makefile.features +++ b/boards/msbiot/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f415rg # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_dac FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm diff --git a/boards/msbiot/include/periph_conf.h b/boards/msbiot/include/periph_conf.h index 154a574797..b77a236c7c 100644 --- a/boards/msbiot/include/periph_conf.h +++ b/boards/msbiot/include/periph_conf.h @@ -27,6 +27,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name Timer configuration * @{ @@ -165,17 +183,23 @@ static const uart_conf_t uart_config[] = { */ static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif } }; From 61830480e99a414d0a292633d73237071e19e405 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:08:08 +0200 Subject: [PATCH 05/13] nucleo-f412zg: add DMA config for SPI --- boards/nucleo-f412zg/Makefile.features | 1 + boards/nucleo-f412zg/include/periph_conf.h | 46 ++++++++++++++++------ 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/nucleo-f412zg/Makefile.features b/boards/nucleo-f412zg/Makefile.features index 20126aaf30..e1b1b6cd0c 100644 --- a/boards/nucleo-f412zg/Makefile.features +++ b/boards/nucleo-f412zg/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f412zg # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f412zg/include/periph_conf.h b/boards/nucleo-f412zg/include/periph_conf.h index de32583fb9..b3e17a0ae3 100644 --- a/boards/nucleo-f412zg/include/periph_conf.h +++ b/boards/nucleo-f412zg/include/periph_conf.h @@ -31,6 +31,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -143,17 +161,23 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif } }; From 2028a97db6a26040706a912dbda1c03ff7936092 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:09:10 +0200 Subject: [PATCH 06/13] nucleo-f413zh: Add DMA config for SPI --- boards/nucleo-f413zh/Makefile.features | 1 + boards/nucleo-f413zh/include/periph_conf.h | 44 ++++++++++------------ 2 files changed, 20 insertions(+), 25 deletions(-) diff --git a/boards/nucleo-f413zh/Makefile.features b/boards/nucleo-f413zh/Makefile.features index 73b48b6501..25971a7432 100644 --- a/boards/nucleo-f413zh/Makefile.features +++ b/boards/nucleo-f413zh/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f413zh # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_can FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c diff --git a/boards/nucleo-f413zh/include/periph_conf.h b/boards/nucleo-f413zh/include/periph_conf.h index 3d20db74b2..d38885ca12 100644 --- a/boards/nucleo-f413zh/include/periph_conf.h +++ b/boards/nucleo-f413zh/include/periph_conf.h @@ -38,18 +38,12 @@ extern "C" { */ #ifdef MODULE_PERIPH_DMA static const dma_conf_t dma_config[] = { - { .stream = 4 }, - { .stream = 14 }, - { .stream = 6 }, - { .stream = 10 }, - { .stream = 8 }, + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ }; -#define DMA_0_ISR isr_dma1_stream4 -#define DMA_1_ISR isr_dma2_stream6 -#define DMA_2_ISR isr_dma1_stream6 -#define DMA_3_ISR isr_dma2_stream2 -#define DMA_4_ISR isr_dma2_stream0 +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 #define DMA_NUMOF ARRAY_SIZE(dma_config) #endif @@ -167,22 +161,22 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2, + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, #ifdef MODULE_PERIPH_DMA - .tx_dma = 3, - .tx_dma_chan = 2, - .rx_dma = 4, - .rx_dma_chan = 3, + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, #endif } }; From 5c63c7ccb68f34e567f7eadc6b91fed7b607dd91 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:09:31 +0200 Subject: [PATCH 07/13] nucleo-f429zi: Add DMA config for SPI --- boards/nucleo-f429zi/Makefile.features | 1 + boards/nucleo-f429zi/include/periph_conf.h | 46 ++++++++++++++++------ 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/nucleo-f429zi/Makefile.features b/boards/nucleo-f429zi/Makefile.features index 536c6eaf8f..28679cd92d 100644 --- a/boards/nucleo-f429zi/Makefile.features +++ b/boards/nucleo-f429zi/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f429zi # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f429zi/include/periph_conf.h b/boards/nucleo-f429zi/include/periph_conf.h index 6617c16e64..336d5b8dff 100644 --- a/boards/nucleo-f429zi/include/periph_conf.h +++ b/boards/nucleo-f429zi/include/periph_conf.h @@ -30,6 +30,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -122,17 +140,23 @@ static const pwm_conf_t pwm_config[] = { */ static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_UNDEF, - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif } }; From 5cee9c61e1212b330f8f8ecdadb69fef9c774933 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:09:55 +0200 Subject: [PATCH 08/13] nucleo-f446re: Add DMA config for SPI --- boards/nucleo-f446re/Makefile.features | 1 + boards/nucleo-f446re/include/periph_conf.h | 110 ++++++++++++++------- 2 files changed, 78 insertions(+), 33 deletions(-) diff --git a/boards/nucleo-f446re/Makefile.features b/boards/nucleo-f446re/Makefile.features index f7ffa52d9d..b3de0f8635 100644 --- a/boards/nucleo-f446re/Makefile.features +++ b/boards/nucleo-f446re/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f446re # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f446re/include/periph_conf.h b/boards/nucleo-f446re/include/periph_conf.h index e62d6bad50..af09454ecc 100644 --- a/boards/nucleo-f446re/include/periph_conf.h +++ b/boards/nucleo-f446re/include/periph_conf.h @@ -29,6 +29,32 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ + { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */ + { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */ + { .stream = 5 }, /* DMA1 Stream 5 - SPI3_TX */ + { .stream = 0 }, /* DMA1 Stream 0 - SPI3_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 +#define DMA_2_ISR isr_dma1_stream4 +#define DMA_3_ISR isr_dma1_stream3 +#define DMA_4_ISR isr_dma1_stream5 +#define DMA_5_ISR isr_dma1_stream0 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -157,43 +183,61 @@ static const qdec_conf_t qdec_config[] = { */ static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif }, { - .dev = SPI2, - .mosi_pin = GPIO_PIN(PORT_B, 15), - .miso_pin = GPIO_PIN(PORT_B, 14), - .sclk_pin = GPIO_PIN(PORT_B, 13), - .cs_pin = GPIO_PIN(PORT_B, 12), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB1ENR_SPI2EN, - .apbbus = APB1 + .dev = SPI2, + .mosi_pin = GPIO_PIN(PORT_B, 15), + .miso_pin = GPIO_PIN(PORT_B, 14), + .sclk_pin = GPIO_PIN(PORT_B, 13), + .cs_pin = GPIO_PIN(PORT_B, 12), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB1ENR_SPI2EN, + .apbbus = APB1, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 2, + .tx_dma_chan = 0, + .rx_dma = 3, + .rx_dma_chan = 0, +#endif }, { - .dev = SPI3, - .mosi_pin = GPIO_PIN(PORT_C, 12), - .miso_pin = GPIO_PIN(PORT_C, 11), - .sclk_pin = GPIO_PIN(PORT_C, 10), - .cs_pin = GPIO_UNDEF, - .mosi_af = GPIO_AF6, - .miso_af = GPIO_AF6, - .sclk_af = GPIO_AF6, - .cs_af = GPIO_AF6, - .rccmask = RCC_APB1ENR_SPI3EN, - .apbbus = APB1 + .dev = SPI3, + .mosi_pin = GPIO_PIN(PORT_C, 12), + .miso_pin = GPIO_PIN(PORT_C, 11), + .sclk_pin = GPIO_PIN(PORT_C, 10), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF6, + .miso_af = GPIO_AF6, + .sclk_af = GPIO_AF6, + .cs_af = GPIO_AF6, + .rccmask = RCC_APB1ENR_SPI3EN, + .apbbus = APB1, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 4, + .tx_dma_chan = 0, + .rx_dma = 5, + .rx_dma_chan = 0, +#endif } }; From 08123b9736e77ffaa8e361bdae76d93f0670bf6b Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:10:14 +0200 Subject: [PATCH 09/13] nucleo-f446ze: Add DMA config for SPI --- boards/nucleo-f446ze/Makefile.features | 1 + boards/nucleo-f446ze/include/periph_conf.h | 28 ++++++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/boards/nucleo-f446ze/Makefile.features b/boards/nucleo-f446ze/Makefile.features index d9f6d7e060..5324f7746a 100644 --- a/boards/nucleo-f446ze/Makefile.features +++ b/boards/nucleo-f446ze/Makefile.features @@ -2,6 +2,7 @@ CPU = stm32f4 CPU_MODEL = stm32f446ze # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-f446ze/include/periph_conf.h b/boards/nucleo-f446ze/include/periph_conf.h index 169d7b2f1d..06390d2835 100644 --- a/boards/nucleo-f446ze/include/periph_conf.h +++ b/boards/nucleo-f446ze/include/periph_conf.h @@ -30,6 +30,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -132,8 +150,14 @@ static const spi_conf_t spi_config[] = { .sclk_af = GPIO_AF5, .cs_af = GPIO_AF5, .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 - } + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif + }, }; #define SPI_NUMOF ARRAY_SIZE(spi_config) From d0f26ac877e931a8596794d450c91401f63587e4 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:10:41 +0200 Subject: [PATCH 10/13] pyboard: Add DMA config for SPI --- boards/pyboard/Makefile.features | 1 + boards/pyboard/include/periph_conf.h | 48 +++++++++++++++++++--------- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/boards/pyboard/Makefile.features b/boards/pyboard/Makefile.features index 30544feeb6..9261834d1b 100644 --- a/boards/pyboard/Makefile.features +++ b/boards/pyboard/Makefile.features @@ -2,6 +2,7 @@ CPU = stm32f4 CPU_MODEL = stm32f405rg # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_spi diff --git a/boards/pyboard/include/periph_conf.h b/boards/pyboard/include/periph_conf.h index 104994b37a..f67ab4b429 100644 --- a/boards/pyboard/include/periph_conf.h +++ b/boards/pyboard/include/periph_conf.h @@ -59,6 +59,24 @@ extern "C" { #define CLOCK_PLL_Q (7) /** @} */ +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name Timer configuration * @{ @@ -130,22 +148,22 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_UNDEF, - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2, + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, #ifdef MODULE_PERIPH_DMA - .tx_dma = 1, - .tx_dma_chan = 1, - .rx_dma = 0, - .rx_dma_chan = 1, + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, #endif } }; From 86ae376a8a2682dd3ac1a04df77125019d3fbb3b Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:11:04 +0200 Subject: [PATCH 11/13] stm32f429i-disc1: Add DMA config for SPI --- boards/stm32f429i-disc1/Makefile.features | 1 + boards/stm32f429i-disc1/include/periph_conf.h | 46 ++++++++++++++----- 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/stm32f429i-disc1/Makefile.features b/boards/stm32f429i-disc1/Makefile.features index a7d89bbd78..5edbca9846 100644 --- a/boards/stm32f429i-disc1/Makefile.features +++ b/boards/stm32f429i-disc1/Makefile.features @@ -2,6 +2,7 @@ CPU = stm32f4 CPU_MODEL = stm32f429zi # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += periph_timer diff --git a/boards/stm32f429i-disc1/include/periph_conf.h b/boards/stm32f429i-disc1/include/periph_conf.h index a34a7c3f24..7aab691760 100644 --- a/boards/stm32f429i-disc1/include/periph_conf.h +++ b/boards/stm32f429i-disc1/include/periph_conf.h @@ -29,6 +29,24 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 14 }, /* DMA2 Stream 6 - SPI5_TX */ + { .stream = 13 }, /* DMA2 Stream 5 - SPI5_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream6 +#define DMA_1_ISR isr_dma2_stream5 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -64,17 +82,23 @@ static const uart_conf_t uart_config[] = { */ static const spi_conf_t spi_config[] = { { - .dev = SPI5, - .mosi_pin = GPIO_PIN(PORT_F, 9), - .miso_pin = GPIO_PIN(PORT_F, 8), - .sclk_pin = GPIO_PIN(PORT_F, 7), - .cs_pin = GPIO_UNDEF, - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI5EN, - .apbbus = APB2 + .dev = SPI5, + .mosi_pin = GPIO_PIN(PORT_F, 9), + .miso_pin = GPIO_PIN(PORT_F, 8), + .sclk_pin = GPIO_PIN(PORT_F, 7), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI5EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 7, + .rx_dma = 1, + .rx_dma_chan = 7, +#endif } }; From 859f0d9c03844a0875b8f9180a7d41eb998c1fbf Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:11:33 +0200 Subject: [PATCH 12/13] stm32f4discovery: Add DMA config for SPI --- boards/stm32f4discovery/Makefile.features | 1 + boards/stm32f4discovery/include/periph_conf.h | 80 +++++++++++++------ 2 files changed, 58 insertions(+), 23 deletions(-) diff --git a/boards/stm32f4discovery/Makefile.features b/boards/stm32f4discovery/Makefile.features index 568c013ad4..4993ae3f65 100644 --- a/boards/stm32f4discovery/Makefile.features +++ b/boards/stm32f4discovery/Makefile.features @@ -4,6 +4,7 @@ CPU_MODEL = stm32f407vg # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc FEATURES_PROVIDED += periph_dac +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/stm32f4discovery/include/periph_conf.h b/boards/stm32f4discovery/include/periph_conf.h index 912c54c9df..8b827515d4 100644 --- a/boards/stm32f4discovery/include/periph_conf.h +++ b/boards/stm32f4discovery/include/periph_conf.h @@ -29,6 +29,28 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ + { .stream = 4 }, /* DMA1 Stream 4 - SPI2_TX */ + { .stream = 3 }, /* DMA1 Stream 3 - SPI2_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream3 +#define DMA_1_ISR isr_dma2_stream2 +#define DMA_2_ISR isr_dma1_stream4 +#define DMA_3_ISR isr_dma1_stream3 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name Timer configuration * @{ @@ -162,31 +184,43 @@ static const pwm_conf_t pwm_config[] = { */ static const spi_conf_t spi_config[] = { { - .dev = SPI1, - .mosi_pin = GPIO_PIN(PORT_A, 7), - .miso_pin = GPIO_PIN(PORT_A, 6), - .sclk_pin = GPIO_PIN(PORT_A, 5), - .cs_pin = GPIO_PIN(PORT_A, 4), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI1EN, - .apbbus = APB2 + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_PIN(PORT_A, 4), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 3, + .rx_dma = 1, + .rx_dma_chan = 3, +#endif }, { - .dev = SPI2, - .mosi_pin = GPIO_PIN(PORT_B, 15), - .miso_pin = GPIO_PIN(PORT_B, 14), - .sclk_pin = GPIO_PIN(PORT_B, 13), - .cs_pin = GPIO_PIN(PORT_B, 12), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB1ENR_SPI2EN, - .apbbus = APB1 - } + .dev = SPI2, + .mosi_pin = GPIO_PIN(PORT_B, 15), + .miso_pin = GPIO_PIN(PORT_B, 14), + .sclk_pin = GPIO_PIN(PORT_B, 13), + .cs_pin = GPIO_PIN(PORT_B, 12), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB1ENR_SPI2EN, + .apbbus = APB1, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 2, + .tx_dma_chan = 0, + .rx_dma = 3, + .rx_dma_chan = 0, +#endif + }, }; #define SPI_NUMOF ARRAY_SIZE(spi_config) From 709f576d4abc2f399b19a4785f8ba59ace0c60c8 Mon Sep 17 00:00:00 2001 From: Koen Zandberg Date: Fri, 15 May 2020 23:11:57 +0200 Subject: [PATCH 13/13] ublox-c030-u201: Add DMA config for SPI --- boards/ublox-c030-u201/Makefile.features | 1 + boards/ublox-c030-u201/include/periph_conf.h | 46 +++++++++++++++----- 2 files changed, 36 insertions(+), 11 deletions(-) diff --git a/boards/ublox-c030-u201/Makefile.features b/boards/ublox-c030-u201/Makefile.features index ef62dcde7b..80a868b081 100644 --- a/boards/ublox-c030-u201/Makefile.features +++ b/boards/ublox-c030-u201/Makefile.features @@ -3,6 +3,7 @@ CPU_MODEL = stm32f437vg # Put defined MCU peripherals here (in alphabetical order) FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_dma FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_spi diff --git a/boards/ublox-c030-u201/include/periph_conf.h b/boards/ublox-c030-u201/include/periph_conf.h index 764cbafe67..cabd06b298 100644 --- a/boards/ublox-c030-u201/include/periph_conf.h +++ b/boards/ublox-c030-u201/include/periph_conf.h @@ -57,6 +57,24 @@ extern "C" { #define CLOCK_PLL_Q (7) /** @} */ +/** + * @name DMA streams configuration + * @{ + */ +#ifdef MODULE_PERIPH_DMA +static const dma_conf_t dma_config[] = { + { .stream = 9 }, /* DMA2 Stream 1 - SPI4_TX */ + { .stream = 8 }, /* DMA2 Stream 0 - SPI4_RX */ +}; + +#define DMA_0_ISR isr_dma2_stream1 +#define DMA_1_ISR isr_dma2_stream0 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) + +#endif /* MODULE_PERIPH_DMA */ +/** @} */ + /** * @name UART configuration * @{ @@ -178,17 +196,23 @@ static const uint8_t spi_divtable[2][5] = { static const spi_conf_t spi_config[] = { { - .dev = SPI4, - .mosi_pin = GPIO_PIN(PORT_E, 6), - .miso_pin = GPIO_PIN(PORT_E, 5), - .sclk_pin = GPIO_PIN(PORT_E, 2), - .cs_pin = GPIO_PIN(PORT_E, 11), - .mosi_af = GPIO_AF5, - .miso_af = GPIO_AF5, - .sclk_af = GPIO_AF5, - .cs_af = GPIO_AF5, - .rccmask = RCC_APB2ENR_SPI4EN, - .apbbus = APB2 + .dev = SPI4, + .mosi_pin = GPIO_PIN(PORT_E, 6), + .miso_pin = GPIO_PIN(PORT_E, 5), + .sclk_pin = GPIO_PIN(PORT_E, 2), + .cs_pin = GPIO_PIN(PORT_E, 11), + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI4EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 0, + .tx_dma_chan = 4, + .rx_dma = 1, + .rx_dma_chan = 4, +#endif }, };