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Merge pull request #7051 from OTAkeys/pr/stm32f7discovery

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boards: add stm32f769 discovery
This commit is contained in:
Alexandre Abadie 2017-05-17 19:24:03 +02:00 committed by GitHub
commit dce3015e0c
14 changed files with 22188 additions and 4 deletions
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3
boards/stm32f7discovery/Makefile Normal file
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@ -0,0 +1,3 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

3
boards/stm32f7discovery/Makefile.dep Normal file
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@ -0,0 +1,3 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif

14
boards/stm32f7discovery/Makefile.features Normal file
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@ -0,0 +1,14 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Various other features (if any)
#FEATURES_PROVIDED += cpp
#FEATURES_PROVIDED += arduino
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m7

13
boards/stm32f7discovery/Makefile.include Normal file
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@ -0,0 +1,13 @@
# define the cpu used by the stm32f769-discovery board
export CPU = stm32f7
export CPU_MODEL = stm32f769ni
# set default port depending on operating system
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# this board uses openocd
include $(RIOTMAKE)/tools/openocd.inc.mk

36
boards/stm32f7discovery/board.c Normal file
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@ -0,0 +1,36 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup boards_stm32f7discovery
* @{
*
* @file
* @brief Board specific implementations for the STM32F7Discovery evaluation board
*
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
#include <stdio.h>
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the boards LEDs */
gpio_init(LED0_PIN, GPIO_OUT);
gpio_init(LED1_PIN, GPIO_OUT);
gpio_init(LED2_PIN, GPIO_OUT);
gpio_init(LED3_PIN, GPIO_OUT);
}

5
boards/stm32f7discovery/dist/openocd.cfg vendored Normal file
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@ -0,0 +1,5 @@
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32f7x.cfg]

81
boards/stm32f7discovery/include/board.h Normal file
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@ -0,0 +1,81 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_stm32f7discovery stm32f769 Discovery board
* @ingroup boards
* @brief Board specific files for the stm32f769 Discovery board
* @{
*
* @file
* @brief Board specific definitions for the stm32f769 Discovery board
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Macros for controlling the on-board LEDs.
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_J, 13)
#define LED1_PIN GPIO_PIN(PORT_J, 5)
#define LED2_PIN GPIO_PIN(PORT_A, 12)
#define LED3_PIN GPIO_PIN(PORT_D, 4)
#define LED0_PORT GPIOJ
#define LED1_PORT GPIOJ
#define LED2_PORT GPIOA
#define LED3_PORT GPIOD
#define LED0_MASK (1 << 13)
#define LED1_MASK (1 << 5)
#define LED2_MASK (1 << 12)
#define LED3_MASK (1 << 4)
#define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
#define LED1_ON (LED1_PORT->BSRR = LED1_MASK)
#define LED1_OFF (LED1_PORT->BSRR = (LED1_MASK << 16))
#define LED1_TOGGLE (LED1_PORT->ODR ^= LED1_MASK)
#define LED2_ON (LED2_PORT->BSRR = LED2_MASK)
#define LED2_OFF (LED2_PORT->BSRR = (LED2_MASK << 16))
#define LED2_TOGGLE (LED2_PORT->ODR ^= LED2_MASK)
#define LED3_ON (LED3_PORT->BSRR = LED3_MASK)
#define LED3_OFF (LED3_PORT->BSRR = (LED3_MASK << 16))
#define LED3_TOGGLE (LED3_PORT->ODR ^= LED3_MASK)
/** @} */
/**
* @brief User button
*/
#define BTN_B1_PIN GPIO_PIN(PORT_A, 0)
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

66
boards/stm32f7discovery/include/gpio_params.h Normal file
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@ -0,0 +1,66 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_stm32f7discovery
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD1",
.pin = LED0_PIN,
.mode = GPIO_OUT
},
{
.name = "LD2",
.pin = LED1_PIN,
.mode = GPIO_OUT
},
{
.name = "LD3",
.pin = LED2_PIN,
.mode = GPIO_OUT
},
{
.name = "LD4",
.pin = LED3_PIN,
.mode = GPIO_OUT
},
{
.name = "BTN USER",
.pin = BTN_B1_PIN,
.mode = GPIO_IN
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

122
boards/stm32f7discovery/include/periph_conf.h Normal file
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@ -0,0 +1,122 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_stm32f7discovery
* @{
*
* @file
* @brief Peripheral MCU configuration for the stm32f769discovery6 board
*
* @author Vincent Dupont <vincent@otakeys.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (25000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 216MHz, min: 96MHz, must be multiple of 48MHz */
#define CLOCK_CORECLOCK (216000000U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB2,
.irqn = USART1_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 4,
.dma_chan = 4
#endif
}
};
#define UART_0_ISR (isr_usart1)
#define UART_0_DMA_ISR (isr_dma1_stream4)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

16
cpu/stm32_common/periph/rtc.c
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@ -27,7 +27,7 @@
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L1)
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1)
/* guard file in case no RTC device was specified */
#if RTC_NUMOF
@ -59,7 +59,11 @@ void rtc_init(void)
{
/* Enable write access to RTC registers */
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
#endif
#if defined(CPU_FAM_STM32L1)
if (!(RCC->CSR & RCC_CSR_RTCEN)) {
@ -98,7 +102,11 @@ int rtc_set_time(struct tm *time)
{
/* Enable write access to RTC registers */
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
#endif
/* Unlock RTC write protection */
RTC->WPR = RTC_WRITE_PROTECTION_KEY1;
@ -152,7 +160,11 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
{
/* Enable write access to RTC registers */
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
#endif
/* Unlock RTC write protection */
RTC->WPR = RTC_WRITE_PROTECTION_KEY1;
@ -319,4 +331,4 @@ static uint8_t byte2bcd(uint8_t value)
#endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32L1) */
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) */

8
cpu/stm32f7/include/cpu_conf.h
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@ -23,8 +23,10 @@
#include "cpu_conf_common.h"
#ifdef CPU_MODEL_STM32F746ZG
#if defined(CPU_MODEL_STM32F746ZG)
#include "vendor/stm32f746xx.h"
#elif defined(CPU_MODEL_STM32F769NI)
#include "vendor/stm32f769xx.h"
#endif
#ifdef __cplusplus
@ -36,7 +38,11 @@ extern "C" {
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(CPU_MODEL_STM32F746ZG)
#define CPU_IRQ_NUMOF (98U)
#elif defined(CPU_MODEL_STM32F769NI)
#define CPU_IRQ_NUMOF (110U)
#endif
/** @} */
#ifdef __cplusplus

21765
cpu/stm32f7/include/vendor/stm32f769xx.h vendored Normal file
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30
cpu/stm32f7/ldscripts/stm32f769ni.ld Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2017 OTA keys S.A.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32f7
* @{
*
* @file
* @brief Memory definitions for the STM32F769NI
*
* @author Vincent Dupont <vincent@otakeys.com>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
cpuid (r) : ORIGIN = 0x1ff0f420, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

30
cpu/stm32f7/vectors.c
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@ -126,6 +126,20 @@ WEAK_DEFAULT void isr_cec(void);
WEAK_DEFAULT void isr_i2c4_ev(void);
WEAK_DEFAULT void isr_i2c4_er(void);
WEAK_DEFAULT void isr_spdif_rx(void);
#if defined(CPU_MODEL_STM32F769NI)
WEAK_DEFAULT void isr_dsi(void);
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
WEAK_DEFAULT void isr_dfsdm1_flt3(void);
WEAK_DEFAULT void isr_sdmmc2(void);
WEAK_DEFAULT void isr_can3_tx(void);
WEAK_DEFAULT void isr_can3_rx0(void);
WEAK_DEFAULT void isr_can3_rx1(void);
WEAK_DEFAULT void isr_can3_sce(void);
WEAK_DEFAULT void isr_jpeg(void);
WEAK_DEFAULT void isr_mdios(void);
#endif
/* interrupt vector table */
ISR_VECTORS const void *interrupt_vector[] = {
@ -247,5 +261,19 @@ ISR_VECTORS const void *interrupt_vector[] = {
(void*) isr_cec,
(void*) isr_i2c4_ev,
(void*) isr_i2c4_er,
(void*) isr_spdif_rx
(void*) isr_spdif_rx,
#if defined(CPU_MODEL_STM32F769NI)
(void*) isr_dsi,
(void*) isr_dfsdm1_flt0,
(void*) isr_dfsdm1_flt1,
(void*) isr_dfsdm1_flt2,
(void*) isr_dfsdm1_flt3,
(void*) isr_sdmmc2,
(void*) isr_can3_tx,
(void*) isr_can3_rx0,
(void*) isr_can3_rx1,
(void*) isr_can3_sce,
(void*) isr_jpeg,
(void*) isr_mdios,
#endif
};