diff --git a/cpu/stm32l1/include/cpu_conf.h b/cpu/stm32l1/include/cpu_conf.h
index 44e075b51f..09bcfab3a5 100644
--- a/cpu/stm32l1/include/cpu_conf.h
+++ b/cpu/stm32l1/include/cpu_conf.h
@@ -23,6 +23,36 @@
 
 #include "cpu_conf_common.h"
 
+/**
+ * @brief  STM32 L1 cpu type
+ *
+ * From CMSIS header file, allowed values for L1 cpu types are:
+ * * STM32L1XX_MD:
+ *   * Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
+ *     STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
+ *     STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
+ *     SM32L152x8xxA and STM32L152xBxxA.
+ *   * Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
+ *     STM32L100x8xx and STM32L100xBxx.
+ *
+ * * STM32L1XX_MDP:
+ *   * Ultra Low Power Medium-density Plus devices: STM32L151xCxx,
+ *     STM32L152xCxx and STM32L162xCxx
+ *   * Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx
+ *
+ * * STM32L1XX_HD: Ultra Low Power High-density devices: STM32L151xDxx,
+ *    STM32L152xDxx and STM32L162xDxx
+ *
+ * * STM32L1XX_XL: Ultra Low Power XL-density devices: STM32L151xExx,
+ *   STM32L152xExx and STM32L162xExx
+ */
+#if defined(CPU_MODEL_STM32L151RBA)
+#define STM32L1XX_MD (1U)
+#elif defined(CPU_MODEL_STM32L151RC)
+#define STM32L1XX_MDP (1U)
+#else
+#define STM32L1XX_XL (1U)
+#endif
 #include "vendor/stm32l1xx.h"
 
 #ifdef __cplusplus
@@ -34,7 +64,11 @@ extern "C" {
  * @{
  */
 #define CPU_DEFAULT_IRQ_PRIO            (1U)
+#if defined(CPU_MODEL_STM32L151RBA)
+#define CPU_IRQ_NUMOF                   (45U)
+#else
 #define CPU_IRQ_NUMOF                   (57U)
+#endif
 #define CPU_FLASH_BASE                  FLASH_BASE
 /** @} */
 
diff --git a/cpu/stm32l1/include/vendor/stm32l1xx.h b/cpu/stm32l1/include/vendor/stm32l1xx.h
index b8ed1deb26..67308e8e18 100644
--- a/cpu/stm32l1/include/vendor/stm32l1xx.h
+++ b/cpu/stm32l1/include/vendor/stm32l1xx.h
@@ -85,9 +85,8 @@
 /*  Tip: To avoid modifying this file each time you need to switch between these
         devices, you can define the device in your toolchain compiler preprocessor.
   */
-#define STM32L1XX_XL (1U)
 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
 #endif
 
 #if !defined  USE_STDPERIPH_DRIVER
diff --git a/cpu/stm32l1/vectors.c b/cpu/stm32l1/vectors.c
index b337706bce..92efd1667c 100644
--- a/cpu/stm32l1/vectors.c
+++ b/cpu/stm32l1/vectors.c
@@ -94,78 +94,93 @@ ISR_VECTORS const void *interrupt_vector[] = {
     (void*) (&_estack),             /* pointer to the top of the stack */
     /* Cortex-M3 handlers */
     (void*) reset_handler_default,  /* entry point of the program */
-    (void*) nmi_default,            /* non maskable interrupt handler */
-    (void*) hard_fault_default,     /* hard fault exception */
-    (void*) mem_manage_default,     /* memory manage exception */
-    (void*) bus_fault_default,      /* bus fault exception */
-    (void*) usage_fault_default,    /* usage fault exception */
-    (void*) (0UL),                  /* Reserved */
-    (void*) (0UL),                  /* Reserved */
-    (void*) (0UL),                  /* Reserved */
-    (void*) (0UL),                  /* Reserved */
-    (void*) isr_svc,                /* system call interrupt, in RIOT used for
-                                     * switching into thread context on boot */
-    (void*) debug_mon_default,      /* debug monitor exception */
-    (void*) (0UL),                  /* Reserved */
-    (void*) isr_pendsv,             /* pendSV interrupt, in RIOT the actual
-                                     * context switching is happening here */
-    (void*) isr_systick,            /* SysTick interrupt, not used in RIOT */
+    (void*) nmi_default,            /* [-14] non maskable interrupt handler */
+    (void*) hard_fault_default,     /* [-13] hard fault exception */
+    (void*) mem_manage_default,     /* [-12] memory manage exception */
+    (void*) bus_fault_default,      /* [-11] bus fault exception */
+    (void*) usage_fault_default,    /* [-10] usage fault exception */
+    (void*) (0UL),                  /* [-9] Reserved */
+    (void*) (0UL),                  /* [-8] Reserved */
+    (void*) (0UL),                  /* [-7] Reserved */
+    (void*) (0UL),                  /* [-6] Reserved */
+    (void*) isr_svc,                /* [-5] system call interrupt, in RIOT used for
+                                            switching into thread context on boot */
+    (void*) debug_mon_default,      /* [-4] debug monitor exception */
+    (void*) (0UL),                  /* [-3] Reserved */
+    (void*) isr_pendsv,             /* [-2] pendSV interrupt, in RIOT the actual
+                                            context switching is happening here */
+    (void*) isr_systick,            /* [-1] SysTick interrupt, not used in RIOT */
     /* STM specific peripheral handlers */
-    (void*) isr_wwdg,
-    (void*) isr_pvd,
-    (void*) isr_tamper_stamp,
-    (void*) isr_rtc_wkup,
-    (void*) isr_flash,
-    (void*) isr_rcc,
-    (void*) isr_exti,
-    (void*) isr_exti,
-    (void*) isr_exti,
-    (void*) isr_exti,
-    (void*) isr_exti,
-    (void*) isr_dma1_ch1,
-    (void*) isr_dma1_ch2,
-    (void*) isr_dma1_ch3,
-    (void*) isr_dma1_ch4,
-    (void*) isr_dma1_ch5,
-    (void*) isr_dma1_ch6,
-    (void*) isr_dma1_ch7,
-    (void*) isr_adc1,
-    (void*) isr_usb_hp,
-    (void*) isr_usb_lp,
-    (void*) isr_dac,
-    (void*) isr_comp,
-    (void*) isr_exti,
-    (void*) isr_lcd,
-    (void*) isr_tim9,
-    (void*) isr_tim10,
-    (void*) isr_tim11,
-    (void*) isr_tim2,
-    (void*) isr_tim3,
-    (void*) isr_tim4,
-    (void*) isr_i2c1_ev,
-    (void*) isr_i2c1_er,
-    (void*) isr_i2c2_ev,
-    (void*) isr_i2c2_er,
-    (void*) isr_spi1,
-    (void*) isr_spi2,
-    (void*) isr_usart1,
-    (void*) isr_usart2,
-    (void*) isr_usart3,
-    (void*) isr_exti,
-    (void*) isr_rtc_alarm,
-    (void*) isr_usb_fs_wkup,
-    (void*) isr_tim6,
-    (void*) isr_tim7,
-    (void*) isr_sdio,
-    (void*) isr_tim5,
-    (void*) isr_spi3,
-    (void*) isr_uart4,
-    (void*) isr_uart5,
-    (void*) isr_dma2_ch1,
-    (void*) isr_dma2_ch2,
-    (void*) isr_dma2_ch3,
-    (void*) isr_dma2_ch4,
-    (void*) isr_dma2_ch5,
-    (void*) isr_aes,
-    (void*) isr_comp_acq,
+    (void*) isr_wwdg,               /* [0] Window WatchDog Interrupt */
+    (void*) isr_pvd,                /* [1] PVD through EXTI Line detection Interrupt */
+    (void*) isr_tamper_stamp,       /* [2] Tamper and Time Stamp through EXTI Line Interrupts */
+    (void*) isr_rtc_wkup,           /* [3] RTC Wakeup Timer through EXTI Line Interrupt */
+    (void*) isr_flash,              /* [4] FLASH global Interrupt */
+    (void*) isr_rcc,                /* [5] RCC global Interrupt */
+    (void*) isr_exti,               /* [6] EXTI Line0 Interrupt */
+    (void*) isr_exti,               /* [7] EXTI Line1 Interrupt */
+    (void*) isr_exti,               /* [8] EXTI Line2 Interrupt */
+    (void*) isr_exti,               /* [9] EXTI Line3 Interrupt */
+    (void*) isr_exti,               /* [10] EXTI Line4 Interrupt */
+    (void*) isr_dma1_ch1,           /* [11] DMA1 Channel 1 global Interrupt */
+    (void*) isr_dma1_ch2,           /* [12] DMA1 Channel 2 global Interrupt */
+    (void*) isr_dma1_ch3,           /* [13] DMA1 Channel 3 global Interrupt */
+    (void*) isr_dma1_ch4,           /* [14] DMA1 Channel 4 global Interrupt */
+    (void*) isr_dma1_ch5,           /* [15] DMA1 Channel 5 global Interrupt */
+    (void*) isr_dma1_ch6,           /* [16] DMA1 Channel 6 global Interrupt */
+    (void*) isr_dma1_ch7,           /* [17] DMA1 Channel 7 global Interrupt */
+    (void*) isr_adc1,               /* [18] ADC1 global Interrupt */
+    (void*) isr_usb_hp,             /* [19] USB High Priority Interrupt */
+    (void*) isr_usb_lp,             /* [20] USB Low Priority Interrupt */
+    (void*) isr_dac,                /* [21] DAC Interrupt */
+    (void*) isr_comp,               /* [22] Comparator through EXTI Line Interrupt */
+    (void*) isr_exti,               /* [23] External Line[9:5] Interrupts */
+    (void*) isr_lcd,                /* [24] LCD Interrupt */
+    (void*) isr_tim9,               /* [25] TIM9 global Interrupt */
+    (void*) isr_tim10,              /* [26] TIM10 global Interrupt */
+    (void*) isr_tim11,              /* [27] TIM11 global Interrupt */
+    (void*) isr_tim2,               /* [28] TIM2 global Interrupt */
+    (void*) isr_tim3,               /* [29] TIM3 global Interrupt */
+    (void*) isr_tim4,               /* [30] TIM4 global Interrupt */
+    (void*) isr_i2c1_ev,            /* [31] I2C1 Event Interrupt */
+    (void*) isr_i2c1_er,            /* [32] I2C1 Error Interrupt */
+    (void*) isr_i2c2_ev,            /* [33] I2C2 Event Interrupt */
+    (void*) isr_i2c2_er,            /* [34] I2C2 Error Interrupt */
+    (void*) isr_spi1,               /* [35] SPI1 global Interrupt */
+    (void*) isr_spi2,               /* [36] SPI2 global Interrupt */
+    (void*) isr_usart1,             /* [37] USART1 global Interrupt */
+    (void*) isr_usart2,             /* [38] USART2 global Interrupt */
+    (void*) isr_usart3,             /* [39] USART3 global Interrupt */
+    (void*) isr_exti,               /* [40] External Line[15:10] Interrupts */
+    (void*) isr_rtc_alarm,          /* [41] RTC Alarm through EXTI Line Interrupt */
+    (void*) isr_usb_fs_wkup,        /* [42] USB FS WakeUp from suspend through EXTI Line Interrupt */
+    (void*) isr_tim6,               /* [43] TIM6 global Interrupt */
+    (void*) isr_tim7,               /* [44] TIM7 global Interrupt */
+#if defined(CPU_MODEL_STM32L151RC)
+    (void*) (0UL),                  /* [45] Reserved */
+    (void*) isr_tim5,               /* [46] TIM5 global Interrupt */
+    (void*) isr_spi3,               /* [47] SPI3 global Interrupt */
+    (void*) (0UL),                  /* [48] Reserved */
+    (void*) (0UL),                  /* [49] Reserved */
+    (void*) isr_dma2_ch1,           /* [50] DMA2 Channel 1 global Interrupt */
+    (void*) isr_dma2_ch2,           /* [51] DMA2 Channel 2 global Interrupt */
+    (void*) isr_dma2_ch3,           /* [52] DMA2 Channel 3 global Interrupt */
+    (void*) isr_dma2_ch4,           /* [53] DMA2 Channel 4 global Interrupt */
+    (void*) isr_dma2_ch5,           /* [54] DMA2 Channel 5 global Interrupt */
+    (void*) isr_aes,                /* [55] AES global Interrupt */
+    (void*) isr_comp_acq            /* [56] Comparator Channel Acquisition global Interrupt */
+#elif defined(CPU_MODEL_STM32L152RET6)
+    (void*) (0UL),                  /* [45] Reserved */
+    (void*) isr_tim5,               /* [46] TIM5 global Interrupt */
+    (void*) isr_spi3,               /* [47] SPI3 global Interrupt */
+    (void*) isr_uart4,              /* [48] UART4 global Interrupt */
+    (void*) isr_uart5,              /* [49] UART5 global Interrupt */
+    (void*) isr_dma2_ch1,           /* [50] DMA2 Channel 1 global Interrupt */
+    (void*) isr_dma2_ch2,           /* [51] DMA2 Channel 2 global Interrupt */
+    (void*) isr_dma2_ch3,           /* [52] DMA2 Channel 3 global Interrupt */
+    (void*) isr_dma2_ch4,           /* [53] DMA2 Channel 4 global Interrupt */
+    (void*) isr_dma2_ch5,           /* [54] DMA2 Channel 5 global Interrupt */
+    (void*) isr_aes,                /* [55] AES global Interrupt */
+    (void*) isr_comp_acq            /* [56] Comparator Channel Acquisition global Interrupt */
+#endif
 };