cpu/esp8266: add LoadStoreError exception handler
Usually, the access to the IROM (flash) memory requires 32-bit word aligned reads. Attempts to access data in the IROM (flash) memory less than 32 bits in size triggers a LoadStoreError exception. With the exception handler from esp-open-rtos it becomes possible to access data in IROM (flash) with a size of less than 32 bits and thus to place .rodata sections in the IROM (flash).
This commit is contained in:
Gunar Schorcht
Schorcht
parent
b17070fbf1
commit
de91b8dc88
312
cpu/esp_common/vendor/xtensa/xtensa_vectors.S
vendored
312
cpu/esp_common/vendor/xtensa/xtensa_vectors.S
vendored
@ -485,12 +485,324 @@ User Exception (including Level 1 Interrupt from user mode).
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_UserExceptionVector:
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#ifdef MCU_ESP8266
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wsr a0, EXCSAVE_1 /* preserve a0 */
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j _UserExceptionTrampoline /* jump to handler trampoline */
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#else
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wsr a0, EXCSAVE_1 /* preserve a0 */
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call0 _xt_user_exc /* user exception handler */
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/* never returns here - call0 is used as a jump (see note at top) */
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#endif
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.end literal_prefix
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#ifdef MCU_ESP8266
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/*************************** LoadStoreError Handler BEGIN ********************/
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/*
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* PLEASE NOTE: The code between "LoadStoreError Handler BEGIN" and
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* "LoadStoreError Handler END" markers was extracted from esp-open-rtos. It is
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* under the following copyright:
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*
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* Original vector contents Copyright (C) 2014-2015 Espressif Systems
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* Additions Copyright (C) Superhouse Automation Pty Ltd and Angus Gratton
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* BSD Licensed as described in the file LICENSE
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*
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* Usually, the access to the IROM (flash) memory requires 32-bit word aligned
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* reads. Attempts to access data in the IROM (flash) memory less than 32 bits
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* in size triggers a LoadStoreError exception. Therefore, it is not possible to
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* place .rodata sections in IROM (flash). Rather, .rodata sections have to
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* be placed in RAM. With the exception handler from esp-open-rtos it becomes
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* possible to access data in IROM (flash) with a size of less than 32 bits
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* and thus to place .rodata sections in the IROM (flash).
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*/
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#define CAUSE_LOADSTORE 3
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#define fatal_exception_handler _xt_user_exc
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/* LoadStoreError handler stack */
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.section .bss
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.balign 16
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_LoadStoreErrorHandlerStack:
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.word 0 # a0
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.word 0 # (unused)
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.word 0 # a2
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.word 0 # a3
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.word 0 # a4
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/* LoadStoreError Trampoline */
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.section .UserExceptionTrampoline.text, "x"
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.literal_position
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.balign 4
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_UserExceptionTrampoline:
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wsr a1, EXCSAVE_2 /* preserve a1 */
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#ifdef MCU_ESP8266
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rsr a1, exccause
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beqi a1, CAUSE_LOADSTORE, _LoadStoreErrorHandler
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#endif
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rsr a1, EXCSAVE_2 /* restore a1 */
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call0 _xt_user_exc /* user exception handler */
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/* never returns here - call0 is used as a jump (see note at top) */
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/*
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* Xtensa "Load/Store Exception" handler:
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* Completes L8/L16 load instructions from Instruction address space,
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* for which the architecture only supports 32-bit reads.
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*
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* Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
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*
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* (Fast path (no branches) is for L8UI)
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*/
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.literal_position
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.balign 4
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.type LoadStoreErrorHandler, @function
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_LoadStoreErrorHandler:
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rsr a1, EXCSAVE_2 /* restore a1 */
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wsr a1, EXCSAVE_1 /* save it to excsave1 */
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/* Registers are saved in the address corresponding to their register
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* number times 4. This allows a quick and easy mapping later on when
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* needing to store the value to a particular register number. */
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movi sp, _LoadStoreErrorHandlerStack
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s32i a0, sp, 0
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s32i a2, sp, 0x08
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s32i a3, sp, 0x0c
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s32i a4, sp, 0x10
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rsr a0, sar # Save SAR in a0 to restore later
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/* Examine the opcode which generated the exception */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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rsr a2, epc1
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movi a3, ~3
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ssa8l a2 # sar is now correct shift for aligned read
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and a2, a2, a3 # a2 now 4-byte aligned address of instruction
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l32i a4, a2, 0
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l32i a2, a2, 4
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movi a3, 0x00700F # opcode mask for l8ui/l16si/l16ui
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src a2, a2, a4 # a2 now instruction that failed
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and a3, a2, a3 # a3 is masked instruction
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bnei a3, 0x000002, .LSE_check_l16
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/* Note: At this point, opcode could technically be one of two things:
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* xx0xx2 (L8UI)
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* xx8xx2 (Reserved (invalid) opcode)
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* It is assumed that we'll never get to this point from an illegal
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* opcode, so we don't bother to check for that case and presume this
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* is always an L8UI. */
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movi a4, ~3
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rsr a3, excvaddr # read faulting address
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and a4, a3, a4 # a4 now word aligned read address
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l32i a4, a4, 0 # perform the actual read
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ssa8l a3 # sar is now shift to extract a3's byte
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srl a3, a4 # shift right correct distance
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extui a4, a3, 0, 8 # mask off bits we need for an l8
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.LSE_post_fetch:
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/* We jump back here after either the L8UI or the L16*I routines do the
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* necessary work to read the value from memory.
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* At this point, a2 holds the faulting instruction and a4 holds the
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* correctly read value.
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* Restore original SAR value (saved in a0) and update EPC so we'll
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* return back to the instruction following the one we just emulated */
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/* Note: Instructions are in this order to avoid pipeline stalls */
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rsr a3, epc1
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wsr a0, sar
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addi a3, a3, 0x3
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wsr a3, epc1
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/* Stupid opcode tricks: The jumptable we use later on needs 16 bytes
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* per entry (so we can avoid a second jump by just doing a RFE inside
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* each entry). Unfortunately, however, Xtensa doesn't have an addx16
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* operation to make that easy for us. Luckily, all of the faulting
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* opcodes we're processing are guaranteed to have bit 3 be zero, which
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* means if we just shift the register bits of the opcode down by 3
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* instead of 4, we will get the register number multiplied by 2. This
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* combined with an addx8 will give us an effective addx16 without
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* needing any extra shift operations. */
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extui a2, a2, 3, 5 # a2 is now destination register 0-15 times 2
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bgei a2, 10, .LSE_assign_reg # a5..a15 use jumptable
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beqi a2, 2, .LSE_assign_a1 # a1 uses a special routine
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/* We're storing into a0 or a2..a4, which are all saved in our "stack"
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* area. Calculate the correct address and stick the value in there,
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* then just do our normal restore and RFE (no jumps required, which
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* actually makes a0..a4 substantially faster). */
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addx2 a2, a2, sp
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s32i a4, a2, 0
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/* Restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1 # restore a1 saved by UserExceptionVector
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rfe
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.LSE_assign_reg:
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/* At this point, a2 contains the register number times 2, a4 is the
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* read value. */
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/* Calculate the jumptable address, and restore all regs except a2 and
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* a4 so we have less to do after jumping. */
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/* Note: Instructions are in this order to avoid pipeline stalls. */
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movi a3, .LSE_jumptable_base
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l32i a0, sp, 0
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addx8 a2, a2, a3 # a2 is now the address to jump to
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l32i a3, sp, 0x0c
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jx a2
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.balign 4
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.LSE_check_l16:
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/* At this point, a2 contains the opcode, a3 is masked opcode */
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movi a4, 0x001002 # l16si or l16ui opcode after masking
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bne a3, a4, .LSE_wrong_opcode
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/* Note: At this point, the opcode could be one of two things:
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* xx1xx2 (L16UI)
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* xx9xx2 (L16SI)
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* Both of these we can handle. */
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movi a4, ~3
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rsr a3, excvaddr # read faulting address
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and a4, a3, a4 # a4 now word aligned read address
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l32i a4, a4, 0 # perform the actual read
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ssa8l a3 # sar is now shift to extract a3's bytes
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srl a3, a4 # shift right correct distance
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extui a4, a3, 0, 16 # mask off bits we need for an l16
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bbci a2, 15, .LSE_post_fetch # Not a signed op
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bbci a4, 15, .LSE_post_fetch # Value does not need sign-extension
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movi a3, 0xFFFF0000
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or a4, a3, a4 # set 32-bit sign bits
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j .LSE_post_fetch
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.LSE_wrong_opcode:
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/* If we got here it's not an opcode we can try to fix, so bomb out.
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* Restore registers so any dump the fatal exception routine produces
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* will have correct values */
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wsr a0, sar
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l32i a0, sp, 0
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/*l32i a2, sp, 0x08*/
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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mov a2, a1
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movi a3, 0
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call0 fatal_exception_handler
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.balign 4
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.LSE_assign_a1:
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/* a1 is saved in excsave1, so just update that with the value, */
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wsr a4, excsave1
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/* Then restore all regs and return */
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l32i a0, sp, 0
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l32i a2, sp, 0x08
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l32i a3, sp, 0x0c
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.balign 4
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.LSE_jumptable:
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/* The first 5 entries (80 bytes) of this table are unused (registers
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* a0..a4 are handled separately above). Rather than have a whole bunch
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* of wasted space, we just pretend that the table starts 80 bytes
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* earlier in memory. */
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.set .LSE_jumptable_base, .LSE_jumptable - (16 * 5)
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.org .LSE_jumptable_base + (16 * 5)
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mov a5, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 6)
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mov a6, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 7)
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mov a7, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 8)
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mov a8, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 9)
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mov a9, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 10)
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mov a10, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 11)
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mov a11, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 12)
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mov a12, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 13)
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mov a13, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 14)
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mov a14, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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.org .LSE_jumptable_base + (16 * 15)
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mov a15, a4
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l32i a2, sp, 0x08
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l32i a4, sp, 0x10
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rsr a1, excsave1
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rfe
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/*************************** LoadStoreError Handler END **********************/
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#endif
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/*
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--------------------------------------------------------------------------------
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Insert some waypoints for jumping beyond the signed 8-bit range of
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