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cpu/cc2538: add TI vendor headers

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Currently the cc2538 is based on from-scratch adaption which is
    not feature complete and thus lacks defines etc. Introducing the
    official vendor header will ease future extension and adaptions
    of the CPU and its features.
This commit is contained in:
smlng 2018-02-05 17:34:41 +01:00
parent ccb5653f8a
commit df37e69b90
25 changed files with 20771 additions and 0 deletions
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4379
cpu/cc2538/include/vendor/hw_aes.h vendored Executable file
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86
cpu/cc2538/include/vendor/hw_ana_regs.h vendored Executable file
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/******************************************************************************
* Filename: hw_ana_regs.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_ANA_REGS_H__
#define __HW_ANA_REGS_H__
//*****************************************************************************
//
// The following are defines for the ANA_REGS register offsets.
//
//*****************************************************************************
#define ANA_REGS_O_IVCTRL 0x00000004 // Analog control register
//*****************************************************************************
//
// The following are defines for the bit fields in the
// ANA_REGS_O_IVCTRL register.
//
//*****************************************************************************
#define ANA_REGS_IVCTRL_DAC_CURR_CTRL_M \
0x00000030 // Controls bias current to DAC
// 00: 100% IVREF, 0% IREF bias 01:
// 60% IVREF, 40% IREF bias 10: 40%
// IVREF, 60% IREF bias 11: 0%
// IVREF, 100% IREF bias
#define ANA_REGS_IVCTRL_DAC_CURR_CTRL_S 4
#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL \
0x00000008 // Controls bias current to LODIV
// 1: PTAT bias 0: IVREF bias
#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL_M \
0x00000008
#define ANA_REGS_IVCTRL_LODIV_BIAS_CTRL_S 3
#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL \
0x00000004 // Controls DC bias in TXMIX
#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL_M \
0x00000004
#define ANA_REGS_IVCTRL_TXMIX_DC_CTRL_S 2
#define ANA_REGS_IVCTRL_PA_BIAS_CTRL_M \
0x00000003 // Controls bias current to PA 00:
// IREF bias 01: IREF and IVREF
// bias (CC2530 mode) 10: PTAT bias
// 11: Increased PTAT slope bias
#define ANA_REGS_IVCTRL_PA_BIAS_CTRL_S 0
#endif // __HW_ANA_REGS_H__

266
cpu/cc2538/include/vendor/hw_cctest.h vendored Executable file
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/******************************************************************************
* Filename: hw_cctest.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_CCTEST_H__
#define __HW_CCTEST_H__
//*****************************************************************************
//
// The following are defines for the CCTEST register offsets.
//
//*****************************************************************************
#define CCTEST_IO 0x44010000 // Output strength control
#define CCTEST_OBSSEL0 0x44010014 // Select output signal on
// observation output 0
#define CCTEST_OBSSEL1 0x44010018 // Select output signal on
// observation output 1
#define CCTEST_OBSSEL2 0x4401001C // Select output signal on
// observation output 2
#define CCTEST_OBSSEL3 0x44010020 // Select output signal on
// observation output 3
#define CCTEST_OBSSEL4 0x44010024 // Select output signal on
// observation output 4
#define CCTEST_OBSSEL5 0x44010028 // Select output signal on
// observation output 5
#define CCTEST_OBSSEL6 0x4401002C // Select output signal on
// observation output 6
#define CCTEST_OBSSEL7 0x44010030 // Select output signal on
// observation output 7
#define CCTEST_TR0 0x44010034 // Test register 0
#define CCTEST_USBCTRL 0x44010050 // USB PHY stand-by control
//*****************************************************************************
//
// The following are defines for the bit fields in the CCTEST_IO register.
//
//*****************************************************************************
#define CCTEST_IO_SC 0x00000001 // I/O strength control bit Common
// to all digital output pads
// Should be set when unregulated
// voltage is below approximately
// 2.6 V.
#define CCTEST_IO_SC_M 0x00000001
#define CCTEST_IO_SC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL0 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL0_EN 0x00000080 // Observation output 0 enable
// control for PC0 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC0.
#define CCTEST_OBSSEL0_EN_M 0x00000080
#define CCTEST_OBSSEL0_EN_S 7
#define CCTEST_OBSSEL0_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 0: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL0_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL1 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL1_EN 0x00000080 // Observation output 1 enable
// control for PC1 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC1.
#define CCTEST_OBSSEL1_EN_M 0x00000080
#define CCTEST_OBSSEL1_EN_S 7
#define CCTEST_OBSSEL1_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 1: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL1_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL2 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL2_EN 0x00000080 // Observation output 2 enable
// control for PC2 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC2.
#define CCTEST_OBSSEL2_EN_M 0x00000080
#define CCTEST_OBSSEL2_EN_S 7
#define CCTEST_OBSSEL2_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 2: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL2_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL3 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL3_EN 0x00000080 // Observation output 3 enable
// control for PC3 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC3.
#define CCTEST_OBSSEL3_EN_M 0x00000080
#define CCTEST_OBSSEL3_EN_S 7
#define CCTEST_OBSSEL3_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 3: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL3_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL4 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL4_EN 0x00000080 // Observation output 4 enable
// control for PC4 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC4.
#define CCTEST_OBSSEL4_EN_M 0x00000080
#define CCTEST_OBSSEL4_EN_S 7
#define CCTEST_OBSSEL4_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 4: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL4_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL5 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL5_EN 0x00000080 // Observation output 5 enable
// control for PC5 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC5.
#define CCTEST_OBSSEL5_EN_M 0x00000080
#define CCTEST_OBSSEL5_EN_S 7
#define CCTEST_OBSSEL5_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 5: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL5_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL6 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL6_EN 0x00000080 // Observation output 6 enable
// control for PC6 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC6.
#define CCTEST_OBSSEL6_EN_M 0x00000080
#define CCTEST_OBSSEL6_EN_S 7
#define CCTEST_OBSSEL6_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 6: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL6_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_OBSSEL7 register.
//
//*****************************************************************************
#define CCTEST_OBSSEL7_EN 0x00000080 // Observation output 7 enable
// control for PC7 0: Observation
// output disabled 1: Observation
// output enabled Note: If enabled,
// this overwrites the standard
// GPIO behavior of PC7.
#define CCTEST_OBSSEL7_EN_M 0x00000080
#define CCTEST_OBSSEL7_EN_S 7
#define CCTEST_OBSSEL7_SEL_M 0x0000007F // n - obs_sigs[n] output on
// output 7: 0: rfc_obs_sig0 1:
// rfc_obs_sig1 2: rfc_obs_sig2
// Others: Reserved
#define CCTEST_OBSSEL7_SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the CCTEST_TR0 register.
//
//*****************************************************************************
#define CCTEST_TR0_ADCTM 0x00000002 // Set to 1 to connect the
// temperature sensor to the
// SOC_ADC. See also
// RFCORE_XREG_ATEST register
// description to enable the
// temperature sensor.
#define CCTEST_TR0_ADCTM_M 0x00000002
#define CCTEST_TR0_ADCTM_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the
// CCTEST_USBCTRL register.
//
//*****************************************************************************
#define CCTEST_USBCTRL_USB_STB 0x00000001 // USB PHY stand-by override bit
// When this bit is cleared to 0
// (default state) the USB module
// cannot change the stand-by mode
// of the PHY (USB pads) and the
// PHY is forced out of stand-by
// mode. This bit must be 1 as well
// as the stand-by control from the
// USB controller, before the mode
// of the PHY is stand-by.
#define CCTEST_USBCTRL_USB_STB_M \
0x00000001
#define CCTEST_USBCTRL_USB_STB_S 0
#endif // __HW_CCTEST_H__

449
cpu/cc2538/include/vendor/hw_flash_ctrl.h vendored Executable file
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/******************************************************************************
* Filename: hw_flash_ctrl.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_FLASH_CTRL_H__
#define __HW_FLASH_CTRL_H__
//*****************************************************************************
//
// The following are defines for the FLASH_CTRL register offsets.
//
//*****************************************************************************
#define FLASH_CTRL_FCTL 0x400D3008 // Flash control This register
// provides control and monitoring
// functions for the flash module.
#define FLASH_CTRL_FADDR 0x400D300C // Flash address The register sets
// the address to be written in
// flash memory. See the bitfield
// descriptions for formatting
// information.
#define FLASH_CTRL_FWDATA 0x400D3010 // Flash data This register
// contains the 32-bits of data to
// be written to the flash location
// selected in FADDR.
#define FLASH_CTRL_DIECFG0 0x400D3014 // These settings are a function
// of the FLASH information page
// bit settings, which are
// programmed during production
// test, and are subject for
// specific configuration for
// multiple device flavors of
// cc2538.
#define FLASH_CTRL_DIECFG1 0x400D3018 // These settings are a function
// of the FLASH information page
// bit settings, which are
// programmed during production
// test, and are subject for
// specific configuration for
// multiple device flavors of
// cc2538.
#define FLASH_CTRL_DIECFG2 0x400D301C // These settings are a function
// of the FLASH information page
// bit settings, which are
// programmed during production
// test, and are subject for
// specific configuration for
// multiple device flavors of
// cc2538. The DIE_*_REVISION
// registers are an exeception to
// this, as they are hardwired and
// are not part of the FLASH
// information page.
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_FCTL register.
//
//*****************************************************************************
#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS \
0x00000200 // Lock bit for lock bit page 0:
// Neither write nor erase not
// allowed 1: Both write and erase
// allowed
#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_M \
0x00000200
#define FLASH_CTRL_FCTL_UPPER_PAGE_ACCESS_S 9
#define FLASH_CTRL_FCTL_SEL_INFO_PAGE \
0x00000100 // Flash erase or write operation
// on APB bus must assert this when
// accessing the information page
#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_M \
0x00000100
#define FLASH_CTRL_FCTL_SEL_INFO_PAGE_S 8
#define FLASH_CTRL_FCTL_BUSY 0x00000080 // Set when the WRITE or ERASE bit
// is set; that is, when the flash
// controller is busy
#define FLASH_CTRL_FCTL_BUSY_M 0x00000080
#define FLASH_CTRL_FCTL_BUSY_S 7
#define FLASH_CTRL_FCTL_FULL 0x00000040 // Write buffer full The CPU can
// write to FWDATA when this bit is
// 0 and WRITE is 1. This bit is
// cleared when BUSY is cleared.
#define FLASH_CTRL_FCTL_FULL_M 0x00000040
#define FLASH_CTRL_FCTL_FULL_S 6
#define FLASH_CTRL_FCTL_ABORT 0x00000020 // Abort status This bit is set to
// 1 when a write sequence or page
// erase is aborted. An operation
// is aborted when the accessed
// page is locked. Cleared when a
// write or page erase is started.
// If a write operation times out
// (because the FWDATA register is
// not written fast enough), the
// ABORT bit is not set even if the
// page is locked. If a page erase
// and a write operation are
// started simultaneously, the
// ABORT bit reflects the status of
// the last write operation. For
// example, if the page is locked
// and the write times out, the
// ABORT bit is not set because
// only the write operation times
// out.
#define FLASH_CTRL_FCTL_ABORT_M 0x00000020
#define FLASH_CTRL_FCTL_ABORT_S 5
#define FLASH_CTRL_FCTL_CM_M 0x0000000C // Cache Mode Disabling the cache
// increases the power consumption
// and reduces performance.
// Prefetching improves performance
// at the expense of a potential
// increase in power consumption.
// Real-time mode provides
// predictable flash read access
// time, the execution time is
// equal to cache disabled mode,
// but the power consumption is
// lower. 00: Cache disabled 01:
// Cache enabled 10: Cache enabled,
// with prefetch 11: Real-time mode
// Note: The read value always
// represents the current cache
// mode. Writing a new cache mode
// starts a cache mode change
// request that does not take
// effect until the controller is
// ready. Writes to this register
// are ignored if there is a
// current cache change request in
// progress.
#define FLASH_CTRL_FCTL_CM_S 2
#define FLASH_CTRL_FCTL_WRITE 0x00000002 // Write bit Start a write
// sequence by setting this bit to
// 1. Cleared by hardware when the
// operation completes. Writes to
// this bit are ignored when
// FCTL.BUSY is 1. If FCTL.ERASE is
// set simultaneously with this
// bit, the erase operation is
// started first, then the write is
// started.
#define FLASH_CTRL_FCTL_WRITE_M 0x00000002
#define FLASH_CTRL_FCTL_WRITE_S 1
#define FLASH_CTRL_FCTL_ERASE 0x00000001 // Erase bit Start an erase
// operation by setting this bit to
// 1. Cleared by hardware when the
// operation completes. Writes to
// this bit are ignored when
// FCTL.BUSY is 1. If FCTL.WRITE is
// set simultaneously with this
// bit, the erase operation is
// started first, then the write is
// started.
#define FLASH_CTRL_FCTL_ERASE_M 0x00000001
#define FLASH_CTRL_FCTL_ERASE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_FADDR register.
//
//*****************************************************************************
#define FLASH_CTRL_FADDR_FADDR_M \
0x0001FFFF // Bit number [16:9] selects one
// of 256 pages for page erase. Bit
// number [8:7] selects one of the
// 4 row in a given page Bit number
// [6:1] selects one of the 64-bit
// wide locations in a give row.
// Bit number [0] will select
// upper/lower 32-bits in a given
// 64-bit location - 64Kbytes -->
// Bits [16:14] will always be 0. -
// 128Kbytes --> Bits [16:15] will
// always be 0. - 256Kbytes --> Bit
// [16] will always be 0. -
// 384/512Kbytes --> All bits
// written and valid. Writes to
// this register will be ignored
// when any of FCTL.WRITE and
// FCTL.ERASE is set. FADDR should
// be written with byte addressable
// location of the Flash to be
// programmed. Read back value
// always reflects a 32-bit aligned
// address. When the register is
// read back, the value that was
// written to FADDR gets right
// shift by 2 to indicate 32-bit
// aligned address. In other words
// lower 2 bits are discarded while
// reading back the register. Out
// of range address results in roll
// over. There is no status signal
// generated by flash controller to
// indicate this. Firmware is
// responsible to managing the
// addresses correctly.
#define FLASH_CTRL_FADDR_FADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_FWDATA register.
//
//*****************************************************************************
#define FLASH_CTRL_FWDATA_FWDATA_M \
0xFFFFFFFF // 32-bit flash write data Writes
// to this register are accepted
// only during a flash write
// sequence; that is, writes to
// this register after having
// written 1 to the FCTL.WRITE bit.
// New 32-bit data is written only
// if FCTL.FULL = 0.
#define FLASH_CTRL_FWDATA_FWDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_DIECFG0 register.
//
//*****************************************************************************
#define FLASH_CTRL_DIECFG0_CHIPID_M \
0xFFFF0000 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit
// field is equal to the field with
// the same name in the information
// page.
#define FLASH_CTRL_DIECFG0_CHIPID_S 16
#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N \
0x00000400 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit is
// equal to the field with the same
// name in the information page.
#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_M \
0x00000400
#define FLASH_CTRL_DIECFG0_CLK_SEL_GATE_EN_N_S 10
#define FLASH_CTRL_DIECFG0_SRAM_SIZE_M \
0x00000380 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit
// field is equal to the field with
// the same name in the information
// page.
#define FLASH_CTRL_DIECFG0_SRAM_SIZE_S 7
#define FLASH_CTRL_DIECFG0_FLASH_SIZE_M \
0x00000070 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit
// field is equal to the field with
// the same name in the information
// page.
#define FLASH_CTRL_DIECFG0_FLASH_SIZE_S 4
#define FLASH_CTRL_DIECFG0_USB_ENABLE \
0x00000008 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit is
// equal to the field with the same
// name in the information page.
#define FLASH_CTRL_DIECFG0_USB_ENABLE_M \
0x00000008
#define FLASH_CTRL_DIECFG0_USB_ENABLE_S 3
#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE \
0x00000004 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit is
// equal to the field with the same
// name in the information page.
#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_M \
0x00000004
#define FLASH_CTRL_DIECFG0_MASS_ERASE_ENABLE_S 2
#define FLASH_CTRL_DIECFG0_LOCK_FWT_N \
0x00000002 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit is
// equal to the field with the same
// name in the information page.
#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_M \
0x00000002
#define FLASH_CTRL_DIECFG0_LOCK_FWT_N_S 1
#define FLASH_CTRL_DIECFG0_LOCK_IP_N \
0x00000001 // Register copy of configuration
// bits Three clock cycles after
// reset is released, this bit is
// equal to the field with the same
// name in the information page.
#define FLASH_CTRL_DIECFG0_LOCK_IP_N_M \
0x00000001
#define FLASH_CTRL_DIECFG0_LOCK_IP_N_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_DIECFG1 register.
//
//*****************************************************************************
#define FLASH_CTRL_DIECFG1_I2C_EN \
0x01000000 // 1: I2C is enabled. 0: I2C is
// permanently disabled.
#define FLASH_CTRL_DIECFG1_I2C_EN_M \
0x01000000
#define FLASH_CTRL_DIECFG1_I2C_EN_S 24
#define FLASH_CTRL_DIECFG1_UART1_EN \
0x00020000 // 1: UART1 is enabled. 0: UART1
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_UART1_EN_M \
0x00020000
#define FLASH_CTRL_DIECFG1_UART1_EN_S 17
#define FLASH_CTRL_DIECFG1_UART0_EN \
0x00010000 // 1: UART0 is enabled. 0: UART0
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_UART0_EN_M \
0x00010000
#define FLASH_CTRL_DIECFG1_UART0_EN_S 16
#define FLASH_CTRL_DIECFG1_SSI1_EN \
0x00000200 // 1: SSI1 is enabled. 0: SSI1 is
// permanently disabled.
#define FLASH_CTRL_DIECFG1_SSI1_EN_M \
0x00000200
#define FLASH_CTRL_DIECFG1_SSI1_EN_S 9
#define FLASH_CTRL_DIECFG1_SSI0_EN \
0x00000100 // 1: SSI0 is enabled. 0: SSI0 is
// permanently disabled.
#define FLASH_CTRL_DIECFG1_SSI0_EN_M \
0x00000100
#define FLASH_CTRL_DIECFG1_SSI0_EN_S 8
#define FLASH_CTRL_DIECFG1_GPTM3_EN \
0x00000008 // 1: GPTM3 is enabled. 0: GPTM3
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_GPTM3_EN_M \
0x00000008
#define FLASH_CTRL_DIECFG1_GPTM3_EN_S 3
#define FLASH_CTRL_DIECFG1_GPTM2_EN \
0x00000004 // 1: GPTM2 is enabled. 0: GPTM2
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_GPTM2_EN_M \
0x00000004
#define FLASH_CTRL_DIECFG1_GPTM2_EN_S 2
#define FLASH_CTRL_DIECFG1_GPTM1_EN \
0x00000002 // 1: GPTM1 is enabled. 0: GPTM1
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_GPTM1_EN_M \
0x00000002
#define FLASH_CTRL_DIECFG1_GPTM1_EN_S 1
#define FLASH_CTRL_DIECFG1_GPTM0_EN \
0x00000001 // 1: GPTM0 is enabled. 0: GPTM0
// is permanently disabled.
#define FLASH_CTRL_DIECFG1_GPTM0_EN_M \
0x00000001
#define FLASH_CTRL_DIECFG1_GPTM0_EN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// FLASH_CTRL_DIECFG2 register.
//
//*****************************************************************************
#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_M \
0x0000F000 // Indicates the major revision
// (all layer change) number for
// the cc2538 0x0 - PG1.0 0x2 -
// PG2.0
#define FLASH_CTRL_DIECFG2_DIE_MAJOR_REVISION_S 12
#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_M \
0x00000F00 // Indicates the minor revision
// (metla layer only) number for
// the cc2538 0x0 - PG1.0 or PG2.0
#define FLASH_CTRL_DIECFG2_DIE_MINOR_REVISION_S 8
#define FLASH_CTRL_DIECFG2_RF_CORE_EN \
0x00000004 // 1: RF_CORE is enabled. 0:
// RF_CORE is permanently disabled.
#define FLASH_CTRL_DIECFG2_RF_CORE_EN_M \
0x00000004
#define FLASH_CTRL_DIECFG2_RF_CORE_EN_S 2
#define FLASH_CTRL_DIECFG2_AES_EN \
0x00000002 // 1: AES is enabled. 0: AES is
// permanently disabled.
#define FLASH_CTRL_DIECFG2_AES_EN_M \
0x00000002
#define FLASH_CTRL_DIECFG2_AES_EN_S 1
#define FLASH_CTRL_DIECFG2_PKA_EN \
0x00000001 // 1: PKA is enabled. 0: PKA is
// permanently disabled.
#define FLASH_CTRL_DIECFG2_PKA_EN_M \
0x00000001
#define FLASH_CTRL_DIECFG2_PKA_EN_S 0
#endif // __HW_FLASH_CTRL_H__

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/******************************************************************************
* Filename: hw_i2cm.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_I2CM_H__
#define __HW_I2CM_H__
//*****************************************************************************
//
// The following are defines for the I2CM register offsets.
//
//*****************************************************************************
#define I2CM_SA 0x40020000 // I2C master slave address This
// register consists of eight bits,
// seven address bits (A6-A0), and
// a receive and send bit, which
// determines if the next operation
// is a receive (high) or transmit
// (low).
#define I2CM_CTRL 0x40020004 // I2C master control and status
// This register accesses status
// bits when read and control bits
// when written. When read, the
// status register indicates the
// state of the I2C bus controller.
// When written, the control
// register configures the I2C
// controller operation. The START
// bit generates the START or
// REPEATED START condition. The
// STOP bit determines if the cycle
// stops at the end of the data
// cycle or continues on to a
// repeated START condition. To
// generate a single transmit
// cycle, the I2C master slave
// address (I2CMSA) register is
// written with the desired
// address, the R/S bit is cleared,
// and this register is written
// with ACK = X (0 or 1), STOP = 1,
// START = 1, and RUN = 1 to
// perform the operation and stop.
// When the operation is completed
// (or aborted due an error), an
// interrupt becomes active and the
// data may be read from the I2CMDR
// register. When the I2C module
// operates in master receiver
// mode, the ACK bit is normally
// set, causing the I2C bus
// controller to automatically
// transmit an acknowledge after
// each byte. This bit must be
// cleared when the I2C bus
// controller requires no further
// data to be transmitted from the
// slave transmitter.
#define I2CM_STAT 0x40020004 // I2C master control and status
// This register accesses status
// bits when read and control bits
// when written. When read, the
// status register indicates the
// state of the I2C bus controller.
// When written, the control
// register configures the I2C
// controller operation. The START
// bit generates the START or
// REPEATED START condition. The
// STOP bit determines if the cycle
// stops at the end of the data
// cycle or continues on to a
// repeated START condition. To
// generate a single transmit
// cycle, the I2C master slave
// address (I2CMSA) register is
// written with the desired
// address, the R/S bit is cleared,
// and this register is written
// with ACK = X (0 or 1), STOP = 1,
// START = 1, and RUN = 1 to
// perform the operation and stop.
// When the operation is completed
// (or aborted due an error), an
// interrupt becomes active and the
// data may be read from the I2CMDR
// register. When the I2C module
// operates in master receiver
// mode, the ACK bit is normally
// set, causing the I2C bus
// controller to automatically
// transmit an acknowledge after
// each byte. This bit must be
// cleared when the I2C bus
// controller requires no further
// data to be transmitted from the
// slave transmitter.
#define I2CM_DR 0x40020008 // I2C master data This register
// contains the data to be
// transmitted when in the master
// transmit state and the data
// received when in the master
// receive state.
#define I2CM_TPR 0x4002000C // I2C master timer period This
// register specifies the period of
// the SCL clock.
#define I2CM_IMR 0x40020010 // I2C master interrupt mask This
// register controls whether a raw
// interrupt is promoted to a
// controller interrupt.
#define I2CM_RIS 0x40020014 // I2C master raw interrupt status
// This register specifies whether
// an interrupt is pending.
#define I2CM_MIS 0x40020018 // I2C master masked interrupt
// status This register specifies
// whether an interrupt was
// signaled.
#define I2CM_ICR 0x4002001C // I2C master interrupt clear This
// register clears the raw and
// masked interrupts.
#define I2CM_CR 0x40020020 // I2C master configuration This
// register configures the mode
// (master or slave) and sets the
// interface for test mode
// loopback.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_SA register.
//
//*****************************************************************************
#define I2CM_SA_SA_M 0x000000FE // I2C slave address
#define I2CM_SA_SA_S 1
#define I2CM_SA_RS 0x00000001 // Receive and send The R/S bit
// specifies if the next operation
// is a receive (high) or transmit
// (low). 0: Transmit 1: Receive
#define I2CM_SA_RS_M 0x00000001
#define I2CM_SA_RS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_CTRL register.
//
//*****************************************************************************
#define I2CM_CTRL_ACK 0x00000008 // Data acknowledge enable 0: The
// received data byte is not
// acknowledged automatically by
// the master. 1: The received data
// byte is acknowledged
// automatically by the master.
#define I2CM_CTRL_ACK_M 0x00000008
#define I2CM_CTRL_ACK_S 3
#define I2CM_CTRL_STOP 0x00000004 // Generate STOP 0: The controller
// does not generate the STOP
// condition. 1: The controller
// generates the STOP condition.
#define I2CM_CTRL_STOP_M 0x00000004
#define I2CM_CTRL_STOP_S 2
#define I2CM_CTRL_START 0x00000002 // Generate START 0: The
// controller does not generate the
// START condition. 1: The
// controller generates the START
// condition.
#define I2CM_CTRL_START_M 0x00000002
#define I2CM_CTRL_START_S 1
#define I2CM_CTRL_RUN 0x00000001 // I2C master enable 0: The master
// is disabled. 1: The master is
// enabled to transmit or receive
// data. When the BUSY bit is set,
// the other status bits are not
// valid.
#define I2CM_CTRL_RUN_M 0x00000001
#define I2CM_CTRL_RUN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_STAT register.
//
//*****************************************************************************
#define I2CM_STAT_BUSBSY 0x00000040 // Bus busy 0: The I2C bus is
// idle. 1: The I2C bus is busy.
// The bit changes based on the
// START and STOP conditions.
#define I2CM_STAT_BUSBSY_M 0x00000040
#define I2CM_STAT_BUSBSY_S 6
#define I2CM_STAT_IDLE 0x00000020 // I2C idle 0: The I2C controller
// is not idle. 1: The I2C
// controller is idle.
#define I2CM_STAT_IDLE_M 0x00000020
#define I2CM_STAT_IDLE_S 5
#define I2CM_STAT_ARBLST 0x00000010 // Arbitration lost 0: The I2C
// controller won arbitration. 1:
// The I2C controller lost
// arbitration.
#define I2CM_STAT_ARBLST_M 0x00000010
#define I2CM_STAT_ARBLST_S 4
#define I2CM_STAT_DATACK 0x00000008 // Acknowledge data 0: The
// transmited data was
// acknowledged. 1: The transmited
// data was not acknowledged.
#define I2CM_STAT_DATACK_M 0x00000008
#define I2CM_STAT_DATACK_S 3
#define I2CM_STAT_ADRACK 0x00000004 // Acknowledge address 0: The
// transmited address was
// acknowledged. 1: The transmited
// address was not acknowledged.
#define I2CM_STAT_ADRACK_M 0x00000004
#define I2CM_STAT_ADRACK_S 2
#define I2CM_STAT_ERROR 0x00000002 // Error 0: No error was detected
// on the last operation. 1: An
// error occurred on the last
// operation.
#define I2CM_STAT_ERROR_M 0x00000002
#define I2CM_STAT_ERROR_S 1
#define I2CM_STAT_BUSY 0x00000001 // I2C busy 0: The controller is
// idle. 1: The controller is busy.
// When the BUSY bit is set, the
// other status bits are not valid.
#define I2CM_STAT_BUSY_M 0x00000001
#define I2CM_STAT_BUSY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_DR register.
//
//*****************************************************************************
#define I2CM_DR_DATA_M 0x000000FF // Data transferred Data
// transferred during transaction
#define I2CM_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_TPR register.
//
//*****************************************************************************
#define I2CM_TPR_TPR_M 0x0000007F // SCL clock period This field
// specifies the period of the SCL
// clock. SCL_PRD = 2 *
// (1+TPR)*(SCL_LP +
// SCL_HP)*CLK_PRD where: SCL_PRD
// is the SCL line period (I2C
// clock). TPR is the timer period
// register value (range of 1 to
// 127) SCL_LP is the SCL low
// period (fixed at 6). SCL_HP is
// the SCL high period (fixed at
// 4). CLK_PRD is the system clock
// period in ns.
#define I2CM_TPR_TPR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_IMR register.
//
//*****************************************************************************
#define I2CM_IMR_IM 0x00000001 // Interrupt mask 1: The master
// interrupt is sent to the
// interrupt controller when the
// RIS bit in the I2CMRIS register
// is set. 0: The RIS interrupt is
// suppressed and not sent to the
// interrupt controller.
#define I2CM_IMR_IM_M 0x00000001
#define I2CM_IMR_IM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_RIS register.
//
//*****************************************************************************
#define I2CM_RIS_RIS 0x00000001 // Raw interrupt status 1: A
// master interrupt is pending. 0:
// No interrupt This bit is cleared
// by writing 1 to the IC bit in
// the I2CMICR register.
#define I2CM_RIS_RIS_M 0x00000001
#define I2CM_RIS_RIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_MIS register.
//
//*****************************************************************************
#define I2CM_MIS_MIS 0x00000001 // Masked interrupt status 1: An
// unmasked master interrupt is
// pending. 0: An interrupt has not
// occurred or is masked. This bit
// is cleared by writing 1 to the
// IC bit in the I2CMICR register.
#define I2CM_MIS_MIS_M 0x00000001
#define I2CM_MIS_MIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_ICR register.
//
//*****************************************************************************
#define I2CM_ICR_IC 0x00000001 // Interrupt clear Writing 1 to
// this bit clears the RIS bit in
// the I2CMRIS register and the MIS
// bit in the I2CMMIS register.
// Reading this register returns no
// meaningful data.
#define I2CM_ICR_IC_M 0x00000001
#define I2CM_ICR_IC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CM_CR register.
//
//*****************************************************************************
#define I2CM_CR_SFE 0x00000020 // I2C slave function enable 1:
// Slave mode is enabled. 0: Slave
// mode is disabled.
#define I2CM_CR_SFE_M 0x00000020
#define I2CM_CR_SFE_S 5
#define I2CM_CR_MFE 0x00000010 // I2C master function enable 1:
// Master mode is enabled. 0:
// Master mode is disabled.
#define I2CM_CR_MFE_M 0x00000010
#define I2CM_CR_MFE_S 4
#define I2CM_CR_LPBK 0x00000001 // I2C loopback 1: The controller
// in a test mode loopback
// configuration. 0: Normal
// operation
#define I2CM_CR_LPBK_M 0x00000001
#define I2CM_CR_LPBK_S 0
#endif // __HW_I2CM_H__

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/******************************************************************************
* Filename: hw_i2cs.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_I2CS_H__
#define __HW_I2CS_H__
//*****************************************************************************
//
// The following are defines for the I2CS register offsets.
//
//*****************************************************************************
#define I2CS_OAR 0x40020800 // I2C slave own address This
// register consists of seven
// address bits that identify the
// CC2538 I2C device on the I2C
// bus.
#define I2CS_STAT 0x40020804 // I2C slave control and status
// This register functions as a
// control register when written,
// and a status register when read.
#define I2CS_CTRL 0x40020804 // I2C slave control and status
// This register functions as a
// control register when written,
// and a status register when read.
#define I2CS_DR 0x40020808 // I2C slave data This register
// contains the data to be
// transmitted when in the slave
// transmit state, and the data
// received when in the slave
// receive state.
#define I2CS_IMR 0x4002080C // I2C slave interrupt mask This
// register controls whether a raw
// interrupt is promoted to a
// controller interrupt.
#define I2CS_RIS 0x40020810 // I2C slave raw interrupt status
// This register specifies whether
// an interrupt is pending.
#define I2CS_MIS 0x40020814 // I2C slave masked interrupt
// status This register specifies
// whether an interrupt was
// signaled.
#define I2CS_ICR 0x40020818 // I2C slave interrupt clear This
// register clears the raw
// interrupt. A read of this
// register returns no meaningful
// data.
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_OAR register.
//
//*****************************************************************************
#define I2CS_OAR_OAR_M 0x0000007F // I2C slave own address This
// field specifies bits A6 through
// A0 of the slave address.
#define I2CS_OAR_OAR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_STAT register.
//
//*****************************************************************************
#define I2CS_STAT_FBR 0x00000004 // First byte received 1: The
// first byte following the slave's
// own address has been received.
// 0: The first byte has not been
// received. This bit is only valid
// when the RREQ bit is set and is
// automatically cleared when data
// has been read from the I2CSDR
// register. Note: This bit is not
// used for slave transmit
// operations.
#define I2CS_STAT_FBR_M 0x00000004
#define I2CS_STAT_FBR_S 2
#define I2CS_STAT_TREQ 0x00000002 // Transmit request 1: The I2C
// controller has been addressed as
// a slave transmitter and is using
// clock stretching to delay the
// master until data has been
// written to the I2CSDR register.
// 0: No outstanding transmit
// request.
#define I2CS_STAT_TREQ_M 0x00000002
#define I2CS_STAT_TREQ_S 1
#define I2CS_STAT_RREQ 0x00000001 // Receive request 1: The I2C
// controller has outstanding
// receive data from the I2C master
// and is using clock stretching to
// delay the master until data has
// been read from the I2CSDR
// register. 0: No outstanding
// receive data
#define I2CS_STAT_RREQ_M 0x00000001
#define I2CS_STAT_RREQ_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_CTRL register.
//
//*****************************************************************************
#define I2CS_CTRL_DA 0x00000001 // Device active 0: Disables the
// I2C slave operation 1: Enables
// the I2C slave operation
#define I2CS_CTRL_DA_M 0x00000001
#define I2CS_CTRL_DA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_DR register.
//
//*****************************************************************************
#define I2CS_DR_DATA_M 0x000000FF // Data for transfer This field
// contains the data for transfer
// during a slave receive or
// transmit operation.
#define I2CS_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_IMR register.
//
//*****************************************************************************
#define I2CS_IMR_STOPIM 0x00000004 // Stop condition interrupt mask
// 1: The STOP condition interrupt
// is sent to the interrupt
// controller when the STOPRIS bit
// in the I2CSRIS register is set.
// 0: The STOPRIS interrupt is
// supressed and not sent to the
// interrupt controller.
#define I2CS_IMR_STOPIM_M 0x00000004
#define I2CS_IMR_STOPIM_S 2
#define I2CS_IMR_STARTIM 0x00000002 // Start condition interrupt mask
// 1: The START condition interrupt
// is sent to the interrupt
// controller when the STARTRIS bit
// in the I2CSRIS register is set.
// 0: The STARTRIS interrupt is
// supressed and not sent to the
// interrupt controller.
#define I2CS_IMR_STARTIM_M 0x00000002
#define I2CS_IMR_STARTIM_S 1
#define I2CS_IMR_DATAIM 0x00000001 // Data interrupt mask 1: The data
// received or data requested
// interrupt is sent to the
// interrupt controller when the
// DATARIS bit in the I2CSRIS
// register is set. 0: The DATARIS
// interrupt is surpressed and not
// sent to the interrupt
// controller.
#define I2CS_IMR_DATAIM_M 0x00000001
#define I2CS_IMR_DATAIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_RIS register.
//
//*****************************************************************************
#define I2CS_RIS_STOPRIS 0x00000004 // Stop condition raw interrupt
// status 1: A STOP condition
// interrupt is pending. 0: No
// interrupt This bit is cleared by
// writing 1 to the STOPIC bit in
// the I2CSICR register.
#define I2CS_RIS_STOPRIS_M 0x00000004
#define I2CS_RIS_STOPRIS_S 2
#define I2CS_RIS_STARTRIS 0x00000002 // Start condition raw interrupt
// status 1: A START condition
// interrupt is pending. 0: No
// interrupt This bit is cleared by
// writing 1 to the STARTIC bit in
// the I2CSICR register.
#define I2CS_RIS_STARTRIS_M 0x00000002
#define I2CS_RIS_STARTRIS_S 1
#define I2CS_RIS_DATARIS 0x00000001 // Data raw interrupt status 1: A
// data received or data requested
// interrupt is pending. 0: No
// interrupt This bit is cleared by
// writing 1 to the DATAIC bit in
// the I2CSICR register.
#define I2CS_RIS_DATARIS_M 0x00000001
#define I2CS_RIS_DATARIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_MIS register.
//
//*****************************************************************************
#define I2CS_MIS_STOPMIS 0x00000004 // Stop condition masked interrupt
// status 1: An unmasked STOP
// condition interrupt is pending.
// 0: An interrupt has not occurred
// or is masked. This bit is
// cleared by writing 1 to the
// STOPIC bit in the I2CSICR
// register.
#define I2CS_MIS_STOPMIS_M 0x00000004
#define I2CS_MIS_STOPMIS_S 2
#define I2CS_MIS_STARTMIS 0x00000002 // Start condition masked
// interrupt status 1: An unmasked
// START condition interrupt is
// pending. 0: An interrupt has not
// occurred or is masked. This bit
// is cleared by writing 1 to the
// STARTIC bit in the I2CSICR
// register.
#define I2CS_MIS_STARTMIS_M 0x00000002
#define I2CS_MIS_STARTMIS_S 1
#define I2CS_MIS_DATAMIS 0x00000001 // Data masked interrupt status 1:
// An unmasked data received or
// data requested interrupt is
// pending. 0: An interrupt has not
// occurred or is masked. This bit
// is cleared by writing 1 to the
// DATAIC bit in the I2CSICR
// register.
#define I2CS_MIS_DATAMIS_M 0x00000001
#define I2CS_MIS_DATAMIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the I2CS_ICR register.
//
//*****************************************************************************
#define I2CS_ICR_STOPIC 0x00000004 // Stop condition interrupt clear
// Writing 1 to this bit clears the
// STOPRIS bit in the I2CSRIS
// register and the STOPMIS bit in
// the I2CSMIS register. A read of
// this register returns no
// meaningful data.
#define I2CS_ICR_STOPIC_M 0x00000004
#define I2CS_ICR_STOPIC_S 2
#define I2CS_ICR_STARTIC 0x00000002 // Start condition interrupt vlear
// Writing 1 to this bit clears the
// STARTRIS bit in the I2CSRIS
// register and the STARTMIS bit in
// the I2CSMIS register. A read of
// this register returns no
// meaningful data.
#define I2CS_ICR_STARTIC_M 0x00000002
#define I2CS_ICR_STARTIC_S 1
#define I2CS_ICR_DATAIC 0x00000001 // Data interrupt clear Writing 1
// to this bit clears the DATARIS
// bit in the I2CSRIS register and
// the DATAMIS bit in the I2CSMIS
// register. A read of this
// register returns no meaningful
// data.
#define I2CS_ICR_DATAIC_M 0x00000001
#define I2CS_ICR_DATAIC_S 0
#endif // __HW_I2CS_H__

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/******************************************************************************
* Filename: hw_ints.h
* Revised: $Date: 2013-04-29 09:49:55 +0200 (Mon, 29 Apr 2013) $
* Revision: $Revision: 9923 $
*
* Description: Macros that define the interrupt assignment on Stellaris.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_INTS_H__
#define __HW_INTS_H__
// Note: Use the following define if alternate interrupt map is to be used.
// This map is smaller. The function IntAltMapEnable() must be called
// to enable The alternate map.
// #define CC2538_USE_ALTERNATE_INTERRUPT_MAP 1
//*****************************************************************************
//
// The following are defines for the fault assignments.
//
//*****************************************************************************
#define FAULT_NMI 2 // NMI fault
#define FAULT_HARD 3 // Hard fault
#define FAULT_MPU 4 // MPU fault
#define FAULT_BUS 5 // Bus fault
#define FAULT_USAGE 6 // Usage fault
#define FAULT_SVCALL 11 // SVCall
#define FAULT_DEBUG 12 // Debug monitor
#define FAULT_PENDSV 14 // PendSV
#define FAULT_SYSTICK 15 // System Tick
//*****************************************************************************
//
// The following are defines for the interrupt assignments.
//
//*****************************************************************************
#define INT_GPIOA 16 // GPIO Port A
#define INT_GPIOB 17 // GPIO Port B
#define INT_GPIOC 18 // GPIO Port C
#define INT_GPIOD 19 // GPIO Port D
// 20 not in use
#define INT_UART0 21 // UART0 Rx and Tx
#define INT_UART1 22 // UART1 Rx and Tx
#define INT_SSI0 23 // SSI0 Rx and Tx
#define INT_I2C0 24 // I2C0 Master and Slave
// 25 - 29 not in use
#define INT_ADC0 30 // ADC0 Sequence 0
// 31 - 33 not in use
#define INT_WATCHDOG 34 // Watchdog timer
#define INT_WATCHDOG0 34 // Watchdog Timer0
#define INT_TIMER0A 35 // Timer 0 subtimer A
#define INT_TIMER0B 36 // Timer 0 subtimer B
#define INT_TIMER1A 37 // Timer 1 subtimer A
#define INT_TIMER1B 38 // Timer 1 subtimer B
#define INT_TIMER2A 39 // Timer 2 subtimer A
#define INT_TIMER2B 40 // Timer 2 subtimer B
#define INT_COMP0 41 // Analog Comparator 0
// 42 - 44 only in use for alternate map
#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_RFCORERTX 42 // RFCORE RX/TX
#define INT_RFCOREERR 43 // RFCORE Error
#define INT_ICEPICK 44 // Icepick
#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_FLASH 45 // FLASH Control
// 46 - 49 only in use for alternate map
#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_AES 46 // AES
#define INT_PKA 47 // PKA
#define INT_SMTIM 48 // SMTimer
#define INT_MACTIMR 49 // MACTimer
#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_SSI1 50 // SSI1 Rx and Tx
#define INT_TIMER3A 51 // Timer 3 subtimer A
#define INT_TIMER3B 52 // Timer 3 subtimer B
// 53 - 59 not in use
// 60 only in use for alternate map
#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_USB2538 60 // USB new for 2538
#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
// 61 not in use
#define INT_UDMA 62 // uDMA controller
#define INT_UDMAERR 63 // uDMA Error
// 64 - 155 not in use
// 156-162 only in use in basic map
#ifndef CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define INT_USB2538 156 // USB new for 2538
#define INT_RFCORERTX 157 // RFCORE RX/TX
#define INT_RFCOREERR 158 // RFCORE Error
#define INT_AES 159 // AES
#define INT_PKA 160 // PKA
#define INT_SMTIM 161 // SMTimer
#define INT_MACTIMR 162 // MACTimer
#endif // not CC2538_USE_ALTERNATE_INTERRUPT_MAP
//*****************************************************************************
//
// The following are defines for the total number of interrupts.
//
//*****************************************************************************
#ifdef CC2538_USE_ALTERNATE_INTERRUPT_MAP
#define NUM_INTERRUPTS 64
#else
#define NUM_INTERRUPTS 163
#endif // CC2538_USE_ALTERNATE_INTERRUPT_MAP
//*****************************************************************************
//
// The following are defines for the total number of priority levels.
//
//*****************************************************************************
#define NUM_PRIORITY 8
#define NUM_PRIORITY_BITS 3
#endif // __HW_INTS_H__

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/******************************************************************************
* Filename: hw_memmap.h
* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
* Revision: $Revision: 9735 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_MEMMAP_H__
#define __HW_MEMMAP_H__
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals on the top_s interface.
//
//*****************************************************************************
#define ROM_BASE 0x00000000 // ROM
#define FLASH_BASE 0x00200000 // Flash
#define SRAM_BASE 0x20000000 // SRAM
#define SRAM_LL_BASE 0x20004000 // SRAM_LL
#define SSI0_BASE 0x40008000 // SSI
#define SSI1_BASE 0x40009000 // SSI
#define UART0_BASE 0x4000C000 // UART
#define UART1_BASE 0x4000D000 // UART
#define I2C_M0_BASE 0x40020000 // I2CM
#define I2C_S0_BASE 0x40020800 // I2CS
#define GPTIMER0_BASE 0x40030000 // GPTIMER
#define GPTIMER1_BASE 0x40031000 // GPTIMER
#define GPTIMER2_BASE 0x40032000 // GPTIMER
#define GPTIMER3_BASE 0x40033000 // GPTIMER
#define RFCORE_RAM_BASE 0x40088000 // SRAM_RFCORE
#define FRMF_SRCM_RAM_BASE 0x40088400 // SRAM_FRMF_SRCM
#define RFCORE_FFSM_BASE 0x40088500 // RFCORE_FFSM
#define RFCORE_XREG_BASE 0x40088600 // RFCORE_XREG
#define RFCORE_SFR_BASE 0x40088800 // RFCORE_SFR
#define USB_BASE 0x40089000 // USB
#define AES_BASE 0x4008B000 // AES
#define SYS_CTRL_BASE 0x400D2000 // SYS_CTRL
#define FLASH_CTRL_BASE 0x400D3000 // FLASH_CTRL
#define IOC_BASE 0x400D4000 // IOC
#define SMWDTHROSC_BASE 0x400D5000 // SMWDTHROSC
#define ANA_REGS_BASE 0x400D6000 // ANA_REGS
#define SOC_ADC_BASE 0x400D7000 // SOC_ADC
#define GPIO_A_BASE 0x400D9000 // GPIO
#define GPIO_B_BASE 0x400DA000 // GPIO
#define GPIO_C_BASE 0x400DB000 // GPIO
#define GPIO_D_BASE 0x400DC000 // GPIO
#define uDMA_BASE 0x400FF000 // UDMA
#define ST_TESTCTRL_BASE 0x40110000 // STTEST
#define PKA_BASE 0x44004000 // PKA
#define PKA_RAM_BASE 0x44006000 // SRAM_PKA
#define CC_TESTCTRL_BASE 0x44010000 // CCTEST
#endif // __HW_MEMMAP_H__

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/******************************************************************************
* Filename: hw_pka.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_PKA_H__
#define __HW_PKA_H__
//*****************************************************************************
//
// The following are defines for the PKA register offsets.
//
//*****************************************************************************
#define PKA_APTR 0x44004000 // PKA vector A address During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_BPTR 0x44004004 // PKA vector B address During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_CPTR 0x44004008 // PKA vector C address During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_DPTR 0x4400400C // PKA vector D address During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_ALENGTH 0x44004010 // PKA vector A length During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_BLENGTH 0x44004014 // PKA vector B length During
// execution of basic PKCP
// operations, this register is
// double buffered and can be
// written with a new value for the
// next operation; when not
// written, the value remains
// intact. During the execution of
// sequencer-controlled complex
// operations, this register may
// not be written and its value is
// undefined at the conclusion of
// the operation. The driver
// software cannot rely on the
// written value to remain intact.
#define PKA_SHIFT 0x44004018 // PKA bit shift value For basic
// PKCP operations, modifying the
// contents of this register is
// made impossible while the
// operation is being performed.
// For the ExpMod-variable and
// ExpMod-CRT operations, this
// register is used to indicate the
// number of odd powers to use
// (directly as a value in the
// range 1-16). For the ModInv and
// ECC operations, this register is
// used to hold a completion code.
#define PKA_FUNCTION 0x4400401C // PKA function This register
// contains the control bits to
// start basic PKCP as well as
// complex sequencer operations.
// The run bit can be used to poll
// for the completion of the
// operation. Modifying bits [11:0]
// is made impossible during the
// execution of a basic PKCP
// operation. During the execution
// of sequencer-controlled complex
// operations, this register is
// modified; the run and stall
// result bits are set to zero at
// the conclusion, but other bits
// are undefined. Attention:
// Continuously reading this
// register to poll the run bit is
// not allowed when executing
// complex sequencer operations
// (the sequencer cannot access the
// PKCP when this is done). Leave
// at least one sysclk cycle
// between poll operations.
#define PKA_COMPARE 0x44004020 // PKA compare result This
// register provides the result of
// a basic PKCP compare operation.
// It is updated when the run bit
// in the PKA_FUNCTION register is
// reset at the end of that
// operation. Status after a
// complex sequencer operation is
// unknown
#define PKA_MSW 0x44004024 // PKA most-significant-word of
// result vector This register
// indicates the (word) address in
// the PKA RAM where the most
// significant nonzero 32-bit word
// of the result is stored. Should
// be ignored for modulo
// operations. For basic PKCP
// operations, this register is
// updated when the run bit in the
// PKA_FUNCTION register is reset
// at the end of the operation. For
// the complex-sequencer controlled
// operations, updating of the
// final value matching the actual
// result is done near the end of
// the operation; note that the
// result is only meaningful if no
// errors were detected and that
// for ECC operations, the PKA_MSW
// register will provide
// information for the x-coordinate
// of the result point only.
#define PKA_DIVMSW 0x44004028 // PKA most-significant-word of
// divide remainder This register
// indicates the (32-bit word)
// address in the PKA RAM where the
// most significant nonzero 32-bit
// word of the remainder result for
// the basic divide and modulo
// operations is stored. Bits [4:0]
// are loaded with the bit number
// of the most-significant nonzero
// bit in the most-significant
// nonzero word when MS one control
// bit is set. For divide, modulo,
// and MS one reporting, this
// register is updated when the RUN
// bit in the PKA_FUNCTION register
// is reset at the end of the
// operation. For the complex
// sequencer controlled operations,
// updating of bits [4:0] of this
// register with the
// most-significant bit location of
// the actual result is done near
// the end of the operation. The
// result is meaningful only if no
// errors were detected and that
// for ECC operations; the
// PKA_DIVMSW register provides
// information for the x-coordinate
// of the result point only.
#define PKA_SEQ_CTRL 0x440040C8 // PKA sequencer control and
// status register The sequencer is
// interfaced with the outside
// world through a single control
// and status register. With the
// exception of bit [31], the
// actual use of bits in the
// separate sub-fields of this
// register is determined by the
// sequencer firmware. This
// register need only be accessed
// when the sequencer program is
// stored in RAM. The reset value
// of the RESTE bit depends upon
// the option chosen for sequencer
// program storage.
#define PKA_OPTIONS 0x440040F4 // PKA hardware options register
// This register provides the host
// with a means to determine the
// hardware configuration
// implemented in this PKA engine,
// focused on options that have an
// effect on software interacting
// with the module. Note: (32 x
// (1st LNME nr. of PEs + 1st LNME
// FIFO RAM depth - 10)) equals the
// maximum modulus vector length
// (in bits) that can be handled by
// the modular exponentiation and
// ECC operations executed on a PKA
// engine that includes an LNME.
#define PKA_SW_REV 0x440040F8 // PKA firmware revision and
// capabilities register This
// register allows the host access
// to the internal firmware
// revision number of the PKA
// Engine for software driver
// matching and diagnostic
// purposes. This register also
// contains a field that encodes
// the capabilities of the embedded
// firmware. The PKA_SW_REV
// register is written by the
// firmware within a few clock
// cycles after starting up that
// firmware. The hardware reset
// value is zero, indicating that
// the information has not been
// written yet.
#define PKA_REVISION 0x440040FC // PKA hardware revision register
// This register allows the host
// access to the hardware revision
// number of the PKA engine for
// software driver matching and
// diagnostic purposes. It is
// always located at the highest
// address in the access space of
// the module and contains an
// encoding of the EIP number (with
// its complement as signature) for
// recognition of the hardware
// module.
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_APTR register.
//
//*****************************************************************************
#define PKA_APTR_APTR_M 0x000007FF // This register specifies the
// location of vector A within the
// PKA RAM. Vectors are identified
// through the location of their
// least-significant 32-bit word.
// Note that bit [0] must be zero
// to ensure that the vector starts
// at an 8-byte boundary.
#define PKA_APTR_APTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_BPTR register.
//
//*****************************************************************************
#define PKA_BPTR_BPTR_M 0x000007FF // This register specifies the
// location of vector B within the
// PKA RAM. Vectors are identified
// through the location of their
// least-significant 32-bit word.
// Note that bit [0] must be zero
// to ensure that the vector starts
// at an 8-byte boundary.
#define PKA_BPTR_BPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_CPTR register.
//
//*****************************************************************************
#define PKA_CPTR_CPTR_M 0x000007FF // This register specifies the
// location of vector C within the
// PKA RAM. Vectors are identified
// through the location of their
// least-significant 32-bit word.
// Note that bit [0] must be zero
// to ensure that the vector starts
// at an 8-byte boundary.
#define PKA_CPTR_CPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_DPTR register.
//
//*****************************************************************************
#define PKA_DPTR_DPTR_M 0x000007FF // This register specifies the
// location of vector D within the
// PKA RAM. Vectors are identified
// through the location of their
// least-significant 32-bit word.
// Note that bit [0] must be zero
// to ensure that the vector starts
// at an 8-byte boundary.
#define PKA_DPTR_DPTR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_ALENGTH register.
//
//*****************************************************************************
#define PKA_ALENGTH_ALENGTH_M 0x000001FF // This register specifies the
// length (in 32-bit words) of
// Vector A.
#define PKA_ALENGTH_ALENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_BLENGTH register.
//
//*****************************************************************************
#define PKA_BLENGTH_BLENGTH_M 0x000001FF // This register specifies the
// length (in 32-bit words) of
// Vector B.
#define PKA_BLENGTH_BLENGTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_SHIFT register.
//
//*****************************************************************************
#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M \
0x0000001F // This register specifies the
// number of bits to shift the
// input vector (in the range 0-31)
// during a Rshift or Lshift
// operation.
#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_FUNCTION register.
//
//*****************************************************************************
#define PKA_FUNCTION_STALL_RESULT \
0x01000000 // When written with a 1b,
// updating of the PKA_COMPARE,
// PKA_MSW and PKA_DIVMSW
// registers, as well as resetting
// the run bit is stalled beyond
// the point that a running
// operation is actually finished.
// Use this to allow software
// enough time to read results from
// a previous operation when the
// newly started operation is known
// to take only a short amount of
// time. If a result is waiting,
// the result registers is updated
// and the run bit is reset in the
// clock cycle following writing
// the stall result bit back to 0b.
// The Stall result function may
// only be used for basic PKCP
// operations.
#define PKA_FUNCTION_STALL_RESULT_M \
0x01000000
#define PKA_FUNCTION_STALL_RESULT_S 24
#define PKA_FUNCTION_RUN 0x00008000 // The host sets this bit to
// instruct the PKA module to begin
// processing the basic PKCP or
// complex sequencer operation.
// This bit is reset low
// automatically when the operation
// is complete. The complement of
// this bit is output as
// interrupts[1]. After a reset,
// the run bit is always set to 1b.
// Depending on the option, program
// ROM or program RAM, the
// following applies: Program ROM -
// The first sequencer instruction
// sets the bit to 0b. This is done
// immediately after the hardware
// reset is released. Program RAM -
// The sequencer must set the bit
// to 0b. As a valid firmware may
// not have been loaded, the
// sequencer is held in software
// reset after the hardware reset
// is released (the reset bit in
// PKA_SEQ_CRTL is set to 1b).
// After the FW image is loaded and
// the Reset bit is cleared, the
// sequencer starts to execute the
// FW. The first instruction clears
// the run bit. In both cases a few
// clock cycles are needed before
// the first instruction is
// executed and the run bit state
// has been propagated.
#define PKA_FUNCTION_RUN_M 0x00008000
#define PKA_FUNCTION_RUN_S 15
#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M \
0x00007000 // These bits select the complex
// sequencer operation to perform:
// 000b: None 001b: ExpMod-CRT
// 010b: ExpMod-ACT4 (compatible
// with EIP2315) 011b: ECC-ADD (if
// available in firmware, otherwise
// reserved) 100b: ExpMod-ACT2
// (compatible with EIP2316) 101b:
// ECC-MUL (if available in
// firmware, otherwise reserved)
// 110b: ExpMod-variable 111b:
// ModInv (if available in
// firmware, otherwise reserved)
// The encoding of these operations
// is determined by sequencer
// firmware.
#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12
#define PKA_FUNCTION_COPY 0x00000800 // Perform copy operation
#define PKA_FUNCTION_COPY_M 0x00000800
#define PKA_FUNCTION_COPY_S 11
#define PKA_FUNCTION_COMPARE 0x00000400 // Perform compare operation
#define PKA_FUNCTION_COMPARE_M 0x00000400
#define PKA_FUNCTION_COMPARE_S 10
#define PKA_FUNCTION_MODULO 0x00000200 // Perform modulo operation
#define PKA_FUNCTION_MODULO_M 0x00000200
#define PKA_FUNCTION_MODULO_S 9
#define PKA_FUNCTION_DIVIDE 0x00000100 // Perform divide operation
#define PKA_FUNCTION_DIVIDE_M 0x00000100
#define PKA_FUNCTION_DIVIDE_S 8
#define PKA_FUNCTION_LSHIFT 0x00000080 // Perform left shift operation
#define PKA_FUNCTION_LSHIFT_M 0x00000080
#define PKA_FUNCTION_LSHIFT_S 7
#define PKA_FUNCTION_RSHIFT 0x00000040 // Perform right shift operation
#define PKA_FUNCTION_RSHIFT_M 0x00000040
#define PKA_FUNCTION_RSHIFT_S 6
#define PKA_FUNCTION_SUBTRACT 0x00000020 // Perform subtract operation
#define PKA_FUNCTION_SUBTRACT_M 0x00000020
#define PKA_FUNCTION_SUBTRACT_S 5
#define PKA_FUNCTION_ADD 0x00000010 // Perform add operation
#define PKA_FUNCTION_ADD_M 0x00000010
#define PKA_FUNCTION_ADD_S 4
#define PKA_FUNCTION_MS_ONE 0x00000008 // Loads the location of the Most
// Significant one bit within the
// result word indicated in the
// PKA_MSW register into bits [4:0]
// of the PKA_DIVMSW register - can
// only be used with basic PKCP
// operations, except for Divide,
// Modulo and Compare.
#define PKA_FUNCTION_MS_ONE_M 0x00000008
#define PKA_FUNCTION_MS_ONE_S 3
#define PKA_FUNCTION_ADDSUB 0x00000002 // Perform combined add/subtract
// operation
#define PKA_FUNCTION_ADDSUB_M 0x00000002
#define PKA_FUNCTION_ADDSUB_S 1
#define PKA_FUNCTION_MULTIPLY 0x00000001 // Perform multiply operation
#define PKA_FUNCTION_MULTIPLY_M 0x00000001
#define PKA_FUNCTION_MULTIPLY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_COMPARE register.
//
//*****************************************************************************
#define PKA_COMPARE_A_GREATER_THAN_B \
0x00000004 // Vector_A is greater than
// Vector_B
#define PKA_COMPARE_A_GREATER_THAN_B_M \
0x00000004
#define PKA_COMPARE_A_GREATER_THAN_B_S 2
#define PKA_COMPARE_A_LESS_THAN_B \
0x00000002 // Vector_A is less than Vector_B
#define PKA_COMPARE_A_LESS_THAN_B_M \
0x00000002
#define PKA_COMPARE_A_LESS_THAN_B_S 1
#define PKA_COMPARE_A_EQUALS_B 0x00000001 // Vector_A is equal to Vector_B
#define PKA_COMPARE_A_EQUALS_B_M \
0x00000001
#define PKA_COMPARE_A_EQUALS_B_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_MSW register.
//
//*****************************************************************************
#define PKA_MSW_RESULT_IS_ZERO 0x00008000 // The result vector is all
// zeroes, ignore the address
// returned in bits [10:0]
#define PKA_MSW_RESULT_IS_ZERO_M \
0x00008000
#define PKA_MSW_RESULT_IS_ZERO_S 15
#define PKA_MSW_MSW_ADDRESS_M 0x000007FF // Address of the most-significant
// nonzero 32-bit word of the
// result vector in PKA RAM
#define PKA_MSW_MSW_ADDRESS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_DIVMSW register.
//
//*****************************************************************************
#define PKA_DIVMSW_RESULT_IS_ZERO \
0x00008000 // The result vector is all
// zeroes, ignore the address
// returned in bits [10:0]
#define PKA_DIVMSW_RESULT_IS_ZERO_M \
0x00008000
#define PKA_DIVMSW_RESULT_IS_ZERO_S 15
#define PKA_DIVMSW_MSW_ADDRESS_M \
0x000007FF // Address of the most significant
// nonzero 32-bit word of the
// remainder result vector in PKA
// RAM
#define PKA_DIVMSW_MSW_ADDRESS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_SEQ_CTRL register.
//
//*****************************************************************************
#define PKA_SEQ_CTRL_RESET 0x80000000 // Option program ROM: Reset value
// = 0. Read/Write, reset value 0b
// (ZERO). Writing 1b resets the
// sequencer, write to 0b to
// restart operations again. As the
// reset value is 0b, the sequencer
// will automatically start
// operations executing from
// program ROM. This bit should
// always be written with zero and
// ignored when reading this
// register. Option Program RAM:
// Reset value =1. Read/Write,
// reset value 1b (ONE). When 1b,
// the sequencer is held in a reset
// state and the PKA_PROGRAM area
// is accessible for loading the
// sequencer program (while the
// PKA_DATA_RAM is inaccessible),
// write to 0b to (re)start
// sequencer operations and disable
// PKA_PROGRAM area accessibility
// (also enables the PKA_DATA_RAM
// accesses). Resetting the
// sequencer (in order to load
// other firmware) should only be
// done when the PKA Engine is not
// performing any operations (i.e.
// the run bit in the PKA_FUNCTION
// register should be zero).
#define PKA_SEQ_CTRL_RESET_M 0x80000000
#define PKA_SEQ_CTRL_RESET_S 31
#define PKA_SEQ_CTRL_SEQUENCER_STATUS_M \
0x0000FF00 // These read-only bits can be
// used by the sequencer to
// communicate status to the
// outside world. Bit [8] is also
// used as sequencer interrupt,
// with the complement of this bit
// ORed into the run bit in
// PKA_FUNCTION. This field should
// always be written with zeroes
// and ignored when reading this
// register.
#define PKA_SEQ_CTRL_SEQUENCER_STATUS_S 8
#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_M \
0x000000FF // These bits can be used by
// software to trigger sequencer
// operations. External logic can
// set these bits by writing 1b,
// cannot reset them by writing 0b.
// The sequencer can reset these
// bits by writing 0b, cannot set
// them by writing 1b. Setting the
// run bit in PKA_FUNCTION together
// with a nonzero sequencer
// operations field automatically
// sets bit [0] here. This field
// should always be written with
// zeroes and ignored when reading
// this register.
#define PKA_SEQ_CTRL_SW_CONTROL_STATUS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_OPTIONS register.
//
//*****************************************************************************
#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_M \
0xFF000000 // Number of words in the first
// LNME's FIFO RAM Should be
// ignored if LNME configuration is
// 0. The contents of this field
// indicate the actual depth as
// selected by the LNME FIFO RAM
// size strap input, fifo_size_sel.
// Note: Reset value is undefined
#define PKA_OPTIONS_FIRST_LNME_FIFO_DEPTH_S 24
#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_M \
0x003F0000 // Number of processing elements
// in the pipeline of the first
// LNME Should be ignored if LNME
// configuration is 0. Note: Reset
// value is undefined.
#define PKA_OPTIONS_FIRST_LNME_NR_OF_PES_S 16
#define PKA_OPTIONS_MMM3A 0x00001000 // Reserved for a future
// functional extension to the LNME
// Always 0b
#define PKA_OPTIONS_MMM3A_M 0x00001000
#define PKA_OPTIONS_MMM3A_S 12
#define PKA_OPTIONS_INT_MASKING 0x00000800 // Value 0b indicates that the
// main interrupt output (bit [1]
// of the interrupts output bus) is
// the direct complement of the run
// bit in the PKA_CONTROL register,
// value 1b indicates that
// interrupt masking logic is
// present for this output. Note:
// Reset value is undefined
#define PKA_OPTIONS_INT_MASKING_M \
0x00000800
#define PKA_OPTIONS_INT_MASKING_S 11
#define PKA_OPTIONS_PROTECTION_OPTION_M \
0x00000700 // Value 0 indicates no additional
// protection against side channel
// attacks, value 1 indicates the
// SCAP option, value 3 indicates
// the PROT option; other values
// are reserved. Note: Reset value
// is undefined
#define PKA_OPTIONS_PROTECTION_OPTION_S 8
#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 // Value 1b indicates sequencer
// program storage in RAM, value 0b
// in ROM. Note: Reset value is
// undefined
#define PKA_OPTIONS_PROGRAM_RAM_M \
0x00000080
#define PKA_OPTIONS_PROGRAM_RAM_S 7
#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M \
0x00000060 // Value 1 indicates a standard
// sequencer; other values are
// reserved.
#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5
#define PKA_OPTIONS_LNME_CONFIGURATION_M \
0x0000001C // Value 0 indicates NO LNME,
// value 1 indicates one standard
// LNME (with alpha = 32, beta =
// 8); other values reserved. Note:
// Reset value is undefined
#define PKA_OPTIONS_LNME_CONFIGURATION_S 2
#define PKA_OPTIONS_PKCP_CONFIGURATION_M \
0x00000003 // Value 1 indicates a PKCP with a
// 16x16 multiplier, value 2
// indicates a PKCP with a 32x32
// multiplier, other values
// reserved. Note: Reset value is
// undefined.
#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_SW_REV register.
//
//*****************************************************************************
#define PKA_SW_REV_FW_CAPABILITIES_M \
0xF0000000 // 4-bit binary encoding for the
// functionality implemented in the
// firmware. Value 0 indicates
// basic ModExp with/without CRT.
// Value 1 adds Modular Inversion,
// value 2 adds Modular Inversion
// and ECC operations. Values 3-15
// are reserved.
#define PKA_SW_REV_FW_CAPABILITIES_S 28
#define PKA_SW_REV_MAJOR_FW_REVISION_M \
0x0F000000 // 4-bit binary encoding of the
// major firmware revision number
#define PKA_SW_REV_MAJOR_FW_REVISION_S 24
#define PKA_SW_REV_MINOR_FW_REVISION_M \
0x00F00000 // 4-bit binary encoding of the
// minor firmware revision number
#define PKA_SW_REV_MINOR_FW_REVISION_S 20
#define PKA_SW_REV_FW_PATCH_LEVEL_M \
0x000F0000 // 4-bit binary encoding of the
// firmware patch level, initial
// release will carry value zero
// Patches are used to remove bugs
// without changing the
// functionality or interface of a
// module.
#define PKA_SW_REV_FW_PATCH_LEVEL_S 16
//*****************************************************************************
//
// The following are defines for the bit fields in the PKA_REVISION register.
//
//*****************************************************************************
#define PKA_REVISION_MAJOR_HW_REVISION_M \
0x0F000000 // 4-bit binary encoding of the
// major hardware revision number
#define PKA_REVISION_MAJOR_HW_REVISION_S 24
#define PKA_REVISION_MINOR_HW_REVISION_M \
0x00F00000 // 4-bit binary encoding of the
// minor hardware revision number
#define PKA_REVISION_MINOR_HW_REVISION_S 20
#define PKA_REVISION_HW_PATCH_LEVEL_M \
0x000F0000 // 4-bit binary encoding of the
// hardware patch level, initial
// release will carry value zero
// Patches are used to remove bugs
// without changing the
// functionality or interface of a
// module.
#define PKA_REVISION_HW_PATCH_LEVEL_S 16
#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_M \
0x0000FF00 // Bit-by-bit logic complement of
// bits [7:0], EIP-28 gives 0xE3
#define PKA_REVISION_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8
#define PKA_REVISION_BASIC_EIP_NUMBER_M \
0x000000FF // 8-bit binary encoding of the
// EIP number, EIP-28 gives 0x1C
#define PKA_REVISION_BASIC_EIP_NUMBER_S 0
#endif // __HW_PKA_H__

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/******************************************************************************
* Filename: hw_rfcore_ffsm.h
* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
* Revision: $Revision: 9735 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_RFCORE_FFSM_H__
#define __HW_RFCORE_FFSM_H__
//*****************************************************************************
//
// The following are defines for the RFCORE_FFSM register offsets.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCRESMASK0 \
0x40088580 // Source address matching result
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCRESMASK1 \
0x40088584 // Source address matching result
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCRESMASK2 \
0x40088588 // Source address matching result
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCRESINDEX \
0x4008858C // Source address matching result
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCEXTPENDEN0 \
0x40088590 // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCEXTPENDEN1 \
0x40088594 // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCEXTPENDEN2 \
0x40088598 // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCSHORTPENDEN0 \
0x4008859C // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCSHORTPENDEN1 \
0x400885A0 // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_SRCSHORTPENDEN2 \
0x400885A4 // Source address matching control
// This register is stored in RAM;
// the reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR0 0x400885A8 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR1 0x400885AC // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR2 0x400885B0 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR3 0x400885B4 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR4 0x400885B8 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR5 0x400885BC // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR6 0x400885C0 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_EXT_ADDR7 0x400885C4 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_PAN_ID0 0x400885C8 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_PAN_ID1 0x400885CC // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_SHORT_ADDR0 \
0x400885D0 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
#define RFCORE_FFSM_SHORT_ADDR1 \
0x400885D4 // Local address information This
// register is stored in RAM; the
// reset value is undefined.
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCRESMASK0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCRESMASK0_SRCRESMASK0_M \
0x000000FF // Extended address matching When
// there is a match on entry ext_n,
// bits 2n and 2n + 1 are set in
// SRCRESMASK.
#define RFCORE_FFSM_SRCRESMASK0_SRCRESMASK0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCRESMASK1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCRESMASK1_SRCRESMASK1_M \
0x000000FF // Short address matching When
// there is a match on entry
// panid_n + short_n, bit n is set
// in SRCRESMASK.
#define RFCORE_FFSM_SRCRESMASK1_SRCRESMASK1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCRESMASK2 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCRESMASK2_SRCRESMASK2_M \
0x000000FF // 24-bit mask that indicates
// source address match for each
// individual entry in the source
// address table
#define RFCORE_FFSM_SRCRESMASK2_SRCRESMASK2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCRESINDEX register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCRESINDEX_SRCRESINDEX_M \
0x000000FF // The bit index of the
// least-significant entry (0-23
// for short addresses or 0-11 for
// extended addresses) in
// SRCRESMASK, or 0x3F when there
// is no source match On a match,
// bit 5 is 0 when the match is on
// a short address and 1 when it is
// on an extended address. On a
// match, bit 6 is 1 when the
// conditions for automatic pending
// bit in acknowledgment have been
// met (see the description of
// SRCMATCH.AUTOPEND). The bit does
// not indicate if the
// acknowledgment is actually
// transmitted, and does not
// consider the PENDING_OR register
// bit and the SACK/SACKPEND/SNACK
// strobes.
#define RFCORE_FFSM_SRCRESINDEX_SRCRESINDEX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCEXTPENDEN0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCEXTPENDEN0_SRCEXTPENDEN0_M \
0x000000FF // 8 LSBs of the 24-bit mask that
// enables or disables automatic
// pending for each of the 12
// extended addresses. Entry n is
// mapped to SRCEXTPENDEN[2n]. All
// SRCEXTPENDEN[2n + 1] bits are
// don't care.
#define RFCORE_FFSM_SRCEXTPENDEN0_SRCEXTPENDEN0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCEXTPENDEN1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCEXTPENDEN1_SRCEXTPENDEN1_M \
0x000000FF // 8 middle bits of the 24-bit
// mask that enables or disables
// automatic pending for each of
// the 12 extended addresses Entry
// n is mapped to SRCEXTPENDEN[2n].
// All SRCEXTPENDEN[2n + 1] bits
// are don't care.
#define RFCORE_FFSM_SRCEXTPENDEN1_SRCEXTPENDEN1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCEXTPENDEN2 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCEXTPENDEN2_SRCEXTPENDEN2_M \
0x000000FF // 8 MSBs of the 24-bit mask that
// enables or disables automatic
// pending for each of the 12
// extended addresses Entry n is
// mapped to SRCEXTPENDEN[2n]. All
// SRCEXTPENDEN[2n + 1] bits are
// don't care.
#define RFCORE_FFSM_SRCEXTPENDEN2_SRCEXTPENDEN2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCSHORTPENDEN0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCSHORTPENDEN0_SRCSHORTPENDEN0_M \
0x000000FF // 8 LSBs of the 24-bit mask that
// enables or disables automatic
// pending for each of the 24 short
// addresses
#define RFCORE_FFSM_SRCSHORTPENDEN0_SRCSHORTPENDEN0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCSHORTPENDEN1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCSHORTPENDEN1_SRCSHORTPENDEN1_M \
0x000000FF // 8 middle bits of the 24-bit
// mask that enables or disables
// automatic pending for each of
// the 24 short addresses
#define RFCORE_FFSM_SRCSHORTPENDEN1_SRCSHORTPENDEN1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SRCSHORTPENDEN2 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SRCSHORTPENDEN2_SRCSHORTPENDEN2_M \
0x000000FF // 8 MSBs of the 24-bit mask that
// enables or disables automatic
// pending for each of the 24 short
// addresses
#define RFCORE_FFSM_SRCSHORTPENDEN2_SRCSHORTPENDEN2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR0_EXT_ADDR0_M \
0x000000FF // EXT_ADDR[7:0] The IEEE extended
// address used during destination
// address filtering
#define RFCORE_FFSM_EXT_ADDR0_EXT_ADDR0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR1_EXT_ADDR1_M \
0x000000FF // EXT_ADDR[15:8] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR1_EXT_ADDR1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR2 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR2_EXT_ADDR2_M \
0x000000FF // EXT_ADDR[23:16] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR2_EXT_ADDR2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR3 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR3_EXT_ADDR3_M \
0x000000FF // EXT_ADDR[31:24] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR3_EXT_ADDR3_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR4 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR4_EXT_ADDR4_M \
0x000000FF // EXT_ADDR[39:32] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR4_EXT_ADDR4_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR5 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR5_EXT_ADDR5_M \
0x000000FF // EXT_ADDR[47:40] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR5_EXT_ADDR5_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR6 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR6_EXT_ADDR6_M \
0x000000FF // EXT_ADDR[55:48] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR6_EXT_ADDR6_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_EXT_ADDR7 register.
//
//*****************************************************************************
#define RFCORE_FFSM_EXT_ADDR7_EXT_ADDR7_M \
0x000000FF // EXT_ADDR[63:56] The IEEE
// extended address used during
// destination address filtering
#define RFCORE_FFSM_EXT_ADDR7_EXT_ADDR7_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_PAN_ID0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_PAN_ID0_PAN_ID0_M \
0x000000FF // PAN_ID[7:0] The PAN ID used
// during destination address
// filtering
#define RFCORE_FFSM_PAN_ID0_PAN_ID0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_PAN_ID1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_PAN_ID1_PAN_ID1_M \
0x000000FF // PAN_ID[15:8] The PAN ID used
// during destination address
// filtering
#define RFCORE_FFSM_PAN_ID1_PAN_ID1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SHORT_ADDR0 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SHORT_ADDR0_SHORT_ADDR0_M \
0x000000FF // SHORT_ADDR[7:0] The short
// address used during destination
// address filtering
#define RFCORE_FFSM_SHORT_ADDR0_SHORT_ADDR0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_FFSM_SHORT_ADDR1 register.
//
//*****************************************************************************
#define RFCORE_FFSM_SHORT_ADDR1_SHORT_ADDR1_M \
0x000000FF // SHORT_ADDR[15:8] The short
// address used during destination
// address filtering
#define RFCORE_FFSM_SHORT_ADDR1_SHORT_ADDR1_S 0
#endif // __HW_RFCORE_FFSM_H__

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/******************************************************************************
* Filename: hw_rfcore_sfr.h
* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
* Revision: $Revision: 9735 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_RFCORE_SFR_H__
#define __HW_RFCORE_SFR_H__
//*****************************************************************************
//
// The following are defines for the RFCORE_SFR register offsets.
//
//*****************************************************************************
#define RFCORE_SFR_MTCSPCFG 0x40088800 // MAC Timer event configuration
#define RFCORE_SFR_MTCTRL 0x40088804 // MAC Timer control register
#define RFCORE_SFR_MTIRQM 0x40088808 // MAC Timer interrupt mask
#define RFCORE_SFR_MTIRQF 0x4008880C // MAC Timer interrupt flags
#define RFCORE_SFR_MTMSEL 0x40088810 // MAC Timer multiplex select
#define RFCORE_SFR_MTM0 0x40088814 // MAC Timer multiplexed register
// 0
#define RFCORE_SFR_MTM1 0x40088818 // MAC Timer multiplexed register
// 1
#define RFCORE_SFR_MTMOVF2 0x4008881C // MAC Timer multiplexed overflow
// register 2
#define RFCORE_SFR_MTMOVF1 0x40088820 // MAC Timer multiplexed overflow
// register 1
#define RFCORE_SFR_MTMOVF0 0x40088824 // MAC Timer multiplexed overflow
// register 0
#define RFCORE_SFR_RFDATA 0x40088828 // The TX FIFO and RX FIFO may be
// accessed through this register.
// Data is written to the TX FIFO
// when writing to the RFD
// register. Data is read from the
// RX FIFO when the RFD register is
// read. The XREG registers
// RXFIFOCNT and TXFIFOCNT provide
// information on the amount of
// data in the FIFOs. The FIFO
// contents can be cleared by
// issuing SFLUSHRX and SFLUSHTX.
#define RFCORE_SFR_RFERRF 0x4008882C // RF error interrupt flags
#define RFCORE_SFR_RFIRQF1 0x40088830 // RF interrupt flags
#define RFCORE_SFR_RFIRQF0 0x40088834 // RF interrupt flags
#define RFCORE_SFR_RFST 0x40088838 // RF CSMA-CA/strobe processor
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTCSPCFG register.
//
//*****************************************************************************
#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENMT_CFG_M \
0x00000070 // Selects the event that triggers
// an MT_EVENT2 pulse 000:
// MT_per_event 001: MT_cmp1_event
// 010: MT_cmp2_event 011:
// MTovf_per_event 100:
// MTovf_cmp1_event 101:
// MTovf_cmp2_event 110: Reserved
// 111: No event
#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENMT_CFG_S 4
#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENT1_CFG_M \
0x00000007 // Selects the event that triggers
// an MT_EVENT1 pulse 000:
// MT_per_event 001: MT_cmp1_event
// 010: MT_cmp2_event 011:
// MTovf_per_event 100:
// MTovf_cmp1_event 101:
// MTovf_cmp2_event 110: Reserved
// 111: No event
#define RFCORE_SFR_MTCSPCFG_MACTIMER_EVENT1_CFG_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTCTRL register.
//
//*****************************************************************************
#define RFCORE_SFR_MTCTRL_LATCH_MODE \
0x00000008 // 0: Reading MTM0 with
// MTMSEL.MTMSEL = 000 latches the
// high byte of the timer, making
// it ready to be read from MTM1.
// Reading MTMOVF0 with
// MTMSEL.MTMOVFSEL = 000 latches
// the two most-significant bytes
// of the overflow counter, making
// it possible to read these from
// MTMOVF1 and MTMOVF2. 1: Reading
// MTM0 with MTMSEL.MTMSEL = 000
// latches the high byte of the
// timer and the entire overflow
// counter at once, making it
// possible to read the values from
// MTM1, MTMOVF0, MTMOVF1, and
// MTMOVF2.
#define RFCORE_SFR_MTCTRL_LATCH_MODE_M \
0x00000008
#define RFCORE_SFR_MTCTRL_LATCH_MODE_S 3
#define RFCORE_SFR_MTCTRL_STATE 0x00000004 // State of MAC Timer 0: Timer
// idle 1: Timer running
#define RFCORE_SFR_MTCTRL_STATE_M \
0x00000004
#define RFCORE_SFR_MTCTRL_STATE_S 2
#define RFCORE_SFR_MTCTRL_SYNC 0x00000002 // 0: Starting and stopping of
// timer is immediate; that is,
// synchronous with clk_rf_32m. 1:
// Starting and stopping of timer
// occurs at the first positive
// edge of the 32-kHz clock. For
// more details regarding timer
// start and stop, see Section
// 22.4.
#define RFCORE_SFR_MTCTRL_SYNC_M \
0x00000002
#define RFCORE_SFR_MTCTRL_SYNC_S 1
#define RFCORE_SFR_MTCTRL_RUN 0x00000001 // Write 1 to start timer, write 0
// to stop timer. When read, it
// returns the last written value.
#define RFCORE_SFR_MTCTRL_RUN_M 0x00000001
#define RFCORE_SFR_MTCTRL_RUN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTIRQM register.
//
//*****************************************************************************
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE2M \
0x00000020 // Enables the
// MACTIMER_OVF_COMPARE2 interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE2M_M \
0x00000020
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE2M_S 5
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE1M \
0x00000010 // Enables the
// MACTIMER_OVF_COMPARE1 interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE1M_M \
0x00000010
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_COMPARE1M_S 4
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_PERM \
0x00000008 // Enables the MACTIMER_OVF_PER
// interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_PERM_M \
0x00000008
#define RFCORE_SFR_MTIRQM_MACTIMER_OVF_PERM_S 3
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE2M \
0x00000004 // Enables the MACTIMER_COMPARE2
// interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE2M_M \
0x00000004
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE2M_S 2
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE1M \
0x00000002 // Enables the MACTIMER_COMPARE1
// interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE1M_M \
0x00000002
#define RFCORE_SFR_MTIRQM_MACTIMER_COMPARE1M_S 1
#define RFCORE_SFR_MTIRQM_MACTIMER_PERM \
0x00000001 // Enables the MACTIMER_PER
// interrupt
#define RFCORE_SFR_MTIRQM_MACTIMER_PERM_M \
0x00000001
#define RFCORE_SFR_MTIRQM_MACTIMER_PERM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTIRQF register.
//
//*****************************************************************************
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE2F \
0x00000020 // Set when the MAC Timer overflow
// counter counts to the value set
// at MTovf_cmp2
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE2F_M \
0x00000020
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE2F_S 5
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE1F \
0x00000010 // Set when the MAC Timer overflow
// counter counts to the value set
// at Timer 2 MTovf_cmp1
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE1F_M \
0x00000010
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_COMPARE1F_S 4
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_PERF \
0x00000008 // Set when the MAC Timer overflow
// counter would have counted to a
// value equal to MTovf_per, but
// instead wraps to 0
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_PERF_M \
0x00000008
#define RFCORE_SFR_MTIRQF_MACTIMER_OVF_PERF_S 3
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE2F \
0x00000004 // Set when the MAC Timer counter
// counts to the value set at
// MT_cmp2
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE2F_M \
0x00000004
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE2F_S 2
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE1F \
0x00000002 // Set when the MAC Timer counter
// counts to the value set at
// MT_cmp1
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE1F_M \
0x00000002
#define RFCORE_SFR_MTIRQF_MACTIMER_COMPARE1F_S 1
#define RFCORE_SFR_MTIRQF_MACTIMER_PERF \
0x00000001 // Set when the MAC Timer counter
// would have counted to a value
// equal to MT_per, but instead
// wraps to 0
#define RFCORE_SFR_MTIRQF_MACTIMER_PERF_M \
0x00000001
#define RFCORE_SFR_MTIRQF_MACTIMER_PERF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTMSEL register.
//
//*****************************************************************************
#define RFCORE_SFR_MTMSEL_MTMOVFSEL_M \
0x00000070 // The value of this register
// selects the internal registers
// that are modified or read when
// accessing MTMOVF0, MTMOVF1, and
// MTMOVF2. 000: MTovf (overflow
// counter) 001: MTovf_cap
// (overflow capture) 010:
// MTovf_per (overflow period) 011:
// MTovf_cmp1 (overflow compare 1)
// 100: MTovf_cmp2 (overflow
// compare 2) 101 to 111: Reserved
#define RFCORE_SFR_MTMSEL_MTMOVFSEL_S 4
#define RFCORE_SFR_MTMSEL_MTMSEL_M \
0x00000007 // The value of this register
// selects the internal registers
// that are modified or read when
// accessing MTM0 and MTM1. 000:
// MTtim (timer count value) 001:
// MT_cap (timer capture) 010:
// MT_per (timer period) 011:
// MT_cmp1 (timer compare 1) 100:
// MT_cmp2 (timer compare 2) 101 to
// 111: Reserved MTM0
#define RFCORE_SFR_MTMSEL_MTMSEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTM0 register.
//
//*****************************************************************************
#define RFCORE_SFR_MTM0_MTM0_M 0x000000FF // Indirectly returns and modifies
// bits [7:0] of an internal
// register depending on the value
// of MTMSEL.MTMSEL. When reading
// the MTM0 register with
// MTMSEL.MTMSEL set to 000 and
// MTCTRL.LATCH_MODE set to 0, the
// timer (MTtim) value is latched.
// When reading the MTM0 register
// with MTMSEL.MTMSEL set to 000
// and MTCTRL.LATCH_MODE set to 1,
// the timer (MTtim) and overflow
// counter (MTovf) values are
// latched.
#define RFCORE_SFR_MTM0_MTM0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTM1 register.
//
//*****************************************************************************
#define RFCORE_SFR_MTM1_MTM1_M 0x000000FF // Indirectly returns and modifies
// bits [15:8] of an internal
// register, depending on the value
// of MTMSEL.MTMSEL. When reading
// the MTM0 register with
// MTMSEL.MTMSEL set to 000, the
// timer (MTtim) value is latched.
// Reading this register with
// MTMSEL.MTMSEL set to 000 returns
// the latched value of
// MTtim[15:8].
#define RFCORE_SFR_MTM1_MTM1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTMOVF2 register.
//
//*****************************************************************************
#define RFCORE_SFR_MTMOVF2_MTMOVF2_M \
0x000000FF // Indirectly returns and modifies
// bits [23:16] of an internal
// register, depending on the value
// of MTMSEL.MTMOVFSEL. Reading
// this register with
// MTMSEL.MTMOVFSEL set to 000
// returns the latched value of
// MTovf[23:16].
#define RFCORE_SFR_MTMOVF2_MTMOVF2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTMOVF1 register.
//
//*****************************************************************************
#define RFCORE_SFR_MTMOVF1_MTMOVF1_M \
0x000000FF // Indirectly returns and modifies
// bits [15:8] of an internal
// register, depending on the value
// of MTMSEL.MTMSEL. Reading this
// register with MTMSEL.MTMOVFSEL
// set to 000 returns the latched
// value of MTovf[15:8].
#define RFCORE_SFR_MTMOVF1_MTMOVF1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_MTMOVF0 register.
//
//*****************************************************************************
#define RFCORE_SFR_MTMOVF0_MTMOVF0_M \
0x000000FF // Indirectly returns and modifies
// bits [7:0] of an internal
// register, depending on the value
// of MTMSEL.MTMOVFSEL. When
// reading the MTMOVF0 register
// with MTMSEL.MTMOVFSEL set to 000
// and MTCTRL.LATCH_MODE set to 0,
// the overflow counter value
// (MTovf) is latched. When reading
// the MTM0 register with
// MTMSEL.MTMOVFSEL set to 000 and
// MTCTRL.LATCH_MODE set to 1, the
// overflow counter value (MTovf)
// is latched.
#define RFCORE_SFR_MTMOVF0_MTMOVF0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_RFDATA register.
//
//*****************************************************************************
#define RFCORE_SFR_RFDATA_RFD_M 0x000000FF // Data written to the register is
// written to the TX FIFO. When
// reading this register, data from
// the RX FIFO is read.
#define RFCORE_SFR_RFDATA_RFD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_RFERRF register.
//
//*****************************************************************************
#define RFCORE_SFR_RFERRF_STROBEERR \
0x00000040 // A command strobe was issued
// when it could not be processed.
// Triggered if trying to disable
// the radio when it is already
// disabled, or when trying to do a
// SACK, SACKPEND, or SNACK command
// when not in active RX. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFERRF_STROBEERR_M \
0x00000040
#define RFCORE_SFR_RFERRF_STROBEERR_S 6
#define RFCORE_SFR_RFERRF_TXUNDERF \
0x00000020 // TX FIFO underflowed. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFERRF_TXUNDERF_M \
0x00000020
#define RFCORE_SFR_RFERRF_TXUNDERF_S 5
#define RFCORE_SFR_RFERRF_TXOVERF \
0x00000010 // TX FIFO overflowed. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFERRF_TXOVERF_M \
0x00000010
#define RFCORE_SFR_RFERRF_TXOVERF_S 4
#define RFCORE_SFR_RFERRF_RXUNDERF \
0x00000008 // RX FIFO underflowed. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFERRF_RXUNDERF_M \
0x00000008
#define RFCORE_SFR_RFERRF_RXUNDERF_S 3
#define RFCORE_SFR_RFERRF_RXOVERF \
0x00000004 // RX FIFO overflowed. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFERRF_RXOVERF_M \
0x00000004
#define RFCORE_SFR_RFERRF_RXOVERF_S 2
#define RFCORE_SFR_RFERRF_RXABO 0x00000002 // Reception of a frame was
// aborted. 0: No interrupt pending
// 1: Interrupt pending
#define RFCORE_SFR_RFERRF_RXABO_M \
0x00000002
#define RFCORE_SFR_RFERRF_RXABO_S 1
#define RFCORE_SFR_RFERRF_NLOCK 0x00000001 // The frequency synthesizer
// failed to achieve lock after
// time-out, or lock is lost during
// reception. The receiver must be
// restarted to clear this error
// situation. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFERRF_NLOCK_M \
0x00000001
#define RFCORE_SFR_RFERRF_NLOCK_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_RFIRQF1 register.
//
//*****************************************************************************
#define RFCORE_SFR_RFIRQF1_CSP_WAIT \
0x00000020 // Execution continued after a
// wait instruction in CSP. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFIRQF1_CSP_WAIT_M \
0x00000020
#define RFCORE_SFR_RFIRQF1_CSP_WAIT_S 5
#define RFCORE_SFR_RFIRQF1_CSP_STOP \
0x00000010 // CSP has stopped program
// execution. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF1_CSP_STOP_M \
0x00000010
#define RFCORE_SFR_RFIRQF1_CSP_STOP_S 4
#define RFCORE_SFR_RFIRQF1_CSP_MANINT \
0x00000008 // Manual interrupt generated from
// CSP 0: No interrupt pending 1:
// Interrupt pending
#define RFCORE_SFR_RFIRQF1_CSP_MANINT_M \
0x00000008
#define RFCORE_SFR_RFIRQF1_CSP_MANINT_S 3
#define RFCORE_SFR_RFIRQF1_RFIDLE \
0x00000004 // Radio state-machine has entered
// the IDLE state. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF1_RFIDLE_M \
0x00000004
#define RFCORE_SFR_RFIRQF1_RFIDLE_S 2
#define RFCORE_SFR_RFIRQF1_TXDONE \
0x00000002 // A complete frame has been
// transmitted. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF1_TXDONE_M \
0x00000002
#define RFCORE_SFR_RFIRQF1_TXDONE_S 1
#define RFCORE_SFR_RFIRQF1_TXACKDONE \
0x00000001 // An acknowledgement frame has
// been completely transmitted. 0:
// No interrupt pending 1:
// Interrupt pending
#define RFCORE_SFR_RFIRQF1_TXACKDONE_M \
0x00000001
#define RFCORE_SFR_RFIRQF1_TXACKDONE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_RFIRQF0 register.
//
//*****************************************************************************
#define RFCORE_SFR_RFIRQF0_RXMASKZERO \
0x00000080 // The RXENABLE register has gone
// from a nonzero state to an
// all-zero state. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF0_RXMASKZERO_M \
0x00000080
#define RFCORE_SFR_RFIRQF0_RXMASKZERO_S 7
#define RFCORE_SFR_RFIRQF0_RXPKTDONE \
0x00000040 // A complete frame has been
// received. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF0_RXPKTDONE_M \
0x00000040
#define RFCORE_SFR_RFIRQF0_RXPKTDONE_S 6
#define RFCORE_SFR_RFIRQF0_FRAME_ACCEPTED \
0x00000020 // Frame has passed frame
// filtering. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF0_FRAME_ACCEPTED_M \
0x00000020
#define RFCORE_SFR_RFIRQF0_FRAME_ACCEPTED_S 5
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_FOUND \
0x00000010 // Source match is found. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_FOUND_M \
0x00000010
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_FOUND_S 4
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_DONE \
0x00000008 // Source matching is complete. 0:
// No interrupt pending 1:
// Interrupt pending
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_DONE_M \
0x00000008
#define RFCORE_SFR_RFIRQF0_SRC_MATCH_DONE_S 3
#define RFCORE_SFR_RFIRQF0_FIFOP \
0x00000004 // The number of bytes in the RX
// FIFO is greater than the
// threshold. Also raised when a
// complete frame is received, and
// when a packet is read out
// completely and more complete
// packets are available. 0: No
// interrupt pending 1: Interrupt
// pending
#define RFCORE_SFR_RFIRQF0_FIFOP_M \
0x00000004
#define RFCORE_SFR_RFIRQF0_FIFOP_S 2
#define RFCORE_SFR_RFIRQF0_SFD 0x00000002 // SFD has been received or
// transmitted. 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF0_SFD_M \
0x00000002
#define RFCORE_SFR_RFIRQF0_SFD_S 1
#define RFCORE_SFR_RFIRQF0_ACT_UNUSED \
0x00000001 // Reserved 0: No interrupt
// pending 1: Interrupt pending
#define RFCORE_SFR_RFIRQF0_ACT_UNUSED_M \
0x00000001
#define RFCORE_SFR_RFIRQF0_ACT_UNUSED_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// RFCORE_SFR_RFST register.
//
//*****************************************************************************
#define RFCORE_SFR_RFST_INSTR_M 0x000000FF // Data written to this register
// is written to the CSP
// instruction memory. Reading this
// register returns the CSP
// instruction currently being
// executed.
#define RFCORE_SFR_RFST_INSTR_S 0
#endif // __HW_RFCORE_SFR_H__

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/******************************************************************************
* Filename: hw_smwdthrosc.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_SMWDTHROSC_H__
#define __HW_SMWDTHROSC_H__
//*****************************************************************************
//
// The following are defines for the SMWDTHROSC register offsets.
//
//*****************************************************************************
#define SMWDTHROSC_WDCTL 0x400D5000 // Watchdog Timer Control
#define SMWDTHROSC_ST0 0x400D5040 // Sleep Timer 0 count and compare
#define SMWDTHROSC_ST1 0x400D5044 // Sleep Timer 1 count and compare
#define SMWDTHROSC_ST2 0x400D5048 // Sleep Timer 2 count and compare
#define SMWDTHROSC_ST3 0x400D504C // Sleep Timer 3 count and compare
#define SMWDTHROSC_STLOAD 0x400D5050 // Sleep Timer load status
#define SMWDTHROSC_STCC 0x400D5054 // Sleep Timer Capture control
#define SMWDTHROSC_STCS 0x400D5058 // Sleep Timer Capture status
#define SMWDTHROSC_STCV0 0x400D505C // Sleep Timer Capture value byte
// 0
#define SMWDTHROSC_STCV1 0x400D5060 // Sleep Timer Capture value byte
// 1
#define SMWDTHROSC_STCV2 0x400D5064 // Sleep Timer Capture value byte
// 2
#define SMWDTHROSC_STCV3 0x400D5068 // Sleep Timer Capture value byte
// 3
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_WDCTL register.
//
//*****************************************************************************
#define SMWDTHROSC_WDCTL_CLR_M 0x000000F0 // Clear timer When 0xA followed
// by 0x5 is written to these bits,
// the timer is loaded with 0x0000.
// Note that 0x5 must be written
// within one watchdog clock period
// Twdt after 0xA was written for
// the clearing to take effect
// (ensured). If 0x5 is written
// between Twdt and 2Twdt after 0xA
// was written, the clearing may
// take effect, but there is no
// guarantee. If 0x5 is written >
// 2Twdt after 0xA was written, the
// timer will not be cleared. If a
// value other than 0x5 is written
// after 0xA has been written, the
// clear sequence is aborted. If
// 0xA is written, this starts a
// new clear sequence. Writing to
// these bits when EN = 0 has no
// effect.
#define SMWDTHROSC_WDCTL_CLR_S 4
#define SMWDTHROSC_WDCTL_EN 0x00000008 // Enable timer When 1 is written
// to this bit the timer is enabled
// and starts incrementing. The
// interval setting specified by
// INT[1:0] is used. Writing 0 to
// this bit have no effect.
#define SMWDTHROSC_WDCTL_EN_M 0x00000008
#define SMWDTHROSC_WDCTL_EN_S 3
#define SMWDTHROSC_WDCTL_INT_M 0x00000003 // Timer interval select These
// bits select the timer interval
// as follows: 00: Twdt x 32768 01:
// Twdt x 8192 10: Twdt x 512 11:
// Twdt x 64 Writing these bits
// when EN = 1 has no effect.
#define SMWDTHROSC_WDCTL_INT_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_ST0 register.
//
//*****************************************************************************
#define SMWDTHROSC_ST0_ST0_M 0x000000FF // Sleep Timer count and compare
// value. When read, this register
// returns the low bits [7:0] of
// the Sleep Timer count. When
// writing this register sets the
// low bits [7:0] of the compare
// value.
#define SMWDTHROSC_ST0_ST0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_ST1 register.
//
//*****************************************************************************
#define SMWDTHROSC_ST1_ST1_M 0x000000FF // Sleep Timer count and compare
// value When read, this register
// returns the middle bits [15:8]
// of the Sleep Timer count. When
// writing this register sets the
// middle bits [15:8] of the
// compare value. The value read is
// latched at the time of reading
// register ST0. The value written
// is latched when ST0 is written.
#define SMWDTHROSC_ST1_ST1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_ST2 register.
//
//*****************************************************************************
#define SMWDTHROSC_ST2_ST2_M 0x000000FF // Sleep Timer count and compare
// value When read, this register
// returns the high bits [23:16] of
// the Sleep Timer count. When
// writing this register sets the
// high bits [23:16] of the compare
// value. The value read is latched
// at the time of reading register
// ST0. The value written is
// latched when ST0 is written.
#define SMWDTHROSC_ST2_ST2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_ST3 register.
//
//*****************************************************************************
#define SMWDTHROSC_ST3_ST3_M 0x000000FF // Sleep Timer count and compare
// value When read, this register
// returns the high bits [31:24] of
// the Sleep Timer count. When
// writing this register sets the
// high bits [31:24] of the compare
// value. The value read is latched
// at the time of reading register
// ST0. The value written is
// latched when ST0 is written.
#define SMWDTHROSC_ST3_ST3_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STLOAD register.
//
//*****************************************************************************
#define SMWDTHROSC_STLOAD_STLOAD \
0x00000001 // Status signal for when STx
// registers have been uploaded to
// 32-kHz counter. 1: Load is
// complete 0: Load is busy and STx
// regs are blocked for writing
#define SMWDTHROSC_STLOAD_STLOAD_M \
0x00000001
#define SMWDTHROSC_STLOAD_STLOAD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCC register.
//
//*****************************************************************************
#define SMWDTHROSC_STCC_PORT_M 0x00000038 // Port select Valid settings are
// 0-3, all others inhibit any
// capture from occurring 000: Port
// A selected 001: Port B selected
// 010: Port C selected 011: Port D
// selected
#define SMWDTHROSC_STCC_PORT_S 3
#define SMWDTHROSC_STCC_PIN_M 0x00000007 // Pin select Valid settings are
// 1-7 when either port A, B, C, or
// D is selected.
#define SMWDTHROSC_STCC_PIN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCS register.
//
//*****************************************************************************
#define SMWDTHROSC_STCS_VALID 0x00000001 // Capture valid flag Set to 1
// when capture value in STCV has
// been updated Clear explicitly to
// allow new capture
#define SMWDTHROSC_STCS_VALID_M 0x00000001
#define SMWDTHROSC_STCS_VALID_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCV0 register.
//
//*****************************************************************************
#define SMWDTHROSC_STCV0_STCV0_M \
0x000000FF // Bits [7:0] of Sleep Timer
// capture value
#define SMWDTHROSC_STCV0_STCV0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCV1 register.
//
//*****************************************************************************
#define SMWDTHROSC_STCV1_STCV1_M \
0x000000FF // Bits [15:8] of Sleep Timer
// capture value
#define SMWDTHROSC_STCV1_STCV1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCV2 register.
//
//*****************************************************************************
#define SMWDTHROSC_STCV2_STCV2_M \
0x000000FF // Bits [23:16] of Sleep Timer
// capture value
#define SMWDTHROSC_STCV2_STCV2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SMWDTHROSC_STCV3 register.
//
//*****************************************************************************
#define SMWDTHROSC_STCV3_STCV3_M \
0x000000FF // Bits [32:24] of Sleep Timer
// capture value
#define SMWDTHROSC_STCV3_STCV3_S 0
#endif // __HW_SMWDTHROSC_H__

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cpu/cc2538/include/vendor/hw_soc_adc.h vendored Executable file
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/******************************************************************************
* Filename: hw_soc_adc.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_SOC_ADC_H__
#define __HW_SOC_ADC_H__
//*****************************************************************************
//
// The following are defines for the SOC_ADC register offsets.
//
//*****************************************************************************
#define SOC_ADC_ADCCON1 0x400D7000 // This register controls the ADC.
#define SOC_ADC_ADCCON2 0x400D7004 // This register controls the ADC.
#define SOC_ADC_ADCCON3 0x400D7008 // This register controls the ADC.
#define SOC_ADC_ADCL 0x400D700C // This register contains the
// least-significant part of ADC
// conversion result.
#define SOC_ADC_ADCH 0x400D7010 // This register contains the
// most-significant part of ADC
// conversion result.
#define SOC_ADC_RNDL 0x400D7014 // This registers contains
// random-number-generator data;
// low byte.
#define SOC_ADC_RNDH 0x400D7018 // This register contains
// random-number-generator data;
// high byte.
#define SOC_ADC_CMPCTL 0x400D7024 // Analog comparator control and
// status register.
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SOC_ADC_ADCCON1 register.
//
//*****************************************************************************
#define SOC_ADC_ADCCON1_EOC 0x00000080 // End of conversion. Cleared when
// ADCH has been read. If a new
// conversion is completed before
// the previous data has been read,
// the EOC bit remains high. 0:
// Conversion not complete 1:
// Conversion completed
#define SOC_ADC_ADCCON1_EOC_M 0x00000080
#define SOC_ADC_ADCCON1_EOC_S 7
#define SOC_ADC_ADCCON1_ST 0x00000040 // Start conversion Read as 1
// until conversion completes 0: No
// conversion in progress. 1: Start
// a conversion sequence if
// ADCCON1.STSEL = 11 and no
// sequence is running.
#define SOC_ADC_ADCCON1_ST_M 0x00000040
#define SOC_ADC_ADCCON1_ST_S 6
#define SOC_ADC_ADCCON1_STSEL_M 0x00000030 // Start select Selects the event
// that starts a new conversion
// sequence 00: Not implemented 01:
// Full speed. Do not wait for
// triggers 10: Timer 1 channel 0
// compare event 11: ADCCON1.ST = 1
#define SOC_ADC_ADCCON1_STSEL_S 4
#define SOC_ADC_ADCCON1_RCTRL_M 0x0000000C // Controls the 16-bit
// random-number generator (see
// User Guide Chapter 16) When 01
// is written, the setting
// automatically returns to 00 when
// the operation completes. 00:
// Normal operation (13x unrolling)
// 01: Clock the LFSR once (13x
// unrolling) 10: Reserved 11:
// Stopped. The random-number
// generator is turned off.
#define SOC_ADC_ADCCON1_RCTRL_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SOC_ADC_ADCCON2 register.
//
//*****************************************************************************
#define SOC_ADC_ADCCON2_SREF_M 0x000000C0 // Selects reference voltage used
// for the sequence of conversions
// 00: Internal reference 01:
// External reference on AIN7 pin
// 10: AVDD5 pin 11: External
// reference on AIN6-AIN7
// differential input
#define SOC_ADC_ADCCON2_SREF_S 6
#define SOC_ADC_ADCCON2_SDIV_M 0x00000030 // Sets the decimation rate for
// channels included in the
// sequence of conversions. The
// decimation rate also determines
// the resolution and time required
// to complete a conversion. 00: 64
// decimation rate (7 bits ENOB
// setting) 01: 128 decimation rate
// (9 bits ENOB setting) 10: 256
// decimation rate (10 bits ENOB
// setting) 11: 512 decimation rate
// (12 bits ENOB setting)
#define SOC_ADC_ADCCON2_SDIV_S 4
#define SOC_ADC_ADCCON2_SCH_M 0x0000000F // Sequence channel select Selects
// the end of the sequence A
// sequence can either be from AIN0
// to AIN7 (SCH <= 7) or from
// differential input AIN0-AIN1 to
// AIN6-AIN7 (8 <= SCH <= 11). For
// other settings, only one
// conversions is performed. When
// read, these bits indicate the
// channel number on which a
// conversion is ongoing: 0000:
// AIN0 0001: AIN1 0010: AIN2 0011:
// AIN3 0100: AIN4 0101: AIN5 0110:
// AIN6 0111: AIN7 1000: AIN0-AIN1
// 1001: AIN2-AIN3 1010: AIN4-AIN5
// 1011: AIN6-AIN7 1100: GND 1101:
// Reserved 1110: Temperature
// sensor 1111: VDD/3
#define SOC_ADC_ADCCON2_SCH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SOC_ADC_ADCCON3 register.
//
//*****************************************************************************
#define SOC_ADC_ADCCON3_EREF_M 0x000000C0 // Selects reference voltage used
// for the extra conversion 00:
// Internal reference 01: External
// reference on AIN7 pin 10: AVDD5
// pin 11: External reference on
// AIN6-AIN7 differential input
#define SOC_ADC_ADCCON3_EREF_S 6
#define SOC_ADC_ADCCON3_EDIV_M 0x00000030 // Sets the decimation rate used
// for the extra conversion The
// decimation rate also determines
// the resolution and the time
// required to complete the
// conversion. 00: 64 decimation
// rate (7 bits ENOB) 01: 128
// decimation rate (9 bits ENOB)
// 10: 256 decimation rate (10 bits
// ENOB) 11: 512 decimation rate
// (12 bits ENOB)
#define SOC_ADC_ADCCON3_EDIV_S 4
#define SOC_ADC_ADCCON3_ECH_M 0x0000000F // Single channel select. Selects
// the channel number of the single
// conversion that is triggered by
// writing to ADCCON3. 0000: AIN0
// 0001: AIN1 0010: AIN2 0011: AIN3
// 0100: AIN4 0101: AIN5 0110: AIN6
// 0111: AIN7 1000: AIN0-AIN1 1001:
// AIN2-AIN3 1010: AIN4-AIN5 1011:
// AIN6-AIN7 1100: GND 1101:
// Reserved 1110: Temperature
// sensor 1111: VDD/3
#define SOC_ADC_ADCCON3_ECH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SOC_ADC_ADCL register.
//
//*****************************************************************************
#define SOC_ADC_ADCL_ADC_M 0x000000FC // Least-significant part of ADC
// conversion result
#define SOC_ADC_ADCL_ADC_S 2
//*****************************************************************************
//
// The following are defines for the bit fields in the SOC_ADC_ADCH register.
//
//*****************************************************************************
#define SOC_ADC_ADCH_ADC_M 0x000000FF // Most-significant part of ADC
// conversion result
#define SOC_ADC_ADCH_ADC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SOC_ADC_RNDL register.
//
//*****************************************************************************
#define SOC_ADC_RNDL_RNDL_M 0x000000FF // Random value/seed or CRC
// result, low byte When used for
// random-number generation,
// writing to this register twice
// seeds the random-number
// generator. Writing to this
// register copies the 8 LSBs of
// the LFSR to the 8 MSBs and
// replaces the 8 LSBs with the
// data value written. The value
// returned when reading from this
// register is the 8 LSBs of the
// LFSR. When used for
// random-number generation,
// reading this register returns
// the 8 LSBs of the random number.
// When used for CRC calculations,
// reading this register returns
// the 8 LSBs of the CRC result.
#define SOC_ADC_RNDL_RNDL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SOC_ADC_RNDH register.
//
//*****************************************************************************
#define SOC_ADC_RNDH_RNDH_M 0x000000FF // Random value or CRC
// result/input data, high byte
// When written, a CRC16
// calculation is triggered, and
// the data value written is
// processed starting with the MSB.
// The value returned when reading
// from this register is the 8 MSBs
// of the LFSR. When used for
// random-number generation,
// reading this register returns
// the 8 MSBs of the random number.
// When used for CRC calculations,
// reading this register returns
// the 8 MSBs of the CRC result.
#define SOC_ADC_RNDH_RNDH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SOC_ADC_CMPCTL register.
//
//*****************************************************************************
#define SOC_ADC_CMPCTL_EN 0x00000002 // Comparator enable
#define SOC_ADC_CMPCTL_EN_M 0x00000002
#define SOC_ADC_CMPCTL_EN_S 1
#define SOC_ADC_CMPCTL_OUTPUT 0x00000001 // Comparator output
#define SOC_ADC_CMPCTL_OUTPUT_M 0x00000001
#define SOC_ADC_CMPCTL_OUTPUT_S 0
#endif // __HW_SOC_ADC_H__

491
cpu/cc2538/include/vendor/hw_ssi.h vendored Executable file
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/******************************************************************************
* Filename: hw_ssi.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_SSI_H__
#define __HW_SSI_H__
//*****************************************************************************
//
// The following are defines for the SSI register offsets.
//
//*****************************************************************************
#define SSI_O_CR0 0x00000000 // The CR0 register contains bit
// fields that control various
// functions within the SSI module.
// Functionality such as protocol
// mode, clock rate, and data size
// are configured in this register.
#define SSI_O_CR1 0x00000004 // The CR1 register contains bit
// fields that control various
// functions within the SSI module.
// Master and slave mode
// functionality is controlled by
// this register.
#define SSI_O_DR 0x00000008 // The DR register is 16 bits
// wide. When the SSIDR register is
// read, the entry in the receive
// FIFO that is pointed to by the
// current FIFO read pointer is
// accessed. When a data value is
// removed by the SSI receive logic
// from the incoming data frame, it
// is placed into the entry in the
// receive FIFO pointed to by the
// current FIFO write pointer. When
// the DR register is written to,
// the entry in the transmit FIFO
// that is pointed to by the write
// pointer is written to. Data
// values are removed from the
// transmit FIFO one value at a
// time by the transmit logic. Each
// data value is loaded into the
// transmit serial shifter, then
// serially shifted out onto the
// SSITx pin at the programmed bit
// rate. When a data size of less
// than 16 bits is selected, the
// user must right-justify data
// written to the transmit FIFO.
// The transmit logic ignores the
// unused bits. Received data less
// than 16 bits is automatically
// right-justified in the receive
// buffer. When the SSI is
// programmed for MICROWIRE frame
// format, the default size for
// transmit data is eight bits (the
// most significant byte is
// ignored). The receive data size
// is controlled by the programmer.
// The transmit FIFO and the
// receive FIFO are not cleared
// even when the SSE bit in the
// SSICR1 register is cleared,
// allowing the software to fill
// the transmit FIFO before
// enabling the SSI.
#define SSI_O_SR 0x0000000C // The SR register contains bits
// that indicate the FIFO fill
// status and the SSI busy status.
#define SSI_O_CPSR 0x00000010 // The CPSR register specifies the
// division factor which is used to
// derive the SSIClk from the
// system clock. The clock is
// further divided by a value from
// 1 to 256, which is 1 + SCR. SCR
// is programmed in the SSICR0
// register. The frequency of the
// SSIClk is defined by: SSIClk =
// SysClk / (CPSDVSR x (1 + SCR))
// The value programmed into this
// register must be an even number
// between 2 and 254. The
// least-significant bit of the
// programmed number is hard-coded
// to zero. If an odd number is
// written to this register, data
// read back from this register has
// the least-significant bit as
// zero.
#define SSI_O_IM 0x00000014 // The IM register is the
// interrupt mask set or clear
// register. It is a read/write
// register and all bits are
// cleared on reset. On a read,
// this register gives the current
// value of the mask on the
// corresponding interrupt. Setting
// a bit sets the mask, preventing
// the interrupt from being
// signaled to the interrupt
// controller. Clearing a bit
// clears the corresponding mask,
// enabling the interrupt to be
// sent to the interrupt
// controller.
#define SSI_O_RIS 0x00000018 // The RIS register is the raw
// interrupt status register. On a
// read, this register gives the
// current raw status value of the
// corresponding interrupt before
// masking. A write has no effect.
#define SSI_O_MIS 0x0000001C // The MIS register is the masked
// interrupt status register. On a
// read, this register gives the
// current masked status value of
// the corresponding interrupt. A
// write has no effect.
#define SSI_O_ICR 0x00000020 // The ICR register is the
// interrupt clear register. On a
// write of 1, the corresponding
// interrupt is cleared. A write of
// 0 has no effect.
#define SSI_O_DMACTL 0x00000024 // The DMACTL register is the uDMA
// control register.
#define SSI_O_CC 0x00000FC8 // SSI clock configuration The CC
// register controls the baud clock
// and system clocks sources for
// the SSI module. Note: If the
// PIOSC is used for the SSI baud
// clock, the system clock
// frequency must be at least 16
// MHz in run mode.
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR0 register.
//
//*****************************************************************************
#define SSI_CR0_SCR_M 0x0000FF00 // SSI serial clock rate (R/W)
// Reset value: 0x0 The value SCR
// is used to generate the transmit
// and receive bit rate of the SSI.
// Where the bit rate is: BR =
// FSSICLK/(CPSDVR * (1 + SCR))
// where CPSDVR is an even value
// from 2-254, programmed in the
// SSICPSR register and SCR is a
// value from 0-255.
#define SSI_CR0_SCR_S 8
#define SSI_CR0_SPH 0x00000080 // SSI serial clock phase (R/W)
// Reset value: 0x0 This bit is
// only applicable to the Motorola
// SPI Format.
#define SSI_CR0_SPH_M 0x00000080
#define SSI_CR0_SPH_S 7
#define SSI_CR0_SPO 0x00000040 // SSI serial clock phase (R/W)
// Reset value: 0x0 This bit is
// only applicable to the Motorola
// SPI Format.
#define SSI_CR0_SPO_M 0x00000040
#define SSI_CR0_SPO_S 6
#define SSI_CR0_FRF_M 0x00000030 // SSI frame format select (R/W)
// Reset value: 0x0 00: Motorola
// SPI frame format 01: TI
// synchronous serial frame format
// 10: National Microwire frame
// format 11: Reserved
#define SSI_CR0_FRF_S 4
#define SSI_CR0_DSS_M 0x0000000F // SSI data size select (R/W)
// Reset value: 0x0 0000-0010:
// Reserved 0011: 4-bit data 0100:
// 5-bit data 0101: 6-bit data
// 0110: 7-bit data 0111: 8-bit
// data 1000: 9-bit data 1001:
// 10-bit data 1010: 11-bit data
// 1011: 12-bit data 1100: 13-bit
// data 1101: 14-bit data 1110:
// 15-bit data 1111: 16-bit data
#define SSI_CR0_DSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CR1 register.
//
//*****************************************************************************
#define SSI_CR1_SOD 0x00000008 // SSI slave mode output disable
// (R/W) Reset value: 0x0 This bit
// is relevant only in the slave
// mode (MS = 1). In multiple-slave
// systems, it is possible for the
// SSI master to broadcast a
// message to all slaves in the
// system while ensuring that only
// one slave drives data onto the
// serial output line. In such
// systems, the RXD lines from
// multiple slaves could be tied
// together. To operate in such a
// system, the SOD bit can be set
// if the SSI slave is not suppose
// to drive the SSITXD line. 0: SSI
// can drive SSITXD in slave output
// mode 1: SSI must not drive the
// SSITXD output in slave mode
#define SSI_CR1_SOD_M 0x00000008
#define SSI_CR1_SOD_S 3
#define SSI_CR1_MS 0x00000004 // SSI master and slave select
// (R/W) Reset value: 0x0 This bit
// can be modified only when the
// SSI is disabled (SSE = 0). 0:
// Device configured as a master
// (default) 1: Device configured
// as a slave
#define SSI_CR1_MS_M 0x00000004
#define SSI_CR1_MS_S 2
#define SSI_CR1_SSE 0x00000002 // SSI synchronous serial port
// enable (R/W) Reset value: 0x0 0:
// SSI operation is disabled. 1:
// SSI operation is enabled.
#define SSI_CR1_SSE_M 0x00000002
#define SSI_CR1_SSE_S 1
#define SSI_CR1_LBM 0x00000001 // SSI loop-back mode (R/W) Reset
// value: 0x0 0: Normal serial port
// operation is enabled. 1: The
// output of the transmit serial
// shifter is connected to the
// input of the receive serial
// shift register internally.
#define SSI_CR1_LBM_M 0x00000001
#define SSI_CR1_LBM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DR register.
//
//*****************************************************************************
#define SSI_DR_DATA_M 0x0000FFFF // SSI receive/transmit data
// register (R/W) Reset value:
// 0xXXXX A read operation reads
// the receive FIFO. A write
// operation writes the transmit
// FIFO. Software must
// right-justify data when the SSI
// is programmed for a data size
// that is less than 16 bits.
// Unused bits at the top are
// ignored by the transmit logic.
// The receive logic automatically
// right-justified the data.
#define SSI_DR_DATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_SR register.
//
//*****************************************************************************
#define SSI_SR_BSY 0x00000010 // SSI busy bit (RO) Reset value:
// 0x0 0: SSI is idle. 1: SSI is
// currently transmitting and/or
// receiving a frame or the
// transmit FIFO is not empty.
#define SSI_SR_BSY_M 0x00000010
#define SSI_SR_BSY_S 4
#define SSI_SR_RFF 0x00000008 // SSI receive FIFO full (RO)
// Reset value: 0x0 0: Receive FIFO
// is not full. 1: Receive FIFO is
// full.
#define SSI_SR_RFF_M 0x00000008
#define SSI_SR_RFF_S 3
#define SSI_SR_RNE 0x00000004 // SSI receive FIFO not empty (RO)
// Reset value: 0x0 0: Receive FIFO
// is empty. 1: Receive FIFO is not
// empty.
#define SSI_SR_RNE_M 0x00000004
#define SSI_SR_RNE_S 2
#define SSI_SR_TNF 0x00000002 // SSI transmit FIFO not full (RO)
// Reset value: 0x1 0: Transmit
// FIFO is full. 1: Transmit FIFO
// is not full.
#define SSI_SR_TNF_M 0x00000002
#define SSI_SR_TNF_S 1
#define SSI_SR_TFE 0x00000001 // SSI transmit FIFO empty (RO)
// Reset value: 0x1 0: Transmit
// FIFO is not empty. 1: Transmit
// FIFO is empty.
#define SSI_SR_TFE_M 0x00000001
#define SSI_SR_TFE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CPSR register.
//
//*****************************************************************************
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI clock prescale divisor
// (R/W) Reset value: 0x0 This
// value must be an even number
// from 2 to 254, depending on the
// frequency of SSICLK. The LSB
// always returns zero on reads.
#define SSI_CPSR_CPSDVSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_IM register.
//
//*****************************************************************************
#define SSI_IM_TXIM 0x00000008 // SSI transmit FIFO interrupt
// mask (R/W) Reset value: 0x0 0:
// TX FIFO half empty or condition
// interrupt is masked. 1: TX FIFO
// half empty or less condition
// interrupt is not masked.
#define SSI_IM_TXIM_M 0x00000008
#define SSI_IM_TXIM_S 3
#define SSI_IM_RXIM 0x00000004 // SSI receive FIFO interrupt mask
// (R/W) Reset value: 0x0 0: RX
// FIFO half empty or condition
// interrupt is masked. 1: RX FIFO
// half empty or less condition
// interrupt is not masked.
#define SSI_IM_RXIM_M 0x00000004
#define SSI_IM_RXIM_S 2
#define SSI_IM_RTIM 0x00000002 // SSI receive time-out interrupt
// mask (R/W) Reset value: 0x0 0:
// RX FIFO time-out interrupt is
// masked. 1: RX FIFO time-out
// interrupt is not masked
#define SSI_IM_RTIM_M 0x00000002
#define SSI_IM_RTIM_S 1
#define SSI_IM_RORIM 0x00000001 // SSI receive overrun interrupt
// mask (R/W) Reset value: 0x0 0:
// RX FIFO Overrun interrupt is
// masked. 1: RX FIFO Overrun
// interrupt is not masked
#define SSI_IM_RORIM_M 0x00000001
#define SSI_IM_RORIM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_RIS register.
//
//*****************************************************************************
#define SSI_RIS_TXRIS 0x00000008 // SSI SSITXINTR raw state (RO)
// Reset value: 0x1 Gives the raw
// interrupt state (before masking)
// of SSITXINTR
#define SSI_RIS_TXRIS_M 0x00000008
#define SSI_RIS_TXRIS_S 3
#define SSI_RIS_RXRIS 0x00000004 // SSI SSIRXINTR raw state (RO)
// Reset value: 0x0 Gives the raw
// interrupt state (before masking)
// of SSIRXINTR
#define SSI_RIS_RXRIS_M 0x00000004
#define SSI_RIS_RXRIS_S 2
#define SSI_RIS_RTRIS 0x00000002 // SSI SSIRTINTR raw state (RO)
// Reset value: 0x0 Gives the raw
// interrupt state (before masking)
// of SSIRTINTR
#define SSI_RIS_RTRIS_M 0x00000002
#define SSI_RIS_RTRIS_S 1
#define SSI_RIS_RORRIS 0x00000001 // SSI SSIRORINTR raw state (RO)
// Reset value: 0x0 Gives the raw
// interrupt state (before masking)
// of SSIRORINTR
#define SSI_RIS_RORRIS_M 0x00000001
#define SSI_RIS_RORRIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_MIS register.
//
//*****************************************************************************
#define SSI_MIS_TXMIS 0x00000008 // SSI SSITXINTR masked state (RO)
// Reset value: 0x0 Gives the
// interrupt state (after masking)
// of SSITXINTR
#define SSI_MIS_TXMIS_M 0x00000008
#define SSI_MIS_TXMIS_S 3
#define SSI_MIS_RXMIS 0x00000004 // SSI SSIRXINTR masked state (RO)
// Reset value: 0x0 Gives the
// interrupt state (after masking)
// of SSIRXINTR
#define SSI_MIS_RXMIS_M 0x00000004
#define SSI_MIS_RXMIS_S 2
#define SSI_MIS_RTMIS 0x00000002 // SSI SSIRTINTR masked state (RO)
// Reset value: 0x0 Gives the
// interrupt state (after masking)
// of SSIRTINTR
#define SSI_MIS_RTMIS_M 0x00000002
#define SSI_MIS_RTMIS_S 1
#define SSI_MIS_RORMIS 0x00000001 // SSI SSIRORINTR masked state
// (RO) Reset value: 0x0 Gives the
// interrupt state (after masking)
// of SSIRORINTR
#define SSI_MIS_RORMIS_M 0x00000001
#define SSI_MIS_RORMIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_ICR register.
//
//*****************************************************************************
#define SSI_ICR_RTIC 0x00000002 // SSI receive time-out interrupt
// clear (W1C) Reset value: 0x0 0:
// No effect on interrupt 1: Clears
// interrupt
#define SSI_ICR_RTIC_M 0x00000002
#define SSI_ICR_RTIC_S 1
#define SSI_ICR_RORIC 0x00000001 // SSI receive overrun interrupt
// clear (W1C) Reset value: 0x0 0:
// No effect on interrupt 1: Clears
// interrupt
#define SSI_ICR_RORIC_M 0x00000001
#define SSI_ICR_RORIC_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_DMACTL register.
//
//*****************************************************************************
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA enable 0: uDMA for
// the transmit FIFO is disabled.
// 1: uDMA for the transmit FIFO is
// enabled.
#define SSI_DMACTL_TXDMAE_M 0x00000002
#define SSI_DMACTL_TXDMAE_S 1
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA enable 0: uDMA for
// the receive FIFO is disabled. 1:
// uDMA for the receive FIFO is
// enabled.
#define SSI_DMACTL_RXDMAE_M 0x00000001
#define SSI_DMACTL_RXDMAE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SSI_O_CC register.
//
//*****************************************************************************
#define SSI_CC_CS_M 0x00000007 // SSI baud and system clock
// source The following bits
// determine the clock source that
// generates the baud and system
// clocks for the SSI. bit0
// (PIOSC): 1: The SSI baud clock
// is determined by the IO DIV
// setting in the system
// controller. 0: The SSI baud
// clock is determined by the SYS
// DIV setting in the system
// controller. bit1: Unused bit2:
// (DSEN) Only meaningful when the
// system is in deep sleep mode.
// This bit is a don't care when
// not in sleep mode. 1: The SSI
// system clock is running on the
// same clock as the baud clock, as
// per PIOSC setting above. 0: The
// SSI system clock is determined
// by the SYS DIV setting in the
// system controller.
#define SSI_CC_CS_S 0
#endif // __HW_SSI_H__

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/******************************************************************************
* Filename: hw_sys_ctrl.h
* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
* Revision: $Revision: 9735 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_SYS_CTRL_H__
#define __HW_SYS_CTRL_H__
//*****************************************************************************
//
// The following are defines for the SYS_CTRL register offsets.
//
//*****************************************************************************
#define SYS_CTRL_CLOCK_CTRL 0x400D2000 // The clock control register
// handels clock settings in the
// CC2538. The settings in
// CLOCK_CTRL do not always reflect
// the current chip status which is
// found in CLOCK_STA register.
#define SYS_CTRL_CLOCK_STA 0x400D2004 // Clock status register This
// register reflects the current
// chip status.
#define SYS_CTRL_RCGCGPT 0x400D2008 // This register defines the
// module clocks for GPT[3:0] when
// the CPU is in active (run) mode.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SCGCGPT 0x400D200C // This register defines the
// module clocks for GPT[3:0] when
// the CPU is in sleep mode. This
// register setting is don't care
// for PM1-3, because the system
// clock is powered down in these
// modes.
#define SYS_CTRL_DCGCGPT 0x400D2010 // This register defines the
// module clocks for GPT[3:0] when
// the CPU is in PM0. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_SRGPT 0x400D2014 // This register controls the
// reset for GPT[3:0].
#define SYS_CTRL_RCGCSSI 0x400D2018 // This register defines the
// module clocks for SSI[1:0] when
// the CPU is in active (run) mode.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SCGCSSI 0x400D201C // This register defines the
// module clocks for SSI[1:0] when
// the CPU is insSleep mode. This
// register setting is don't care
// for PM1-3, because the system
// clock is powered down in these
// modes.
#define SYS_CTRL_DCGCSSI 0x400D2020 // This register defines the
// module clocks for SSI[1:0] when
// the CPU is in PM0. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_SRSSI 0x400D2024 // This register controls the
// reset for SSI[1:0].
#define SYS_CTRL_RCGCUART 0x400D2028 // This register defines the
// module clocks for UART[1:0] when
// the CPU is in active (run) mode.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SCGCUART 0x400D202C // This register defines the
// module clocks for UART[1:0] when
// the CPU is in sleep mode. This
// register setting is don't care
// for PM1-3, because the system
// clock is powered down in these
// modes.
#define SYS_CTRL_DCGCUART 0x400D2030 // This register defines the
// module clocks for UART[1:0] when
// the CPU is in PM0. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_SRUART 0x400D2034 // This register controls the
// reset for UART[1:0].
#define SYS_CTRL_RCGCI2C 0x400D2038 // This register defines the
// module clocks for I2C when the
// CPU is in active (run) mode.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SCGCI2C 0x400D203C // This register defines the
// module clocks for I2C when the
// CPU is in sleep mode. This
// register setting is don't care
// for PM1-3, because the system
// clock is powered down in these
// modes.
#define SYS_CTRL_DCGCI2C 0x400D2040 // This register defines the
// module clocks for I2C when the
// CPU is in PM0. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_SRI2C 0x400D2044 // This register controls the
// reset for I2C.
#define SYS_CTRL_RCGCSEC 0x400D2048 // This register defines the
// module clocks for the security
// module when the CPU is in active
// (run) mode. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_SCGCSEC 0x400D204C // This register defines the
// module clocks for the security
// module when the CPU is in sleep
// mode. This register setting is
// don't care for PM1-3, because
// the system clock is powered down
// in these modes.
#define SYS_CTRL_DCGCSEC 0x400D2050 // This register defines the
// module clocks for the security
// module when the CPU is in PM0.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SRSEC 0x400D2054 // This register controls the
// reset for the security module.
#define SYS_CTRL_PMCTL 0x400D2058 // This register controls the
// power mode. Note: The
// Corresponding PM is not entered
// before the WFI instruction is
// asserted. To enter PM1-3 the
// DEEPSLEEP bit in SYSCTRL must be
// 1.
#define SYS_CTRL_SRCRC 0x400D205C // This register controls CRC on
// state retention.
#define SYS_CTRL_PWRDBG 0x400D2074 // Power debug register
#define SYS_CTRL_CLD 0x400D2080 // This register controls the
// clock loss detection feature.
#define SYS_CTRL_IWE 0x400D2094 // This register controls
// interrupt wake-up.
#define SYS_CTRL_I_MAP 0x400D2098 // This register selects which
// interrupt map to be used.
#define SYS_CTRL_RCGCRFC 0x400D20A8 // This register defines the
// module clocks for RF CORE when
// the CPU is in active (run) mode.
// This register setting is don't
// care for PM1-3, because the
// system clock is powered down in
// these modes.
#define SYS_CTRL_SCGCRFC 0x400D20AC // This register defines the
// module clocks for RF CORE when
// the CPU is in sleep mode. This
// register setting is don't care
// for PM1-3, because the system
// clock is powered down in these
// modes.
#define SYS_CTRL_DCGCRFC 0x400D20B0 // This register defines the
// module clocks for RF CORE when
// the CPU is in PM0. This register
// setting is don't care for PM1-3,
// because the system clock is
// powered down in these modes.
#define SYS_CTRL_EMUOVR 0x400D20B4 // This register defines the
// emulator override controls for
// power mode and peripheral clock
// gate.
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_CLOCK_CTRL register.
//
//*****************************************************************************
#define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS \
0x02000000 // Disable calibration 32-kHz RC
// oscillator. 0: Enable
// calibration 1: Disable
// calibration
#define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS_M \
0x02000000
#define SYS_CTRL_CLOCK_CTRL_OSC32K_CALDIS_S 25
#define SYS_CTRL_CLOCK_CTRL_OSC32K \
0x01000000 // 32-kHz clock oscillator
// selection 0: 32-kHz crystal
// oscillator 1: 32-kHz RC
// oscillator
#define SYS_CTRL_CLOCK_CTRL_OSC32K_M \
0x01000000
#define SYS_CTRL_CLOCK_CTRL_OSC32K_S 24
#define SYS_CTRL_CLOCK_CTRL_AMP_DET \
0x00200000 // Amplitude detector of XOSC
// during power up 0: No action 1:
// Delay qualification of XOSC
// until amplitude is greater than
// the threshold.
#define SYS_CTRL_CLOCK_CTRL_AMP_DET_M \
0x00200000
#define SYS_CTRL_CLOCK_CTRL_AMP_DET_S 21
#define SYS_CTRL_CLOCK_CTRL_OSC_PD \
0x00020000 // 0: Power up both oscillators 1:
// Power down oscillator not
// selected by OSC bit
// (hardware-controlled when
// selected).
#define SYS_CTRL_CLOCK_CTRL_OSC_PD_M \
0x00020000
#define SYS_CTRL_CLOCK_CTRL_OSC_PD_S 17
#define SYS_CTRL_CLOCK_CTRL_OSC 0x00010000 // System clock oscillator
// selection 0: 32-MHz crystal
// oscillator 1: 16-MHz HF-RC
// oscillator
#define SYS_CTRL_CLOCK_CTRL_OSC_M \
0x00010000
#define SYS_CTRL_CLOCK_CTRL_OSC_S 16
#define SYS_CTRL_CLOCK_CTRL_IO_DIV_M \
0x00000700 // I/O clock rate setting Cannot
// be higher than OSC setting 000:
// 32 MHz 001: 16 MHz 010: 8 MHz
// 011: 4 MHz 100: 2 MHz 101: 1 MHz
// 110: 0.5 MHz 111: 0.25 MHz
#define SYS_CTRL_CLOCK_CTRL_IO_DIV_S 8
#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_M \
0x00000007 // System clock rate setting
// Cannot be higher than OSC
// setting 000: 32 MHz 001: 16 MHz
// 010: 8 MHz 011: 4 MHz 100: 2 MHz
// 101: 1 MHz 110: 0.5 MHz 111:
// 0.25 MHz
#define SYS_CTRL_CLOCK_CTRL_SYS_DIV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_CLOCK_STA register.
//
//*****************************************************************************
#define SYS_CTRL_CLOCK_STA_SYNC_32K \
0x04000000 // 32-kHz clock source synced to
// undivided system clock (16 or 32
// MHz).
#define SYS_CTRL_CLOCK_STA_SYNC_32K_M \
0x04000000
#define SYS_CTRL_CLOCK_STA_SYNC_32K_S 26
#define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS \
0x02000000 // Disable calibration 32-kHz RC
// oscillator. 0: Calibration
// enabled 1: Calibration disabled
#define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS_M \
0x02000000
#define SYS_CTRL_CLOCK_STA_OSC32K_CALDIS_S 25
#define SYS_CTRL_CLOCK_STA_OSC32K \
0x01000000 // Current 32-kHz clock oscillator
// selected. 0: 32-kHz crystal
// oscillator 1: 32-kHz RC
// oscillator
#define SYS_CTRL_CLOCK_STA_OSC32K_M \
0x01000000
#define SYS_CTRL_CLOCK_STA_OSC32K_S 24
#define SYS_CTRL_CLOCK_STA_RST_M \
0x00C00000 // Returns last source of reset
// 00: POR 01: External reset 10:
// WDT 11: CLD or software reset
#define SYS_CTRL_CLOCK_STA_RST_S 22
#define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE \
0x00100000 // 0: System clock is not
// requested to change. 1: A change
// of system clock source has been
// initiated and is not finished.
// Same as when OSC bit in
// CLOCK_STA and CLOCK_CTRL
// register are not equal
#define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE_M \
0x00100000
#define SYS_CTRL_CLOCK_STA_SOURCE_CHANGE_S 20
#define SYS_CTRL_CLOCK_STA_XOSC_STB \
0x00080000 // XOSC stable status 0: XOSC is
// not powered up or not yet
// stable. 1: XOSC is powered up
// and stable.
#define SYS_CTRL_CLOCK_STA_XOSC_STB_M \
0x00080000
#define SYS_CTRL_CLOCK_STA_XOSC_STB_S 19
#define SYS_CTRL_CLOCK_STA_HSOSC_STB \
0x00040000 // HSOSC stable status 0: HSOSC is
// not powered up or not yet
// stable. 1: HSOSC is powered up
// and stable.
#define SYS_CTRL_CLOCK_STA_HSOSC_STB_M \
0x00040000
#define SYS_CTRL_CLOCK_STA_HSOSC_STB_S 18
#define SYS_CTRL_CLOCK_STA_OSC_PD \
0x00020000 // 0: Both oscillators powered up
// and stable and OSC_PD_CMD = 0.
// 1: Oscillator not selected by
// CLOCK_CTRL.OSC bit is powered
// down.
#define SYS_CTRL_CLOCK_STA_OSC_PD_M \
0x00020000
#define SYS_CTRL_CLOCK_STA_OSC_PD_S 17
#define SYS_CTRL_CLOCK_STA_OSC 0x00010000 // Current clock source selected
// 0: 32-MHz crystal oscillator 1:
// 16-MHz HF-RC oscillator
#define SYS_CTRL_CLOCK_STA_OSC_M \
0x00010000
#define SYS_CTRL_CLOCK_STA_OSC_S 16
#define SYS_CTRL_CLOCK_STA_IO_DIV_M \
0x00000700 // Returns current functional
// frequency for IO_CLK (may differ
// from setting in the CLOCK_CTRL
// register) 000: 32 MHz 001: 16
// MHz 010: 8 MHz 011: 4 MHz 100: 2
// MHz 101: 1 MHz 110: 0.5 MHz 111:
// 0.25 MHz
#define SYS_CTRL_CLOCK_STA_IO_DIV_S 8
#define SYS_CTRL_CLOCK_STA_RTCLK_FREQ_M \
0x00000018 // Returns current functional
// frequency for real-time clock.
// (may differ from setting in the
// CLOCK_CTRL register) 1x : 8 MHz
// 01: 2 MHz 00: 62.5 kHz
#define SYS_CTRL_CLOCK_STA_RTCLK_FREQ_S 3
#define SYS_CTRL_CLOCK_STA_SYS_DIV_M \
0x00000007 // Returns current functional
// frequency for system clock (may
// differ from setting in the
// CLOCK_CTRL register) 000: 32 MHz
// 001: 16 MHz 010: 8 MHz 011: 4
// MHz 100: 2 MHz 101: 1 MHz 110:
// 0.5 MHz 111: 0.25 MHz
#define SYS_CTRL_CLOCK_STA_SYS_DIV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCGPT register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCGPT_GPT3 0x00000008 // 0: Clock for GPT3 is gated. 1:
// Clock for GPT3 is enabled.
#define SYS_CTRL_RCGCGPT_GPT3_M 0x00000008
#define SYS_CTRL_RCGCGPT_GPT3_S 3
#define SYS_CTRL_RCGCGPT_GPT2 0x00000004 // 0: Clock for GPT2 is gated. 1:
// Clock for GPT2 is enabled.
#define SYS_CTRL_RCGCGPT_GPT2_M 0x00000004
#define SYS_CTRL_RCGCGPT_GPT2_S 2
#define SYS_CTRL_RCGCGPT_GPT1 0x00000002 // 0: Clock for GPT1 is gated. 1:
// Clock for GPT1 is enabled.
#define SYS_CTRL_RCGCGPT_GPT1_M 0x00000002
#define SYS_CTRL_RCGCGPT_GPT1_S 1
#define SYS_CTRL_RCGCGPT_GPT0 0x00000001 // 0: Clock for GPT0 is gated. 1:
// Clock for GPT0 is enabled.
#define SYS_CTRL_RCGCGPT_GPT0_M 0x00000001
#define SYS_CTRL_RCGCGPT_GPT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCGPT register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCGPT_GPT3 0x00000008 // 0: Clock for GPT3 is gated. 1:
// Clock for GPT3 is enabled.
#define SYS_CTRL_SCGCGPT_GPT3_M 0x00000008
#define SYS_CTRL_SCGCGPT_GPT3_S 3
#define SYS_CTRL_SCGCGPT_GPT2 0x00000004 // 0: Clock for GPT2 is gated. 1:
// Clock for GPT2 is enabled.
#define SYS_CTRL_SCGCGPT_GPT2_M 0x00000004
#define SYS_CTRL_SCGCGPT_GPT2_S 2
#define SYS_CTRL_SCGCGPT_GPT1 0x00000002 // 0: Clock for GPT1 is gated. 1:
// Clock for GPT1 is enabled.
#define SYS_CTRL_SCGCGPT_GPT1_M 0x00000002
#define SYS_CTRL_SCGCGPT_GPT1_S 1
#define SYS_CTRL_SCGCGPT_GPT0 0x00000001 // 0: Clock for GPT0 is gated. 1:
// Clock for GPT0 is enabled.
#define SYS_CTRL_SCGCGPT_GPT0_M 0x00000001
#define SYS_CTRL_SCGCGPT_GPT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCGPT register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCGPT_GPT3 0x00000008 // 0: Clock for GPT3 is gated. 1:
// Clock for GPT3 is enabled.
#define SYS_CTRL_DCGCGPT_GPT3_M 0x00000008
#define SYS_CTRL_DCGCGPT_GPT3_S 3
#define SYS_CTRL_DCGCGPT_GPT2 0x00000004 // 0: Clock for GPT2 is gated. 1:
// Clock for GPT2 is enabled.
#define SYS_CTRL_DCGCGPT_GPT2_M 0x00000004
#define SYS_CTRL_DCGCGPT_GPT2_S 2
#define SYS_CTRL_DCGCGPT_GPT1 0x00000002 // 0: Clock for GPT1 is gated. 1:
// Clock for GPT1 is enabled.
#define SYS_CTRL_DCGCGPT_GPT1_M 0x00000002
#define SYS_CTRL_DCGCGPT_GPT1_S 1
#define SYS_CTRL_DCGCGPT_GPT0 0x00000001 // 0: Clock for GPT0 is gated. 1:
// Clock for GPT0 is enabled.
#define SYS_CTRL_DCGCGPT_GPT0_M 0x00000001
#define SYS_CTRL_DCGCGPT_GPT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRGPT register.
//
//*****************************************************************************
#define SYS_CTRL_SRGPT_GPT3 0x00000008 // 0: GPT3 module is not reset 1:
// GPT3 module is reset
#define SYS_CTRL_SRGPT_GPT3_M 0x00000008
#define SYS_CTRL_SRGPT_GPT3_S 3
#define SYS_CTRL_SRGPT_GPT2 0x00000004 // 0: GPT2 module is not reset 1:
// GPT2 module is reset
#define SYS_CTRL_SRGPT_GPT2_M 0x00000004
#define SYS_CTRL_SRGPT_GPT2_S 2
#define SYS_CTRL_SRGPT_GPT1 0x00000002 // 0: GPT1 module is not reset 1:
// GPT1 module is reset
#define SYS_CTRL_SRGPT_GPT1_M 0x00000002
#define SYS_CTRL_SRGPT_GPT1_S 1
#define SYS_CTRL_SRGPT_GPT0 0x00000001 // 0: GPT0 module is not reset 1:
// GPT0 module is reset
#define SYS_CTRL_SRGPT_GPT0_M 0x00000001
#define SYS_CTRL_SRGPT_GPT0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCSSI register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCSSI_SSI1 0x00000002 // 0: Clock for SSI1 is gated. 1:
// Clock for SSI1 is enabled.
#define SYS_CTRL_RCGCSSI_SSI1_M 0x00000002
#define SYS_CTRL_RCGCSSI_SSI1_S 1
#define SYS_CTRL_RCGCSSI_SSI0 0x00000001 // 0: Clock for SSI0 is gated. 1:
// Clock for SSI0 is enabled.
#define SYS_CTRL_RCGCSSI_SSI0_M 0x00000001
#define SYS_CTRL_RCGCSSI_SSI0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCSSI register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCSSI_SSI1 0x00000002 // 0: Clock for SSI1 is gated. 1:
// Clock for SSI1 is enabled.
#define SYS_CTRL_SCGCSSI_SSI1_M 0x00000002
#define SYS_CTRL_SCGCSSI_SSI1_S 1
#define SYS_CTRL_SCGCSSI_SSI0 0x00000001 // 0: Clock for SSI0 is gated. 1:
// Clock for SSI0 is enabled.
#define SYS_CTRL_SCGCSSI_SSI0_M 0x00000001
#define SYS_CTRL_SCGCSSI_SSI0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCSSI register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCSSI_SSI1 0x00000002 // 0: Clock for SSI1 is gated. 1:
// Clock for SSI1 is enabled.
#define SYS_CTRL_DCGCSSI_SSI1_M 0x00000002
#define SYS_CTRL_DCGCSSI_SSI1_S 1
#define SYS_CTRL_DCGCSSI_SSI0 0x00000001 // 0: Clock for SSI0 is gated. 1:
// Clock for SSI0 is enabled.
#define SYS_CTRL_DCGCSSI_SSI0_M 0x00000001
#define SYS_CTRL_DCGCSSI_SSI0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRSSI register.
//
//*****************************************************************************
#define SYS_CTRL_SRSSI_SSI1 0x00000002 // 0: SSI1 module is not reset 1:
// SSI1 module is reset
#define SYS_CTRL_SRSSI_SSI1_M 0x00000002
#define SYS_CTRL_SRSSI_SSI1_S 1
#define SYS_CTRL_SRSSI_SSI0 0x00000001 // 0: SSI0 module is not reset 1:
// SSI0 module is reset
#define SYS_CTRL_SRSSI_SSI0_M 0x00000001
#define SYS_CTRL_SRSSI_SSI0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCUART register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCUART_UART1 0x00000002 // 0: Clock for UART1 is gated. 1:
// Clock for UART1 is enabled.
#define SYS_CTRL_RCGCUART_UART1_M \
0x00000002
#define SYS_CTRL_RCGCUART_UART1_S 1
#define SYS_CTRL_RCGCUART_UART0 0x00000001 // 0: Clock for UART0 is gated. 1:
// Clock for UART0 is enabled.
#define SYS_CTRL_RCGCUART_UART0_M \
0x00000001
#define SYS_CTRL_RCGCUART_UART0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCUART register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCUART_UART1 0x00000002 // 0: Clock for UART1 is gated. 1:
// Clock for UART1 is enabled.
#define SYS_CTRL_SCGCUART_UART1_M \
0x00000002
#define SYS_CTRL_SCGCUART_UART1_S 1
#define SYS_CTRL_SCGCUART_UART0 0x00000001 // 0: Clock for UART0 is gated. 1:
// Clock for UART0 is enabled.
#define SYS_CTRL_SCGCUART_UART0_M \
0x00000001
#define SYS_CTRL_SCGCUART_UART0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCUART register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCUART_UART1 0x00000002 // 0: Clock for UART1 is gated. 1:
// Clock for UART1 is enabled.
#define SYS_CTRL_DCGCUART_UART1_M \
0x00000002
#define SYS_CTRL_DCGCUART_UART1_S 1
#define SYS_CTRL_DCGCUART_UART0 0x00000001 // 0: Clock for UART0 is gated. 1:
// Clock for UART0 is enabled.
#define SYS_CTRL_DCGCUART_UART0_M \
0x00000001
#define SYS_CTRL_DCGCUART_UART0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRUART register.
//
//*****************************************************************************
#define SYS_CTRL_SRUART_UART1 0x00000002 // 0: UART1 module is not reset 1:
// UART1 module is reset
#define SYS_CTRL_SRUART_UART1_M 0x00000002
#define SYS_CTRL_SRUART_UART1_S 1
#define SYS_CTRL_SRUART_UART0 0x00000001 // 0: UART0 module is not reset 1:
// UART0 module is reset
#define SYS_CTRL_SRUART_UART0_M 0x00000001
#define SYS_CTRL_SRUART_UART0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCI2C register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCI2C_I2C0 0x00000001 // 0: Clock for I2C0 is gated. 1:
// Clock for I2C0 is enabled.
#define SYS_CTRL_RCGCI2C_I2C0_M 0x00000001
#define SYS_CTRL_RCGCI2C_I2C0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCI2C register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCI2C_I2C0 0x00000001 // 0: Clock for I2C0 is gated. 1:
// Clock for I2C0 is enabled.
#define SYS_CTRL_SCGCI2C_I2C0_M 0x00000001
#define SYS_CTRL_SCGCI2C_I2C0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCI2C register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCI2C_I2C0 0x00000001 // 0: Clock for I2C0 is gated. 1:
// Clock for I2C0 is enabled.
#define SYS_CTRL_DCGCI2C_I2C0_M 0x00000001
#define SYS_CTRL_DCGCI2C_I2C0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRI2C register.
//
//*****************************************************************************
#define SYS_CTRL_SRI2C_I2C0 0x00000001 // 0: I2C0 module is not reset 1:
// I2C0 module is reset
#define SYS_CTRL_SRI2C_I2C0_M 0x00000001
#define SYS_CTRL_SRI2C_I2C0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCSEC register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCSEC_AES 0x00000002 // 0: Clock for AES is gated. 1:
// Clock for AES is enabled.
#define SYS_CTRL_RCGCSEC_AES_M 0x00000002
#define SYS_CTRL_RCGCSEC_AES_S 1
#define SYS_CTRL_RCGCSEC_PKA 0x00000001 // 0: Clock for PKA is gated. 1:
// Clock for PKA is enabled.
#define SYS_CTRL_RCGCSEC_PKA_M 0x00000001
#define SYS_CTRL_RCGCSEC_PKA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCSEC register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCSEC_AES 0x00000002 // 0: Clock for AES is gated. 1:
// Clock for AES is enabled.
#define SYS_CTRL_SCGCSEC_AES_M 0x00000002
#define SYS_CTRL_SCGCSEC_AES_S 1
#define SYS_CTRL_SCGCSEC_PKA 0x00000001 // 0: Clock for PKA is gated. 1:
// Clock for PKA is enabled.
#define SYS_CTRL_SCGCSEC_PKA_M 0x00000001
#define SYS_CTRL_SCGCSEC_PKA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCSEC register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCSEC_AES 0x00000002 // 0: Clock for AES is gated. 1:
// Clock for AES is enabled.
#define SYS_CTRL_DCGCSEC_AES_M 0x00000002
#define SYS_CTRL_DCGCSEC_AES_S 1
#define SYS_CTRL_DCGCSEC_PKA 0x00000001 // 0: Clock for PKA is gated. 1:
// Clock for PKA is enabled.
#define SYS_CTRL_DCGCSEC_PKA_M 0x00000001
#define SYS_CTRL_DCGCSEC_PKA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRSEC register.
//
//*****************************************************************************
#define SYS_CTRL_SRSEC_AES 0x00000002 // 0: AES module is not reset 1:
// AES module is reset
#define SYS_CTRL_SRSEC_AES_M 0x00000002
#define SYS_CTRL_SRSEC_AES_S 1
#define SYS_CTRL_SRSEC_PKA 0x00000001 // 0: PKA module is not reset 1:
// PKA module is reset
#define SYS_CTRL_SRSEC_PKA_M 0x00000001
#define SYS_CTRL_SRSEC_PKA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_PMCTL register.
//
//*****************************************************************************
#define SYS_CTRL_PMCTL_PM_M 0x00000003 // 00: No action 01: PM1 10: PM2
// 11: PM3
#define SYS_CTRL_PMCTL_PM_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SRCRC register.
//
//*****************************************************************************
#define SYS_CTRL_SRCRC_CRC_REN_USB \
0x00000100 // 1: Enable reset of chip if CRC
// fails. 0: Disable reset feature
// of chip due to CRC.
#define SYS_CTRL_SRCRC_CRC_REN_USB_M \
0x00000100
#define SYS_CTRL_SRCRC_CRC_REN_USB_S 8
#define SYS_CTRL_SRCRC_CRC_REN_RF \
0x00000001 // 1: Enable reset of chip if CRC
// fails. 0: Disable reset feature
// of chip due to CRC.
#define SYS_CTRL_SRCRC_CRC_REN_RF_M \
0x00000001
#define SYS_CTRL_SRCRC_CRC_REN_RF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_PWRDBG register.
//
//*****************************************************************************
#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET \
0x00000008 // 0: No action 1: When written
// high, the chip is reset in the
// same manner as a CLD event and
// is readable from the RST field
// in the CLOCK_STA register.
#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET_M \
0x00000008
#define SYS_CTRL_PWRDBG_FORCE_WARM_RESET_S 3
//*****************************************************************************
//
// The following are defines for the bit fields in the SYS_CTRL_CLD register.
//
//*****************************************************************************
#define SYS_CTRL_CLD_VALID 0x00000100 // 0: CLD status in always-on
// domain is not equal to status in
// the EN register. 1: CLD status
// in always-on domain and EN
// register are equal.
#define SYS_CTRL_CLD_VALID_M 0x00000100
#define SYS_CTRL_CLD_VALID_S 8
#define SYS_CTRL_CLD_EN 0x00000001 // 0: CLD is disabled. 1: CLD is
// enabled. Writing to this
// register shall be ignored if
// VALID = 0
#define SYS_CTRL_CLD_EN_M 0x00000001
#define SYS_CTRL_CLD_EN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the SYS_CTRL_IWE register.
//
//*****************************************************************************
#define SYS_CTRL_IWE_SM_TIMER_IWE \
0x00000020 // 1: Enable SM Timer wake-up
// interrupt. 0: Disable SM Timer
// wake-up interrupt.
#define SYS_CTRL_IWE_SM_TIMER_IWE_M \
0x00000020
#define SYS_CTRL_IWE_SM_TIMER_IWE_S 5
#define SYS_CTRL_IWE_USB_IWE 0x00000010 // 1: Enable USB wake-up
// interrupt. 0: Disable USB
// wake-up interrupt.
#define SYS_CTRL_IWE_USB_IWE_M 0x00000010
#define SYS_CTRL_IWE_USB_IWE_S 4
#define SYS_CTRL_IWE_PORT_D_IWE 0x00000008 // 1: Enable port D wake-up
// interrupt. 0: Disable port D
// wake-up interrupt.
#define SYS_CTRL_IWE_PORT_D_IWE_M \
0x00000008
#define SYS_CTRL_IWE_PORT_D_IWE_S 3
#define SYS_CTRL_IWE_PORT_C_IWE 0x00000004 // 1: Enable port C wake-up
// interrupt. 0: Disable port C
// wake-up interrupt.
#define SYS_CTRL_IWE_PORT_C_IWE_M \
0x00000004
#define SYS_CTRL_IWE_PORT_C_IWE_S 2
#define SYS_CTRL_IWE_PORT_B_IWE 0x00000002 // 1: Enable port B wake-up
// interrupt. 0: Disable port B
// wake-up interrupt.
#define SYS_CTRL_IWE_PORT_B_IWE_M \
0x00000002
#define SYS_CTRL_IWE_PORT_B_IWE_S 1
#define SYS_CTRL_IWE_PORT_A_IWE 0x00000001 // 1: Enable port A wake-up
// interrupt. 0: Disable port A
// wake-up interrupt.
#define SYS_CTRL_IWE_PORT_A_IWE_M \
0x00000001
#define SYS_CTRL_IWE_PORT_A_IWE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_I_MAP register.
//
//*****************************************************************************
#define SYS_CTRL_I_MAP_ALTMAP 0x00000001 // 1: Select alternate interrupt
// map. 0: Select regular interrupt
// map. (See the ASD document for
// details.)
#define SYS_CTRL_I_MAP_ALTMAP_M 0x00000001
#define SYS_CTRL_I_MAP_ALTMAP_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_RCGCRFC register.
//
//*****************************************************************************
#define SYS_CTRL_RCGCRFC_RFC0 0x00000001 // 0: Clock for RF CORE is gated.
// 1: Clock for RF CORE is enabled.
#define SYS_CTRL_RCGCRFC_RFC0_M 0x00000001
#define SYS_CTRL_RCGCRFC_RFC0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_SCGCRFC register.
//
//*****************************************************************************
#define SYS_CTRL_SCGCRFC_RFC0 0x00000001 // 0: Clock for RF CORE is gated.
// 1: Clock for RF CORE is enabled.
#define SYS_CTRL_SCGCRFC_RFC0_M 0x00000001
#define SYS_CTRL_SCGCRFC_RFC0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_DCGCRFC register.
//
//*****************************************************************************
#define SYS_CTRL_DCGCRFC_RFC0 0x00000001 // 0: Clock for RF CORE is gated.
// 1: Clock for RF CORE is enabled.
#define SYS_CTRL_DCGCRFC_RFC0_M 0x00000001
#define SYS_CTRL_DCGCRFC_RFC0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// SYS_CTRL_EMUOVR register.
//
//*****************************************************************************
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_CG \
0x00000080 // ICEPick 'Force Active' clock
// gate override bit. 'Force
// Active' is an ICEPick command. 1
// --> In non-sleep power mode,
// peripherals clocks are forced to
// follow RCG* register settings.
// It forces CM3 clocks on. 0 -->
// Does not affect the peripheral
// clock settings.
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_CG_M \
0x00000080
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_CG_S 7
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_CG \
0x00000040 // ICEPick 'Force Power' clock
// gate override bit. 'Force Power'
// is an ICEPick command. 1 --> In
// non-sleep power mode,
// peripherals clocks are forced to
// follow RCG* register settings.
// It forces CM3 clocks on. 0 -->
// Does not affect the peripheral
// clock settings.
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_CG_M \
0x00000040
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_CG_S 6
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_CG \
0x00000020 // ICEPick 'Inhibit Sleep' clock
// gate override bit. 'Inhibit
// Sleep' is an ICEPick command. 1
// --> In non-sleep power mode,
// peripherals clocks are forced to
// follow RCG* register settings.
// It forces CM3 clocks on. 0 -->
// Does not affect the peripheral
// clock settings.
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_CG_M \
0x00000020
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_CG_S 5
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_CG \
0x00000010 // ICEMelter 'WAKEUPEMU' clock
// gate override bit. 1 --> In
// non-sleep power mode,
// peripherals clocks are forced to
// follow RCG* register settings.
// It forces CM3 clocks on. 0 -->
// Does not affect the peripheral
// clock settings
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_CG_M \
0x00000010
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_CG_S 4
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_PM \
0x00000008 // ICEPick 'Force Active' power
// mode override bit. 'Force
// Active' is an ICEPick command. 1
// --> Prohibit the system to go
// into any power down modes. Keeps
// the emulator attached. 0 -->
// Does not override any power mode
// settings from SYSREGS and does
// not prohibit system to go into
// any power down modes.
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_PM_M \
0x00000008
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_CLOCK_PM_S 3
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_PM \
0x00000004 // ICEPick 'Force Power' power
// mode override bit. 'Force Power'
// is an ICEPick command. 1 -->
// Prohibit the system to go into
// any power down modes. Keeps the
// emulator attached. 0 --> Does
// not override any power mode
// settings from SYSREGS and does
// not prohibit system to go into
// any power down modes.
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_PM_M \
0x00000004
#define SYS_CTRL_EMUOVR_ICEPICK_FORCE_POWER_PM_S 2
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_PM \
0x00000002 // ICEPick 'Inhibit Sleep' power
// mode override bit. 'Inhibit
// Sleep' is an ICEPick command. 1
// --> Prohibit the system to go
// into any power down modes. Keeps
// the emulator attached. 0 -->
// Does not override any power mode
// settings from SYSREGS and does
// not prohibit system to go into
// any power down modes.
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_PM_M \
0x00000002
#define SYS_CTRL_EMUOVR_ICEPICK_INHIBIT_SLEEP_PM_S 1
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_PM \
0x00000001 // ICEMelter 'WAKEUPEMU' power
// mode override bit. 1 -->
// Prohibit the system to go into
// any power down modes. Keeps the
// emulator attached. 0 --> Does
// not override any power mode
// settings from SYSREGS and does
// not prohibit system to go into
// any power down modes.
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_PM_M \
0x00000001
#define SYS_CTRL_EMUOVR_ICEMELTER_WKUP_PM_S 0
#endif // __HW_SYS_CTRL_H__

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/******************************************************************************
* Filename: hw_types.h
* Revised: $Date: 2013-04-29 09:49:55 +0200 (Mon, 29 Apr 2013) $
* Revision: $Revision: 9923 $
*
* Description: Common types and macros.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_TYPES_H__
#define __HW_TYPES_H__
#include <stdint.h>
#include <stdbool.h>
//*****************************************************************************
//
// Define a boolean type, and values for true and false.
//
//*****************************************************************************
typedef unsigned char tBoolean;
#ifndef true
#define true 1
#endif
#ifndef false
#define false 0
#endif
//*****************************************************************************
//
// Macros for hardware access, both direct and via the bit-band region.
//
//*****************************************************************************
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#define HWREGB(x) \
(*((volatile unsigned char *)(x)))
#define HWREGBITW(x, b) \
HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITH(x, b) \
HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#define HWREGBITB(x, b) \
HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
(((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
#endif // __HW_TYPES_H__

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/******************************************************************************
* Filename: hw_udma.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the UDMA register offsets.
//
//*****************************************************************************
#define UDMA_STAT 0x400FF000 // DMA status The STAT register
// returns the status of the uDMA
// controller. This register cannot
// be read when the uDMA controller
// is in the reset state.
#define UDMA_CFG 0x400FF004 // DMA configuration The CFG
// register controls the
// configuration of the uDMA
// controller.
#define UDMA_CTLBASE 0x400FF008 // DMA channel control base
// pointer The CTLBASE register
// must be configured so that the
// base pointer points to a
// location in system memory. The
// amount of system memory that
// must be assigned to the uDMA
// controller depends on the number
// of uDMA channels used and
// whether the alternate channel
// control data structure is used.
// See Section 10.2.5 for details
// about the Channel Control Table.
// The base address must be aligned
// on a 1024-byte boundary. This
// register cannot be read when the
// uDMA controller is in the reset
// state.
#define UDMA_ALTBASE 0x400FF00C // DMA alternate channel control
// base pointer The ALTBASE
// register returns the base
// address of the alternate channel
// control data. This register
// removes the necessity for
// application software to
// calculate the base address of
// the alternate channel control
// structures. This register cannot
// be read when the uDMA controller
// is in the reset state.
#define UDMA_WAITSTAT 0x400FF010 // DMA channel wait-on-request
// status This read-only register
// indicates that the uDMA channel
// is waiting on a request. A
// peripheral can hold off the uDMA
// from performing a single request
// until the peripheral is ready
// for a burst request to enhance
// the uDMA performance. The use of
// this feature is dependent on the
// design of the peripheral and is
// not controllable by software in
// any way. This register cannot be
// read when the uDMA controller is
// in the reset state.
#define UDMA_SWREQ 0x400FF014 // DMA channel software request
// Each bit of the SWREQ register
// represents the corresponding
// uDMA channel. Setting a bit
// generates a request for the
// specified uDMA channel.
#define UDMA_USEBURSTSET 0x400FF018 // DMA channel useburst set Each
// bit of the USEBURSTSET register
// represents the corresponding
// uDMA channel. Setting a bit
// disables the channel single
// request input from generating
// requests, configuring the
// channel to only accept burst
// requests. Reading the register
// returns the status of USEBURST.
// If the amount of data to
// transfer is a multiple of the
// arbitration (burst) size, the
// corresponding SET[n] bit is
// cleared after completing the
// final transfer. If there are
// fewer items remaining to
// transfer than the arbitration
// (burst) size, the uDMA
// controller automatically clears
// the corresponding SET[n] bit,
// allowing the remaining items to
// transfer using single requests.
// To resume transfers using burst
// requests, the corresponding bit
// must be set again. A bit must
// not be set if the corresponding
// peripheral does not support the
// burst request model.
#define UDMA_USEBURSTCLR 0x400FF01C // DMA channel useburst clear Each
// bit of the USEBURSTCLR register
// represents the corresponding
// uDMA channel. Setting a bit
// clears the corresponding SET[n]
// bit in the USEBURSTSET register.
#define UDMA_REQMASKSET 0x400FF020 // DMA channel request mask set
// Each bit of the REQMASKSET
// register represents the
// corresponding uDMA channel.
// Setting a bit disables uDMA
// requests for the channel.
// Reading the register returns the
// request mask status. When a uDMA
// channel request is masked, that
// means the peripheral can no
// longer request uDMA transfers.
// The channel can then be used for
// software-initiated transfers.
#define UDMA_REQMASKCLR 0x400FF024 // DMA channel request mask clear
// Each bit of the REQMASKCLR
// register represents the
// corresponding uDMA channel.
// Setting a bit clears the
// corresponding SET[n] bit in the
// REQMASKSET register.
#define UDMA_ENASET 0x400FF028 // DMA channel enable set Each bit
// of the ENASET register
// represents the corresponding
// uDMA channel. Setting a bit
// enables the corresponding uDMA
// channel. Reading the register
// returns the enable status of the
// channels. If a channel is
// enabled but the request mask is
// set (REQMASKSET), then the
// channel can be used for
// software-initiated transfers.
#define UDMA_ENACLR 0x400FF02C // DMA channel enable clear Each
// bit of the ENACLR register
// represents the corresponding
// uDMA channel. Setting a bit
// clears the corresponding SET[n]
// bit in the ENASET register.
#define UDMA_ALTSET 0x400FF030 // DMA channel primary alternate
// set Each bit of the ALTSET
// register represents the
// corresponding uDMA channel.
// Setting a bit configures the
// uDMA channel to use the
// alternate control data
// structure. Reading the register
// returns the status of which
// control data structure is in use
// for the corresponding uDMA
// channel.
#define UDMA_ALTCLR 0x400FF034 // DMA channel primary alternate
// clear Each bit of the ALTCLR
// register represents the
// corresponding uDMA channel.
// Setting a bit clears the
// corresponding SET[n] bit in the
// ALTSET register.
#define UDMA_PRIOSET 0x400FF038 // DMA channel priority set Each
// bit of the PRIOSET register
// represents the corresponding
// uDMA channel. Setting a bit
// configures the uDMA channel to
// have a high priority level.
// Reading the register returns the
// status of the channel priority
// mask.
#define UDMA_PRIOCLR 0x400FF03C // DMA channel priority clear Each
// bit of the DMAPRIOCLR register
// represents the corresponding
// uDMA channel. Setting a bit
// clears the corresponding SET[n]
// bit in the PRIOSET register.
#define UDMA_ERRCLR 0x400FF04C // DMA bus error clear The ERRCLR
// register is used to read and
// clear the uDMA bus error status.
// The error status is set if the
// uDMA controller encountered a
// bus error while performing a
// transfer. If a bus error occurs
// on a channel, that channel is
// automatically disabled by the
// uDMA controller. The other
// channels are unaffected.
#define UDMA_CHASGN 0x400FF500 // DMA channel assignment Each bit
// of the CHASGN register
// represents the corresponding
// uDMA channel. Setting a bit
// selects the secondary channel
// assignment as specified in the
// section "Channel Assignments"
#define UDMA_CHIS 0x400FF504 // DMA channel interrupt status
// Each bit of the CHIS register
// represents the corresponding
// uDMA channel. A bit is set when
// that uDMA channel causes a
// completion interrupt. The bits
// are cleared by writing 1.
#define UDMA_CHMAP0 0x400FF510 // DMA channel map select 0 Each
// 4-bit field of the CHMAP0
// register configures the uDMA
// channel assignment as specified
// in the uDMA channel assignment
// table in the "Channel
// Assignments" section.
#define UDMA_CHMAP1 0x400FF514 // DMA channel map select 1 Each
// 4-bit field of the CHMAP1
// register configures the uDMA
// channel assignment as specified
// in the uDMA channel assignment
// table in the "Channel
// Assignments" section.
#define UDMA_CHMAP2 0x400FF518 // DMA channel map select 2 Each
// 4-bit field of the CHMAP2
// register configures the uDMA
// channel assignment as specified
// in the uDMA channel assignment
// table in the "Channel
// Assignments" section.
#define UDMA_CHMAP3 0x400FF51C // DMA channel map select 3 Each
// 4-bit field of the CHMAP3
// register configures the uDMA
// channel assignment as specified
// in the uDMA channel assignment
// table in the "Channel
// Assignments" section.
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_STAT register.
//
//*****************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA channels minus 1
// This field contains a value
// equal to the number of uDMA
// channels the uDMA controller is
// configured to use, minus one.
// The value of 0x1F corresponds to
// 32 uDMA channels.
#define UDMA_STAT_DMACHANS_S 16
#define UDMA_STAT_STATE_M 0x000000F0 // Control state machine status
// This field shows the current
// status of the control
// state-machine. Status can be one
// of the following: 0x0: Idle 0x1:
// Reading channel controller data
// 0x2: Reading source end pointer
// 0x3: Reading destination end
// pointer 0x4: Reading source data
// 0x5: Writing destination data
// 0x6: Waiting for uDMA request to
// clear 0x7: Writing channel
// controller data 0x8: Stalled
// 0x9: Done 0xA-0xF: Undefined
#define UDMA_STAT_STATE_S 4
#define UDMA_STAT_MASTEN 0x00000001 // Master enable status 0: The
// uDMA controller is disabled. 1:
// The uDMA controller is enabled.
#define UDMA_STAT_MASTEN_M 0x00000001
#define UDMA_STAT_MASTEN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CFG register.
//
//*****************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller master enable 0:
// Disables the uDMA controller. 1:
// Enables the uDMA controller.
#define UDMA_CFG_MASTEN_M 0x00000001
#define UDMA_CFG_MASTEN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CTLBASE register.
//
//*****************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel control base address
// This field contains the pointer
// to the base address of the
// channel control table. The base
// address must be 1024-byte
// alligned.
#define UDMA_CTLBASE_ADDR_S 10
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTBASE register.
//
//*****************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate channel address
// pointer This field provides the
// base address of the alternate
// channel control structures.
#define UDMA_ALTBASE_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_WAITSTAT register.
//
//*****************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] wait status These
// bits provide the tchannel
// wait-on-request status. Bit 0
// corresponds to channel 0. 1: The
// corresponding channel is waiting
// on a request. 0: The
// corresponding channel is not
// waiting on a request.
#define UDMA_WAITSTAT_WAITREQ_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_SWREQ register.
//
//*****************************************************************************
#define UDMA_SWREQ_SWREQ_M 0xFFFFFFFF // Channel [n] software request
// These bits generate software
// requests. Bit 0 corresponds to
// channel 0. 1: Generate a
// software request for the
// corresponding channel 0: No
// request generated These bits are
// automatically cleared when the
// software request has been
// completed.
#define UDMA_SWREQ_SWREQ_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_USEBURSTSET register.
//
//*****************************************************************************
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] useburst set 0:
// uDMA channel [n] responds to
// single or burst requests. 1:
// uDMA channel [n] responds only
// to burst requests. Bit 0
// corresponds to channel 0. This
// bit is automatically cleared as
// described above. A bit can also
// be manually cleared by setting
// the corresponding CLR[n] bit in
// the DMAUSEBURSTCLR register.
#define UDMA_USEBURSTSET_SET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_USEBURSTCLR register.
//
//*****************************************************************************
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] useburst clear 0:
// No effect 1: Setting a bit
// clears the corresponding SET[n]
// bit in the DMAUSEBURSTSET
// register meaning that uDMA
// channel [n] responds to single
// and burst requests.
#define UDMA_USEBURSTCLR_CLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_REQMASKSET register.
//
//*****************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] request mask set 0:
// The peripheral associated with
// channel [n] is enabled to
// request uDMA transfers 1: The
// peripheral associated with
// channel [n] is not able to
// request uDMA transfers. Channel
// [n] may be used for
// software-initiated transfers.
// Bit 0 corresponds to channel 0.
// A bit can only be cleared by
// setting the corresponding CLR[n]
// bit in the DMAREQMASKCLR
// register.
#define UDMA_REQMASKSET_SET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_REQMASKCLR register.
//
//*****************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] request mask clear
// 0: No effect 1: Setting a bit
// clears the corresponding SET[n]
// bit in the DMAREQMASKSET
// register meaning that the
// peripheral associated with
// channel [n] is enabled to
// request uDMA transfers.
#define UDMA_REQMASKCLR_CLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENASET register.
//
//*****************************************************************************
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] enable set 0: uDMA
// channel [n] is disabled 1: uDMA
// channel [n] is enabled Bit 0
// corresponds to channel 0. A bit
// can only be cleared by setting
// the corresponding CLR[n] bit in
// the DMAENACLR register.
#define UDMA_ENASET_SET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ENACLR register.
//
//*****************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Channel [n] enable clear 0: No
// effect 1: Setting a bit clears
// the corresponding SET[n] bit in
// the DMAENASET register meaning
// that channel [n] is disabled for
// uDMA transfers. Note: The
// controller disables a channel
// when it completes the uDMA
// cycle.
#define UDMA_ENACLR_CLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTSET register.
//
//*****************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] alternate set 0:
// uDMA channel [n] is using the
// primary control structure 1:
// uDMA channel [n] is using the
// alternate control structure Bit
// 0 corresponds to channel 0. A
// bit can only be cleared by
// setting the corresponding CLR[n]
// bit in the DMAALTCLR register.
// Note: For Ping-Pong and
// Scatter-Gather cycle types, the
// uDMA controller automatically
// sets these bits to select the
// alternate channel control data
// structure.
#define UDMA_ALTSET_SET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ALTCLR register.
//
//*****************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] alternate clear 0:
// No effect 1: Setting a bit
// clears the corresponding SET[n]
// bit in the DMAALTSET register
// meaning that channel [n] is
// using the primary control
// structure. Note: For Ping-Pong
// and Scatter-Gather cycle types,
// the uDMA controller
// automatically sets these bits to
// select the alternate channel
// control data structure.
#define UDMA_ALTCLR_CLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOSET register.
//
//*****************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] priority set 0:
// uDMA channel [n] is using the
// default priority level 1: uDMA
// channel [n] is using a high
// priority level Bit 0 corresponds
// to channel 0. A bit can only be
// cleared by setting the
// corresponding CLR[n] bit in the
// DMAPRIOCLR register.
#define UDMA_PRIOSET_SET_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_PRIOCLR register.
//
//*****************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] priority clear 0:
// No effect 1: Setting a bit
// clears the corresponding SET[n]
// bit in the DMAPRIOSET register
// meaning that channel [n] is
// using the default priority
// level.
#define UDMA_PRIOCLR_CLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_ERRCLR register.
//
//*****************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA bus error status 0: No bus
// error is pending 1: A bus error
// is pending This bit is cleared
// by writing 1 to it.
#define UDMA_ERRCLR_ERRCLR_M 0x00000001
#define UDMA_ERRCLR_ERRCLR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHASGN register.
//
//*****************************************************************************
#define UDMA_CHASGN_CHASGN_M 0xFFFFFFFF // Channel [n] assignment select
// 0: Use the primary channel
// assignment 1: Use the secondary
// channel assignment
#define UDMA_CHASGN_CHASGN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHIS register.
//
//*****************************************************************************
#define UDMA_CHIS_CHIS_M 0xFFFFFFFF // Channel [n] interrupt status 0:
// The corresponding uDMA channel
// has not caused an interrupt. 1:
// The corresponding uDMA channel
// has caused an interrupt. This
// bit is cleared by writing 1 to
// it.
#define UDMA_CHIS_CHIS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP0 register.
//
//*****************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA channel 7 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA channel 6 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA channel 5 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA channel 4 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA channel 3 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA channel 2 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA channel 1 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA channel 0 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP0_CH0SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP1 register.
//
//*****************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA channel 15 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA channel 14 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA channel 13 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA channel 12 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA channel 11 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA channel 10 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA channel 9 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA channel 8 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP1_CH8SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP2 register.
//
//*****************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA channel 23 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA channel 22 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA channel 21 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA channel 20 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA channel 19 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA channel 18 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA channel 17 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA channel 16 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP2_CH16SEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_CHMAP3 register.
//
//*****************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA channel 31 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA channel 30 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA channel 29 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA channel 28 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA channel 27 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA channel 26 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA channel 25 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA channel 24 source select
// See section titled "Channel
// Assignments" in Micro Direct
// Memory Access chapter.
#define UDMA_CHMAP3_CH24SEL_S 0
#endif // __HW_UDMA_H__

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/******************************************************************************
* Filename: hw_udmachctl.h
* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
* Revision: $Revision: 9735 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_UDMACHCTL_H__
#define __HW_UDMACHCTL_H__
//*****************************************************************************
//
// The following are defines for the UDMACHCTL register offsets.
//
//*****************************************************************************
#define UDMACHCTL_O_SRCENDP 0x00000000
#define UDMACHCTL_O_DSTENDP 0x00000004
#define UDMACHCTL_O_CHCTL 0x00000008
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMACHCTL_O_SRCENDP register.
//
//*****************************************************************************
#define UDMACHCTL_SRCENDP_ADDR_M \
0xFFFFFFFF // Source address end pointer This
// field points to the last address
// of the uDMA transfer source
// (inclusive). If the source
// address is not incrementing (the
// SRCINC field in the DMACHCTL
// register is 0x3), then this
// field points at the source
// location itself (such as a
// peripheral control register).
#define UDMACHCTL_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMACHCTL_O_DSTENDP register.
//
//*****************************************************************************
#define UDMACHCTL_DSTENDP_ADDR_M \
0xFFFFFFFF // Destination address end pointer
// This field points to the last
// address of the uDMA transfer
// destination (inclusive). If the
// destination address is not
// incrementing (the DSTINC field
// in the DMACHCTL register is
// 0x3), then this field points at
// the destination location itself
// (such as a peripheral control
// register).
#define UDMACHCTL_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// UDMACHCTL_O_CHCTL register.
//
//*****************************************************************************
#define UDMACHCTL_CHCTL_DSTINC_M \
0xC0000000 // Destination address increment
// This field configures the
// destination address increment.
// The address increment value must
// be equal or greater than the
// value of the destination size
// (DSTSIZE). 0x0: Byte - Increment
// by 8-bit locations 0x1:
// Half-word - Increment by 16-bit
// locations 0x2: Word - Increment
// by 32-bit locations 0x3: No
// increment - Address remains set
// to the value of the Destination
// address end pointer (DMADSTENDP)
// for the channel.
#define UDMACHCTL_CHCTL_DSTINC_S 30
#define UDMACHCTL_CHCTL_DSTSIZE_M \
0x30000000 // Destination data size This
// field configures the destination
// item data size. Note: DSTSIZE
// must be the same as SRCSIZE.
// 0x0: Byte - 8-bit data size 0x1:
// Half-word - 16-bit data size
// 0x2: Word - 32-bit data size
// 0x3: Reserved
#define UDMACHCTL_CHCTL_DSTSIZE_S 28
#define UDMACHCTL_CHCTL_SRCINC_M \
0x0C000000 // Source address increment This
// field configures the source
// address increment. The address
// increment value must be equal or
// greater than the value of the
// source size (SRCSIZE). 0x0: Byte
// - Increment by 8-bit locations
// 0x1: Half-word - Increment by
// 16-bit locations 0x2: Word -
// Increment by 32-bit locations
// 0x3: No increment - Address
// remains set to the value of the
// Source address end pointer
// (DMASRCENDP) for the channel.
#define UDMACHCTL_CHCTL_SRCINC_S 26
#define UDMACHCTL_CHCTL_SRCSIZE_M \
0x03000000 // Source data size This field
// configures the source item data
// size. Note: SRCSIZE must be the
// same as DSTSIZE. 0x0: Byte -
// 8-bit data size 0x1: Half-word -
// 16-bit data size 0x2: Word -
// 32-bit data size 0x3: Reserved
#define UDMACHCTL_CHCTL_SRCSIZE_S 24
#define UDMACHCTL_CHCTL_ARBSIZE_M \
0x0003C000 // Arbitration size This field
// configures the number of
// transfers that can occur before
// the uDMA controller
// re-arbitrates. The possible
// arbitration rate configurations
// represent powers of 2 and are
// shown below. 0x0: 1 Transfer -
// Arbitrates after each uDMA
// transfer 0x1: 2 Transfers 0x2: 4
// Transfers 0x3: 8 Transfers 0x4:
// 16 Transfers 0x5: 32 Transfers
// 0x6: 64 Transfers 0x7: 128
// Transfers 0x8: 256 Transfers
// 0x9: 512 Transfers 0xA-0xF: 1024
// Transfers - In this
// configuration, no arbitration
// occurs during the uDMA transfer
// because the maximum transfer
// size is 1024.
#define UDMACHCTL_CHCTL_ARBSIZE_S 14
#define UDMACHCTL_CHCTL_XFERSIZE_M \
0x00003FF0 // Transfer size (minus 1) This
// field configures the total
// number of items to transfer. The
// value of this field is 1 less
// than the number to transfer
// (value 0 means transfer 1 item).
// The maximum value for this
// 10-bit field is 1023which
// represents a transfer size of
// 1024 items. The transfer size is
// the number of items, not the
// number of bytes, If the data
// size is 32 bits, then this value
// is the number of 32-bit words to
// transfer. The uDMA controller
// updates this field immediately
// before entering the arbitration
// process, so it contrains the
// number of outstanding items that
// is necessary to complete the
// uDMA cycle.
#define UDMACHCTL_CHCTL_XFERSIZE_S 4
#define UDMACHCTL_CHCTL_NXTUSEBURST \
0x00000008 // Next useburst This field
// controls whether the Useburst
// SET[n] bit is automatically set
// for the last transfer of a
// peripheral scatter-gather
// operation. Normally, for the
// last transfer, if the number of
// remaining items to transfer is
// less than the arbitration size,
// the uDMA controller uses single
// transfers to complete the
// transaction. If this bit is set,
// then the controller uses a burst
// transfer to complete the last
// transfer.
#define UDMACHCTL_CHCTL_NXTUSEBURST_M \
0x00000008
#define UDMACHCTL_CHCTL_NXTUSEBURST_S 3
#define UDMACHCTL_CHCTL_XFERMODE_M \
0x00000007 // uDMA transfer mode This field
// configures the operating mode of
// the uDMA cycle. Refer to "Micro
// Direct Memory Access - Transfer
// Modes" for a detailed
// explanation of transfer modes.
// Because this register is in
// system RAM, it has no reset
// value. Therefore, this field
// should be initialized to 0
// before the channel is enabled.
// 0x0: Stop 0x1: Basic 0x2:
// Auto-request 0x3: Ping-pong 0x4:
// Memory scatter-gather 0x5:
// Alternate memory scatter-gather
// 0x6: Peripheral scatter-gather
// 0x7: Alternate peripheral
// scatter-gather
#define UDMACHCTL_CHCTL_XFERMODE_S 0
#endif // __HW_UDMACHCTL_H__

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/******************************************************************************
* Filename: hw_usb.h
* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
* Revision: $Revision: 9943 $
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef __HW_USB_H__
#define __HW_USB_H__
//*****************************************************************************
//
// The following are defines for the USB register offsets.
//
//*****************************************************************************
#define USB_ADDR 0x40089000 // Function address
#define USB_POW 0x40089004 // Power management and control
// register
#define USB_IIF 0x40089008 // Interrupt flags for endpoint 0
// and IN endpoints 1-5
#define USB_OIF 0x40089010 // Interrupt flags for OUT
// endpoints 1-5
#define USB_CIF 0x40089018 // Common USB interrupt flags
#define USB_IIE 0x4008901C // Interrupt enable mask for IN
// endpoints 1-5 and endpoint 0
#define USB_OIE 0x40089024 // Interrupt enable mask for OUT
// endpoints 1-5
#define USB_CIE 0x4008902C // Common USB interrupt enable
// mask
#define USB_FRML 0x40089030 // Frame number (low byte)
#define USB_FRMH 0x40089034 // Frame number (high byte)
#define USB_INDEX 0x40089038 // Index register for selecting
// the endpoint status and control
// registers
#define USB_CTRL 0x4008903C // USB peripheral control register
#define USB_MAXI 0x40089040 // Indexed register: For USB_INDEX
// = 1-5: Maximum packet size for
// IN endpoint {1-5}
#define USB_CS0_CSIL 0x40089044 // Indexed register: For USB_INDEX
// = 0: Endpoint 0 control and
// status For USB_INDEX = 1-5: IN
// endpoint {1-5} control and
// status (low byte)
#define USB_CSIH 0x40089048 // Indexed register: For USB_INDEX
// = 1-5: IN endpoint {1-5} control
// and status (high byte)
#define USB_MAXO 0x4008904C // Indexed register: For USB_INDEX
// = 1-5: Maximum packet size for
// OUT endpoint {1-5}
#define USB_CSOL 0x40089050 // Indexed register: For USB_INDEX
// = 1-5: OUT endpoint {1-5}
// control and status (low byte)
#define USB_CSOH 0x40089054 // Indexed register: For USB_INDEX
// = 1-5: OUT endpoint {1-5}
// control and status (high byte)
#define USB_CNT0_CNTL 0x40089058 // Indexed register: For USB_INDEX
// = 0: Number of received bytes in
// the endpoint 0 FIFO For
// USB_INDEX = 1-5: Number of
// received bytes in the OUT
// endpoint {1-5} FIFO (low byte)
#define USB_CNTH 0x4008905C // Indexed register: For USB_INDEX
// = 1-5: Number of received in the
// OUT endpoint {1-5} FIFO (high
// byte)
#define USB_F0 0x40089080 // Endpoint 0 FIFO
#define USB_F1 0x40089088 // IN/OUT endpoint 1 FIFO
#define USB_F2 0x40089090 // IN/OUT endpoint 2 FIFO
#define USB_F3 0x40089098 // IN/OUT endpoint 3 FIFO
#define USB_F4 0x400890A0 // IN/OUT endpoint 4 FIFO
#define USB_F5 0x400890A8 // IN/OUT endpoint 5 FIFO
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_ADDR register.
//
//*****************************************************************************
#define USB_ADDR_UPDATE 0x00000080 // This bit is set by hardware
// when writing to this register,
// and is cleared by hardware when
// the new address becomes
// effective.
#define USB_ADDR_UPDATE_M 0x00000080
#define USB_ADDR_UPDATE_S 7
#define USB_ADDR_USBADDR_M 0x0000007F // Device address. The address
// shall be updated upon successful
// completion of the status stage
// of the SET_ADDRESS request.
#define USB_ADDR_USBADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_POW register.
//
//*****************************************************************************
#define USB_POW_ISOWAITSOF 0x00000080 // For isochronous mode IN
// endpoints: When set, the USB
// controller will wait for an SOF
// token from the time
// USB_CSIL.INPKTRDY is set before
// sending the packet. If an IN
// token is received before an SOF
// token, then a zero length data
// packet will be sent.
#define USB_POW_ISOWAITSOF_M 0x00000080
#define USB_POW_ISOWAITSOF_S 7
#define USB_POW_RST 0x00000008 // Indicates that reset signaling
// is present on the bus
#define USB_POW_RST_M 0x00000008
#define USB_POW_RST_S 3
#define USB_POW_RESUME 0x00000004 // Drives resume signaling for
// remote wakeup According to the
// USB Specification, the resume
// signal must be held active for
// at least 1 ms and no more than
// 15 ms. It is recommended to keep
// this bit set for approximately
// 10 ms.
#define USB_POW_RESUME_M 0x00000004
#define USB_POW_RESUME_S 2
#define USB_POW_SUSPEND 0x00000002 // Indicates entry into suspend
// mode Suspend mode must be
// enabled by setting
// USB_POW.SUSPENDEN Software
// clears this bit by reading the
// USB_CIF register or by asserting
// USB_POW.RESUME
#define USB_POW_SUSPEND_M 0x00000002
#define USB_POW_SUSPEND_S 1
#define USB_POW_SUSPENDEN 0x00000001 // Enables detection of and entry
// into suspend mode.
#define USB_POW_SUSPENDEN_M 0x00000001
#define USB_POW_SUSPENDEN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_IIF register.
//
//*****************************************************************************
#define USB_IIF_INEP5IF 0x00000020 // Interrupt flag for IN endpoint
// 5 Cleared by hardware when read
#define USB_IIF_INEP5IF_M 0x00000020
#define USB_IIF_INEP5IF_S 5
#define USB_IIF_INEP4IF 0x00000010 // Interrupt flag for IN endpoint
// 4 Cleared by hardware when read
#define USB_IIF_INEP4IF_M 0x00000010
#define USB_IIF_INEP4IF_S 4
#define USB_IIF_INEP3IF 0x00000008 // Interrupt flag for IN endpoint
// 3 Cleared by hardware when read
#define USB_IIF_INEP3IF_M 0x00000008
#define USB_IIF_INEP3IF_S 3
#define USB_IIF_INEP2IF 0x00000004 // Interrupt flag for IN endpoint
// 2 Cleared by hardware when read
#define USB_IIF_INEP2IF_M 0x00000004
#define USB_IIF_INEP2IF_S 2
#define USB_IIF_INEP1IF 0x00000002 // Interrupt flag for IN endpoint
// 1 Cleared by hardware when read
#define USB_IIF_INEP1IF_M 0x00000002
#define USB_IIF_INEP1IF_S 1
#define USB_IIF_EP0IF 0x00000001 // Interrupt flag for endpoint 0
// Cleared by hardware when read
#define USB_IIF_EP0IF_M 0x00000001
#define USB_IIF_EP0IF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_OIF register.
//
//*****************************************************************************
#define USB_OIF_OUTEP5IF 0x00000020 // Interrupt flag for OUT endpoint
// 5 Cleared by hardware when read
#define USB_OIF_OUTEP5IF_M 0x00000020
#define USB_OIF_OUTEP5IF_S 5
#define USB_OIF_OUTEP4IF 0x00000010 // Interrupt flag for OUT endpoint
// 4 Cleared by hardware when read
#define USB_OIF_OUTEP4IF_M 0x00000010
#define USB_OIF_OUTEP4IF_S 4
#define USB_OIF_OUTEP3IF 0x00000008 // Interrupt flag for OUT endpoint
// 3 Cleared by hardware when read
#define USB_OIF_OUTEP3IF_M 0x00000008
#define USB_OIF_OUTEP3IF_S 3
#define USB_OIF_OUTEP2IF 0x00000004 // Interrupt flag for OUT endpoint
// 2 Cleared by hardware when read
#define USB_OIF_OUTEP2IF_M 0x00000004
#define USB_OIF_OUTEP2IF_S 2
#define USB_OIF_OUTEP1IF 0x00000002 // Interrupt flag for OUT endpoint
// 1 Cleared by hardware when read
#define USB_OIF_OUTEP1IF_M 0x00000002
#define USB_OIF_OUTEP1IF_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CIF register.
//
//*****************************************************************************
#define USB_CIF_SOFIF 0x00000008 // Start-of-frame interrupt flag
// Cleared by hardware when read
#define USB_CIF_SOFIF_M 0x00000008
#define USB_CIF_SOFIF_S 3
#define USB_CIF_RSTIF 0x00000004 // Reset interrupt flag Cleared by
// hardware when read
#define USB_CIF_RSTIF_M 0x00000004
#define USB_CIF_RSTIF_S 2
#define USB_CIF_RESUMEIF 0x00000002 // Resume interrupt flag Cleared
// by hardware when read
#define USB_CIF_RESUMEIF_M 0x00000002
#define USB_CIF_RESUMEIF_S 1
#define USB_CIF_SUSPENDIF 0x00000001 // Suspend interrupt flag Cleared
// by hardware when read
#define USB_CIF_SUSPENDIF_M 0x00000001
#define USB_CIF_SUSPENDIF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_IIE register.
//
//*****************************************************************************
#define USB_IIE_INEP5IE 0x00000020 // Interrupt enable for IN
// endpoint 5 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_IIE_INEP5IE_M 0x00000020
#define USB_IIE_INEP5IE_S 5
#define USB_IIE_INEP4IE 0x00000010 // Interrupt enable for IN
// endpoint 4 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_IIE_INEP4IE_M 0x00000010
#define USB_IIE_INEP4IE_S 4
#define USB_IIE_INEP3IE 0x00000008 // Interrupt enable for IN
// endpoint 3 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_IIE_INEP3IE_M 0x00000008
#define USB_IIE_INEP3IE_S 3
#define USB_IIE_INEP2IE 0x00000004 // Interrupt enable for IN
// endpoint 2 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_IIE_INEP2IE_M 0x00000004
#define USB_IIE_INEP2IE_S 2
#define USB_IIE_INEP1IE 0x00000002 // Interrupt enable for IN
// endpoint 1 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_IIE_INEP1IE_M 0x00000002
#define USB_IIE_INEP1IE_S 1
#define USB_IIE_EP0IE 0x00000001 // Interrupt enable for endpoint 0
// 0: Interrupt disabled 1:
// Interrupt enabled
#define USB_IIE_EP0IE_M 0x00000001
#define USB_IIE_EP0IE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_OIE register.
//
//*****************************************************************************
#define USB_OIE_reserved8_M 0x000000C0 // Reserved
#define USB_OIE_reserved8_S 6
#define USB_OIE_OUTEP5IE 0x00000020 // Interrupt enable for OUT
// endpoint 5 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_OIE_OUTEP5IE_M 0x00000020
#define USB_OIE_OUTEP5IE_S 5
#define USB_OIE_OUTEP4IE 0x00000010 // Interrupt enable for OUT
// endpoint 4 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_OIE_OUTEP4IE_M 0x00000010
#define USB_OIE_OUTEP4IE_S 4
#define USB_OIE_OUTEP3IE 0x00000008 // Interrupt enable for OUT
// endpoint 3 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_OIE_OUTEP3IE_M 0x00000008
#define USB_OIE_OUTEP3IE_S 3
#define USB_OIE_OUTEP2IE 0x00000004 // Interrupt enable for OUT
// endpoint 2 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_OIE_OUTEP2IE_M 0x00000004
#define USB_OIE_OUTEP2IE_S 2
#define USB_OIE_OUTEP1IE 0x00000002 // Interrupt enable for OUT
// endpoint 1 0: Interrupt disabled
// 1: Interrupt enabled
#define USB_OIE_OUTEP1IE_M 0x00000002
#define USB_OIE_OUTEP1IE_S 1
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CIE register.
//
//*****************************************************************************
#define USB_CIE_SOFIE 0x00000008 // Start-of-frame interrupt enable
// 0: Interrupt disabled 1:
// Interrupt enabled
#define USB_CIE_SOFIE_M 0x00000008
#define USB_CIE_SOFIE_S 3
#define USB_CIE_RSTIE 0x00000004 // Reset interrupt enable 0:
// Interrupt disabled 1: Interrupt
// enabled
#define USB_CIE_RSTIE_M 0x00000004
#define USB_CIE_RSTIE_S 2
#define USB_CIE_RESUMEIE 0x00000002 // Resume interrupt enable 0:
// Interrupt disabled 1: Interrupt
// enabled
#define USB_CIE_RESUMEIE_M 0x00000002
#define USB_CIE_RESUMEIE_S 1
#define USB_CIE_SUSPENDIE 0x00000001 // Suspend interrupt enable 0:
// Interrupt disabled 1: Interrupt
// enabled
#define USB_CIE_SUSPENDIE_M 0x00000001
#define USB_CIE_SUSPENDIE_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_FRML register.
//
//*****************************************************************************
#define USB_FRML_FRAMEL_M 0x000000FF // Bits 7:0 of the 11-bit frame
// number The frame number is only
// updated upon successful
// reception of SOF tokens
#define USB_FRML_FRAMEL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_FRMH register.
//
//*****************************************************************************
#define USB_FRMH_FRAMEH_M 0x00000007 // Bits 10:8 of the 11-bit frame
// number The frame number is only
// updated upon successful
// reception of SOF tokens
#define USB_FRMH_FRAMEH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_INDEX register.
//
//*****************************************************************************
#define USB_INDEX_USBINDEX_M 0x0000000F // Index of the currently selected
// endpoint The index is set to 0
// to enable access to endpoint 0
// control and status registers The
// index is set to 1, 2, 3, 4 or 5
// to enable access to IN/OUT
// endpoint 1, 2, 3, 4 or 5 control
// and status registers,
// respectively
#define USB_INDEX_USBINDEX_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CTRL register.
//
//*****************************************************************************
#define USB_CTRL_PLLLOCKED 0x00000080 // PLL lock status. The PLL is
// locked when USB_CTRL.PLLLOCKED
// is 1.
#define USB_CTRL_PLLLOCKED_M 0x00000080
#define USB_CTRL_PLLLOCKED_S 7
#define USB_CTRL_PLLEN 0x00000002 // 48 MHz USB PLL enable When this
// bit is set, the 48 MHz PLL is
// started. Software must avoid
// access to other USB registers
// before the PLL has locked; that
// is, USB_CTRL.PLLLOCKED is 1.
// This bit can be set only when
// USB_CTRL.USBEN is 1. The PLL
// must be disabled before entering
// PM1 when suspended, and must be
// re-enabled when resuming
// operation.
#define USB_CTRL_PLLEN_M 0x00000002
#define USB_CTRL_PLLEN_S 1
#define USB_CTRL_USBEN 0x00000001 // USB enable The USB controller
// is reset when this bit is
// cleared
#define USB_CTRL_USBEN_M 0x00000001
#define USB_CTRL_USBEN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_MAXI register.
//
//*****************************************************************************
#define USB_MAXI_USBMAXI_M 0x000000FF // Maximum packet size, in units
// of 8 bytes, for the selected IN
// endpoint The value of this
// register should match the
// wMaxPacketSize field in the
// standard endpoint descriptor for
// the endpoint. The value must not
// exceed the available memory.
#define USB_MAXI_USBMAXI_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CS0_CSIL register.
//
//*****************************************************************************
#define USB_CS0_CSIL_CLROUTPKTRDY_or_CLRDATATOG \
0x00000040 // USB_CS0.CLROUTPKTRDY [RW]:
// Software sets this bit to clear
// the USB_CS0.OUTPKTRDY bit. It is
// cleared automatically.
// USB_CSIL.CLRDATATOG [RW]:
// Software sets this bit to reset
// the IN endpoint data toggle to
// 0.
#define USB_CS0_CSIL_CLROUTPKTRDY_or_CLRDATATOG_M \
0x00000040
#define USB_CS0_CSIL_CLROUTPKTRDY_or_CLRDATATOG_S 6
#define USB_CS0_CSIL_SENDSTALL_or_SENTSTALL \
0x00000020 // USB_CS0.SENDSTALL [RW]:
// Software sets this bit to
// terminate the current
// transaction with a STALL
// handshake. The bit is cleared
// automatically when the STALL
// handshake has been transmitted.
// USB_CSIL.SENTSTALL [RW]: For
// bulk/interrupt mode IN
// endpoints: This bit is set when
// a STALL handshake is
// transmitted. The FIFO is flushed
// and the USB_CSIL.INPKTRDY bit
// cleared. Software should clear
// this bit.
#define USB_CS0_CSIL_SENDSTALL_or_SENTSTALL_M \
0x00000020
#define USB_CS0_CSIL_SENDSTALL_or_SENTSTALL_S 5
#define USB_CS0_CSIL_SETUPEND_or_SENDSTALL \
0x00000010 // USB_CS0.SETUPEND [RO]: This bit
// is set when a control
// transaction ends before the
// USB_CS0.DATAEND bit has been
// set. An interrupt is generated
// and the FIFO flushed at this
// time. Software clears this bit
// by setting USB_CS0.CLRSETUPEND.
// CSIL.SENDSTALL [RW]: For
// bulk/interrupt mode IN
// endpoints: Software sets this
// bit to issue a STALL handshake.
// Software clears this bit to
// terminate the stall condition.
#define USB_CS0_CSIL_SETUPEND_or_SENDSTALL_M \
0x00000010
#define USB_CS0_CSIL_SETUPEND_or_SENDSTALL_S 4
#define USB_CS0_CSIL_DATAEND_or_FLUSHPACKET \
0x00000008 // USB_CS0.DATAEND [RW]: This bit
// is used to signal the end of the
// data stage, and must be set: 1.
// When the last data packet is
// loaded and USB_CS0.INPKTRDY is
// set. 2. When the last data
// packet is unloaded and
// USB_CS0.CLROUTPKTRDY is set. 3.
// When USB_CS0.INPKTRDY is set to
// send a zero-length packet. The
// USB controller clears this bit
// automatically.
// USB_CSIL.FLUSHPACKET [RW]:
// Software sets this bit to flush
// the next packet to be
// transmitted from the IN endpoint
// FIFO. The FIFO pointer is reset
// and the USB_CSIL.INPKTRDY bit is
// cleared. Note: If the FIFO
// contains two packets,
// USB_CSIL.FLUSHPACKET will need
// to be set twice to completely
// clear the FIFO.
#define USB_CS0_CSIL_DATAEND_or_FLUSHPACKET_M \
0x00000008
#define USB_CS0_CSIL_DATAEND_or_FLUSHPACKET_S 3
#define USB_CS0_CSIL_SENTSTALL_or_UNDERRUN \
0x00000004 // USB_CS0.SENTSTALL [RW]: This
// bit is set when a STALL
// handshake is sent. An interrupt
// is generated is generated when
// this bit is set. Software must
// clear this bit.
// USB_CSIL.UNDERRUN [RW]: In
// isochronous mode, this bit is
// set when a zero length data
// packet is sent after receiving
// an IN token with
// USB_CSIL.INPKTRDY not set. In
// bulk/interrupt mode, this bit is
// set when a NAK is returned in
// response to an IN token.
// Software should clear this bit.
#define USB_CS0_CSIL_SENTSTALL_or_UNDERRUN_M \
0x00000004
#define USB_CS0_CSIL_SENTSTALL_or_UNDERRUN_S 2
#define USB_CS0_CSIL_INPKTRDY_or_PKTPRESENT \
0x00000002 // USB_CS0. INPKTRDY [RW]:
// Software sets this bit after
// loading a data packet into the
// endpoint 0 FIFO. It is cleared
// automatically when the data
// packet has been transmitted. An
// interrupt is generated when the
// bit is cleared.
// USB_CSIL.PKTPRESENT [RO]: This
// bit is set when there is at
// least one packet in the IN
// endpoint FIFO.
#define USB_CS0_CSIL_INPKTRDY_or_PKTPRESENT_M \
0x00000002
#define USB_CS0_CSIL_INPKTRDY_or_PKTPRESENT_S 1
#define USB_CS0_CSIL_OUTPKTRDY_or_INPKTRDY \
0x00000001 // USB_CS0.OUTPKTRDY [RO]:
// Endpoint 0 data packet received
// An interrupt request (EP0) is
// generated if the interrupt is
// enabled. Software must read the
// endpoint 0 FIFO empty, and clear
// this bit by setting
// USB_CS0.CLROUTPKTRDY
// USB_CSIL.INPKTRDY [RW]: IN
// endpoint {1-5} packet transfer
// pending Software sets this bit
// after loading a data packet into
// the FIFO. It is cleared
// automatically when a data packet
// has been transmitted. An
// interrupt is generated (if
// enabled) when the bit is
// cleared. When using
// double-buffering, the bit is
// cleared immediately if the other
// FIFO is empty.
#define USB_CS0_CSIL_OUTPKTRDY_or_INPKTRDY_M \
0x00000001
#define USB_CS0_CSIL_OUTPKTRDY_or_INPKTRDY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CSIH register.
//
//*****************************************************************************
#define USB_CSIH_AUTISET 0x00000080 // If set by software, the
// USB_CSIL.INPKTRDY bit is
// automatically set when a data
// packet of maximum size
// (specified by USBMAXI) is loaded
// into the IN endpoint FIFO. If a
// packet of less than the maximum
// packet size is loaded, then
// USB_CSIL.INPKTRDY will have to
// be set manually.
#define USB_CSIH_AUTISET_M 0x00000080
#define USB_CSIH_AUTISET_S 7
#define USB_CSIH_ISO 0x00000040 // Selects IN endpoint type: 0:
// Bulk/interrupt 1: Isochronous
#define USB_CSIH_ISO_M 0x00000040
#define USB_CSIH_ISO_S 6
#define USB_CSIH_FORCEDATATOG 0x00000008 // Software sets this bit to force
// the IN endpoint's data toggle to
// switch after each data packet is
// sent regardless of whether an
// ACK was received. This can be
// used by interrupt IN endpoints
// which are used to communicate
// rate feedback for isochronous
// endpoints.
#define USB_CSIH_FORCEDATATOG_M 0x00000008
#define USB_CSIH_FORCEDATATOG_S 3
#define USB_CSIH_INDBLBUF 0x00000001 // IN endpoint FIFO
// double-buffering enable: 0:
// Double buffering disabled 1:
// Double buffering enabled
#define USB_CSIH_INDBLBUF_M 0x00000001
#define USB_CSIH_INDBLBUF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_MAXO register.
//
//*****************************************************************************
#define USB_MAXO_USBMAXO_M 0x000000FF // Maximum packet size, in units
// of 8 bytes, for the selected OUT
// endpoint The value of this
// register should match the
// wMaxPacketSize field in the
// standard endpoint descriptor for
// the endpoint. The value must not
// exceed the available memory.
#define USB_MAXO_USBMAXO_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CSOL register.
//
//*****************************************************************************
#define USB_CSOL_CLRDATATOG 0x00000080 // Software sets this bit to reset
// the endpoint data toggle to 0.
#define USB_CSOL_CLRDATATOG_M 0x00000080
#define USB_CSOL_CLRDATATOG_S 7
#define USB_CSOL_SENTSTALL 0x00000040 // This bit is set when a STALL
// handshake is transmitted. An
// interrupt is generated when this
// bit is set. Software should
// clear this bit.
#define USB_CSOL_SENTSTALL_M 0x00000040
#define USB_CSOL_SENTSTALL_S 6
#define USB_CSOL_SENDSTALL 0x00000020 // For bulk/interrupt mode OUT
// endpoints: Software sets this
// bit to issue a STALL handshake.
// Software clears this bit to
// terminate the stall condition.
#define USB_CSOL_SENDSTALL_M 0x00000020
#define USB_CSOL_SENDSTALL_S 5
#define USB_CSOL_FLUSHPACKET 0x00000010 // Software sets this bit to flush
// the next packet to be read from
// the endpoint OUT FIFO. Note: If
// the FIFO contains two packets,
// USB_CSOL.FLUSHPACKET will need
// to be set twice to completely
// clear the FIFO.
#define USB_CSOL_FLUSHPACKET_M 0x00000010
#define USB_CSOL_FLUSHPACKET_S 4
#define USB_CSOL_DATAERROR 0x00000008 // For isochronous mode OUT
// endpoints: This bit is set when
// USB_CSOL.OUTPKTRDY is set if the
// data packet has a CRC or
// bit-stuff error. It is cleared
// automatically when
// USB_CSOL.OUTPKTRDY is cleared.
#define USB_CSOL_DATAERROR_M 0x00000008
#define USB_CSOL_DATAERROR_S 3
#define USB_CSOL_OVERRUN 0x00000004 // For isochronous mode OUT
// endpoints: This bit is set when
// an OUT packet cannot be loaded
// into the OUT endpoint FIFO.
// Firmware should clear this bit.
#define USB_CSOL_OVERRUN_M 0x00000004
#define USB_CSOL_OVERRUN_S 2
#define USB_CSOL_FIFOFULL 0x00000002 // This bit is set when no more
// packets can be loaded into the
// OUT endpoint FIFO.
#define USB_CSOL_FIFOFULL_M 0x00000002
#define USB_CSOL_FIFOFULL_S 1
#define USB_CSOL_OUTPKTRDY 0x00000001 // This bit is set when a data
// packet has been received.
// Software should clear this bit
// when the packet has been
// unloaded from the OUT endpoint
// FIFO. An interrupt is generated
// when the bit is set.
#define USB_CSOL_OUTPKTRDY_M 0x00000001
#define USB_CSOL_OUTPKTRDY_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CSOH register.
//
//*****************************************************************************
#define USB_CSOH_AUTOCLEAR 0x00000080 // If software sets this bit, the
// USB_CSOL.OUTPKTRDY bit will be
// automatically cleared when a
// packet of maximum size
// (specified by USB_MAXO) has been
// unloaded from the OUT FIFO. When
// packets of less than the maximum
// packet size are unloaded,
// USB_CSOL.OUTPKTRDY will have to
// be cleared manually.
#define USB_CSOH_AUTOCLEAR_M 0x00000080
#define USB_CSOH_AUTOCLEAR_S 7
#define USB_CSOH_ISO 0x00000040 // Selects OUT endpoint type: 0:
// Bulk/interrupt 1: Isochronous
#define USB_CSOH_ISO_M 0x00000040
#define USB_CSOH_ISO_S 6
#define USB_CSOH_OUTDBLBUF 0x00000001 // OUT endpoint FIFO
// double-buffering enable: 0:
// Double buffering disabled 1:
// Double buffering enabled
#define USB_CSOH_OUTDBLBUF_M 0x00000001
#define USB_CSOH_OUTDBLBUF_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the
// USB_CNT0_CNTL register.
//
//*****************************************************************************
#define USB_CNT0_CNTL_FIFOCNT_or_FIFOCNTL_M \
0x000000FF // USB_CS0.FIFOCNT (USBINDEX = 0)
// [RO]: Number of bytes received
// in the packet in the endpoint 0
// FIFO Valid only when
// USB_CS0.OUTPKTRDY is set
// USB_CSIL.FIFOCNTL (USBINDEX = 1
// to 5) [RW]: Bits 7:0 of the of
// the number of bytes received in
// the packet in the OUT endpoint
// {1-5} FIFO Valid only when
// USB_CSOL.OUTPKTRDY is set
#define USB_CNT0_CNTL_FIFOCNT_or_FIFOCNTL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_CNTH register.
//
//*****************************************************************************
#define USB_CNTH_FIFOCNTH_M 0x00000007 // Bits 10:8 of the of the number
// of bytes received in the packet
// in the OUT endpoint {1-5} FIFO
// Valid only when
// USB_CSOL.OUTPKTRDY is set
#define USB_CNTH_FIFOCNTH_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F0 register.
//
//*****************************************************************************
#define USB_F0_USBF0_M 0x000000FF // Endpoint 0 FIFO Reading this
// register unloads one byte from
// the endpoint 0 FIFO. Writing to
// this register loads one byte
// into the endpoint 0 FIFO. The
// FIFO memory for EP0 is used for
// incoming and outgoing data
// packets.
#define USB_F0_USBF0_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F1 register.
//
//*****************************************************************************
#define USB_F1_USBF1_M 0x000000FF // Endpoint 1 FIFO register
// Reading this register unloads
// one byte from the EP1 OUT FIFO.
// Writing to this register loads
// one byte into the EP1 IN FIFO.
#define USB_F1_USBF1_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F2 register.
//
//*****************************************************************************
#define USB_F2_USBF2_M 0x000000FF // Endpoint 2 FIFO register
// Reading this register unloads
// one byte from the EP2 OUT FIFO.
// Writing to this register loads
// one byte into the EP2 IN FIFO.
#define USB_F2_USBF2_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F3 register.
//
//*****************************************************************************
#define USB_F3_USBF3_M 0x000000FF // Endpoint 3 FIFO register
// Reading this register unloads
// one byte from the EP3 OUT FIFO.
// Writing to this register loads
// one byte into the EP3 IN FIFO.
#define USB_F3_USBF3_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F4 register.
//
//*****************************************************************************
#define USB_F4_USBF4_M 0x000000FF // Endpoint 4 FIFO register
// Reading this register unloads
// one byte from the EP4 OUT FIFO.
// Writing to this register loads
// one byte into the EP4 IN FIFO.
#define USB_F4_USBF4_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the USB_F5 register.
//
//*****************************************************************************
#define USB_F5_USBF5_M 0x000000FF // Endpoint 5 FIFO register
// Reading this register unloads
// one byte from the EP5 OUT FIFO.
// Writing to this register loads
// one byte into the EP5 IN FIFO.
#define USB_F5_USBF5_S 0
#endif // __HW_USB_H__