diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h index 409be6b0ad..0056d47869 100644 --- a/cpu/stm32/include/clk/clk_conf.h +++ b/cpu/stm32/include/clk/clk_conf.h @@ -39,10 +39,8 @@ #elif defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F7) #include "f2f4f7/cfg_clock_default.h" -#elif defined(CPU_FAM_STM32G0) -#include "g0/cfg_clock_default.h" -#elif defined(CPU_FAM_STM32G4) -#include "g4/cfg_clock_default.h" +#elif defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) +#include "g0g4/cfg_clock_default.h" #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) #include "l0l1/cfg_clock_default.h" #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \ diff --git a/cpu/stm32/include/clk/g0/cfg_clock_default.h b/cpu/stm32/include/clk/g0g4/cfg_clock_default.h similarity index 68% rename from cpu/stm32/include/clk/g0/cfg_clock_default.h rename to cpu/stm32/include/clk/g0g4/cfg_clock_default.h index 3f530ea11c..07c22fcf05 100644 --- a/cpu/stm32/include/clk/g0/cfg_clock_default.h +++ b/cpu/stm32/include/clk/g0g4/cfg_clock_default.h @@ -11,7 +11,7 @@ * @{ * * @file - * @brief Configure STM32G0 clock + * @brief Configure STM32G0/G4 clock * * CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz. * Default configuration use PLL clock as system clock. PLL input clock is HSI @@ -20,15 +20,15 @@ * @author Alexandre Abadie */ -#ifndef CLK_G0_CFG_CLOCK_DEFAULT_H -#define CLK_G0_CFG_CLOCK_DEFAULT_H +#ifndef CLK_G0G4_CFG_CLOCK_DEFAULT_H +#define CLK_G0G4_CFG_CLOCK_DEFAULT_H #ifdef __cplusplus extern "C" { #endif /** - * @name G0 clock settings + * @name G0/G4 clock settings * * @{ */ @@ -36,9 +36,11 @@ extern "C" { #error "HSE clock frequency must be between 4MHz and 48MHz" #endif +#ifdef CPU_FAM_STM32G0 #ifndef CONFIG_CLOCK_HSISYS_DIV #define CONFIG_CLOCK_HSISYS_DIV (1) #endif +#endif #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #define CLOCK_PLL_SRC (CLOCK_HSE) @@ -48,17 +50,33 @@ extern "C" { /* The following parameters configure a 64MHz system clock with HSI as input clock */ #ifndef CONFIG_CLOCK_PLL_M +#ifdef CPU_FAM_STM32G0 #define CONFIG_CLOCK_PLL_M (1) +#else +#define CONFIG_CLOCK_PLL_M (4) +#endif #endif #ifndef CONFIG_CLOCK_PLL_N +#ifdef CPU_FAM_STM32G0 #define CONFIG_CLOCK_PLL_N (20) +#else +#define CONFIG_CLOCK_PLL_N (85) +#endif #endif #ifndef CONFIG_CLOCK_PLL_R +#ifdef CPU_FAM_STM32G0 #define CONFIG_CLOCK_PLL_R (5) +#else +#define CONFIG_CLOCK_PLL_R (2) +#endif #endif #if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#ifdef CPU_FAM_STM32G0 #define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) +#else +#define CLOCK_CORECLOCK (CLOCK_HSI) +#endif #elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) #if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) @@ -69,22 +87,34 @@ extern "C" { #elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK \ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R +#ifdef CPU_FAM_STM32G0 #if CLOCK_CORECLOCK > MHZ(64) #error "SYSCLK cannot exceed 64MHz" #endif +#else /* CPU_FAM_STM32G4 */ +#if CLOCK_CORECLOCK > MHZ(170) +#error "SYSCLK cannot exceed 170MHz" +#endif +#endif #endif /* CONFIG_USE_CLOCK_PLL */ -#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz */ +#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz (G0), 170MHZ (G4) */ #ifndef CONFIG_CLOCK_APB1_DIV #define CONFIG_CLOCK_APB1_DIV (1) #endif -#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz */ +#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */ +#ifdef CPU_FAM_STM32G4 +#ifndef CONFIG_CLOCK_APB2_DIV +#define CONFIG_CLOCK_APB2_DIV (1) +#endif +#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz (only on G4) */ +#endif /** @} */ #ifdef __cplusplus } #endif -#endif /* CLK_G0_CFG_CLOCK_DEFAULT_H */ +#endif /* CLK_G0G4_CFG_CLOCK_DEFAULT_H */ /** @} */ diff --git a/cpu/stm32/include/clk/g4/cfg_clock_default.h b/cpu/stm32/include/clk/g4/cfg_clock_default.h deleted file mode 100644 index a46f740c9e..0000000000 --- a/cpu/stm32/include/clk/g4/cfg_clock_default.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (C) 2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Configure STM32G4 clock - * - * @author Alexandre Abadie - */ - -#ifndef CLK_G4_CFG_CLOCK_DEFAULT_H -#define CLK_G4_CFG_CLOCK_DEFAULT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @name G4 clock settings - * @{ - */ -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) -#error "HSE clock frequency must be between 4MHz and 48MHz" -#endif - -#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) -#endif - -/* The following parameters configure a 170MHz system clock with HSI16 as input clock */ -#ifndef CONFIG_CLOCK_PLL_M -#define CONFIG_CLOCK_PLL_M (4) -#endif -#ifndef CONFIG_CLOCK_PLL_N -#define CONFIG_CLOCK_PLL_N (85) -#endif -#ifndef CONFIG_CLOCK_PLL_R -#define CONFIG_CLOCK_PLL_R (2) -#endif - -#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) -#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) -#error "The board doesn't provide an HSE oscillator" -#endif -#define CLOCK_CORECLOCK (CLOCK_HSE) - -#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) -#define CLOCK_CORECLOCK \ - ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R -#if CLOCK_CORECLOCK > MHZ(170) -#error "SYSCLK cannot exceed 170MHz" -#endif -#endif /* CONFIG_USE_CLOCK_PLL */ - -#define CLOCK_AHB CLOCK_CORECLOCK /* max: 170MHz */ - -#ifndef CONFIG_CLOCK_APB1_DIV -#define CONFIG_CLOCK_APB1_DIV (1) -#endif -#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */ -#ifndef CONFIG_CLOCK_APB2_DIV -#define CONFIG_CLOCK_APB2_DIV (1) -#endif -#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */ - -#ifdef __cplusplus -} -#endif - -#endif /* CLK_G4_CFG_CLOCK_DEFAULT_H */ -/** @} */