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cpu/stm32_common: update doc

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Vincent Dupont 2017-08-24 20:30:04 +02:00
parent 60be58ea6d
commit e005554b48
1 changed files with 15 additions and 5 deletions
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20
cpu/stm32_common/doc.txt
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@ -8,10 +8,10 @@
* @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4, * @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4,
* @ref cpu_stm32l4, @ref cpu_stm32f7. * @ref cpu_stm32l4, @ref cpu_stm32f7.
* *
* STM32F[2|4|7] Clock configuration * STM32Fx Clock configuration
* ================================= * =================================
* *
* stm32f2, stm32f4 and stm32f7 cpus share clock configuration code and macro. * stm32fx cpus share clock configuration code and macro.
* It can be configured as described here. * It can be configured as described here.
* *
* The following macro must be defined in the board's periph_conf.h: * The following macro must be defined in the board's periph_conf.h:
@ -22,16 +22,26 @@
* - CLOCK_AHB_DIV, CLOCK_AHB: AHB prescaler in register value and AHB frequecny in Hz * - CLOCK_AHB_DIV, CLOCK_AHB: AHB prescaler in register value and AHB frequecny in Hz
* - CLOCK_APB1_DIV, CLOCK_APB1: APB1 prescaler in register value and APB1 frequecny in Hz * - CLOCK_APB1_DIV, CLOCK_APB1: APB1 prescaler in register value and APB1 frequecny in Hz
* - CLOCK_APB2_DIV, CLOCK_APB2: APB2 prescaler in register value and APB2 frequecny in Hz * - CLOCK_APB2_DIV, CLOCK_APB2: APB2 prescaler in register value and APB2 frequecny in Hz
* - CLOCK_PLL_M, CLOCK_PLL_N, CLOCK_PLL_P, CLOCK_PLL_Q: Main PLL factors * (CLOCK_APB2_DIV is not needed for stm32f0)
*
* The following macro must be defined for stm32f[2|4|7]:
* - CLOCK_PLL_M, CLOCK_PLL_N, CLOCK_PLL_P, CLOCK_PLL_Q, (CLOCK_PLL_R, optional):
* Main PLL factors
*
* The following macro must be defined for stm32f[0|1|3]:
* - PLL_MUL, PLL_PREDIV: PLL factors. These values are used as is. A PREDIV of 2
* can be assumed when HSI is selected as PLL input. Some model support any value
* as PREDIV even with HSI though. The `clk_conf` tool will assume PREDIV must be
* to with HSI and will set it accordingly.
* *
* The following macro are optional and can be defined depending on board config * The following macro are optional and can be defined depending on board config
* and application needs: * and application needs:
* - CLOCK_ENABLE_PLL_I2S: if a second PLL (PLL I2S) is available on the cpu, it * - CLOCK_ENABLE_PLL_I2S: if a second PLL (PLL I2S) is available on the cpu, it
* can be activated with this macro, then CLOCK_PLL_I2S_M, CLOCK_PLL_I2S_N, * can be activated with this macro, then CLOCK_PLL_I2S_M, CLOCK_PLL_I2S_N,
* CLOCK_PLL_I2S_P and CLOCK_PLL_I2S_Q need to be defined * CLOCK_PLL_I2S_P and CLOCK_PLL_I2S_Q need to be defined, CLOCK_PLL_I2S_R is optional.
* - CLOCK_ENABLE_PLL_SAI: if a second PLL (PLL SAI) is available on the cpu, it * - CLOCK_ENABLE_PLL_SAI: if a second PLL (PLL SAI) is available on the cpu, it
* can be activated with this macro, then CLOCK_PLL_SAI_M, CLOCK_PLL_SAI_N, * can be activated with this macro, then CLOCK_PLL_SAI_M, CLOCK_PLL_SAI_N,
* CLOCK_PLL_SAI_P and CLOCK_PLL_SAI_Q need to be defined * CLOCK_PLL_SAI_P and CLOCK_PLL_SAI_Q need to be defined, CLOCK_PLL_SAI_R is optional.
* - CLOCK_USE_ALT_48MHZ: if the 48MHz clock should be generated by the alternate * - CLOCK_USE_ALT_48MHZ: if the 48MHz clock should be generated by the alternate
* source (PLL I2S or PLL SAI, depending on cpu) * source (PLL I2S or PLL SAI, depending on cpu)
* *