cpu/efm32: add flashpage_raw
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@ -2,6 +2,7 @@ include $(RIOTCPU)/efm32/efm32-features.mk
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_raw
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FEATURES_CONFLICT += periph_rtc:periph_rtt
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FEATURES_CONFLICT_MSG += "On the EFM32, the RTC and RTT map to the same hardware peripheral."
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@ -45,6 +45,12 @@ extern "C" {
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*/
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#define FLASHPAGE_SIZE (FLASH_PAGE_SIZE)
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#define FLASHPAGE_NUMOF (FLASH_SIZE / FLASH_PAGE_SIZE)
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/* The minimum block size which can be written is 4B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_RAW_BLOCKSIZE (4U)
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/* Writing should be always 4 bytes aligned */
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#define FLASHPAGE_RAW_ALIGNMENT (4U)
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/** @} */
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#ifdef __cplusplus
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@ -26,19 +26,41 @@
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#include "em_msc.h"
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void flashpage_write_raw(void *target_addr, const void *data, size_t len)
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{
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/* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
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that length. */
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assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
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/* ensure writes are aligned */
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assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
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((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
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/* ensure the length doesn't exceed the actual flash size */
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assert(((unsigned)target_addr + len) <
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(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
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uint32_t *page_addr = target_addr;
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const uint32_t *data_addr = data;
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MSC_Init();
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MSC_WriteWord(page_addr, data_addr, len);
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MSC_Deinit();
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}
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void flashpage_write(int page, const void *data)
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{
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assert(page < (int)FLASHPAGE_NUMOF);
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uint32_t *page_addr = (uint32_t *)flashpage_addr(page);
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const uint32_t *data_addr = data;
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/* erase given page */
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MSC_Init();
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MSC_ErasePage(page_addr);
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if (data != NULL) {
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MSC_WriteWord(page_addr, data_addr, FLASHPAGE_SIZE);
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}
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MSC_Deinit();
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/* write data to page */
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if (data != NULL) {
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flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
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}
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}
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