From e1766492669cd9ddd710a45f90070683f0892c21 Mon Sep 17 00:00:00 2001
From: Koen Zandberg <koen@bergzand.net>
Date: Mon, 9 Nov 2020 16:44:21 +0100
Subject: [PATCH] nrf5x: Adapt to flashpage/flashpage_pagewise API

---
 cpu/nrf51/include/cpu_conf.h        |  4 +-
 cpu/nrf52/include/cpu_conf.h        |  4 +-
 cpu/nrf5x_common/Kconfig            |  2 +-
 cpu/nrf5x_common/Makefile.features  |  2 +-
 cpu/nrf5x_common/periph/flashpage.c | 59 +++++++++++++----------------
 5 files changed, 33 insertions(+), 38 deletions(-)

diff --git a/cpu/nrf51/include/cpu_conf.h b/cpu/nrf51/include/cpu_conf.h
index 69d7db95fa..c5177ecf03 100644
--- a/cpu/nrf51/include/cpu_conf.h
+++ b/cpu/nrf51/include/cpu_conf.h
@@ -52,9 +52,9 @@ extern "C" {
 /* The minimum block size which can be written is 4B. However, the erase
  * block is always FLASHPAGE_SIZE.
  */
-#define FLASHPAGE_RAW_BLOCKSIZE    (4U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (4U)
 /* Writing should be always 4 bytes aligned */
-#define FLASHPAGE_RAW_ALIGNMENT    (4U)
+#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
 /** @} */
 
 /**
diff --git a/cpu/nrf52/include/cpu_conf.h b/cpu/nrf52/include/cpu_conf.h
index f06d952a93..990665b844 100644
--- a/cpu/nrf52/include/cpu_conf.h
+++ b/cpu/nrf52/include/cpu_conf.h
@@ -107,9 +107,9 @@ extern "C" {
 /* The minimum block size which can be written is 4B. However, the erase
  * block is always FLASHPAGE_SIZE.
  */
-#define FLASHPAGE_RAW_BLOCKSIZE    (4U)
+#define FLASHPAGE_WRITE_BLOCK_SIZE      (4U)
 /* Writing should be always 4 bytes aligned */
-#define FLASHPAGE_RAW_ALIGNMENT    (4U)
+#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U)
 /** @} */
 
 #ifdef CPU_MODEL_NRF52840XXAA
diff --git a/cpu/nrf5x_common/Kconfig b/cpu/nrf5x_common/Kconfig
index 3f9bd4728b..e77265eae6 100644
--- a/cpu/nrf5x_common/Kconfig
+++ b/cpu/nrf5x_common/Kconfig
@@ -8,7 +8,7 @@ config CPU_COMMON_NRF5X
     bool
     select HAS_PERIPH_CPUID
     select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_RAW
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
     select HAS_PERIPH_GPIO
     select HAS_PERIPH_GPIO_IRQ
     select HAS_PERIPH_HWRNG
diff --git a/cpu/nrf5x_common/Makefile.features b/cpu/nrf5x_common/Makefile.features
index 2933c0ee40..5bcd257807 100644
--- a/cpu/nrf5x_common/Makefile.features
+++ b/cpu/nrf5x_common/Makefile.features
@@ -1,7 +1,7 @@
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_flashpage
-FEATURES_PROVIDED += periph_flashpage_raw
+FEATURES_PROVIDED += periph_flashpage_pagewise
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
 FEATURES_PROVIDED += periph_hwrng
 FEATURES_PROVIDED += periph_temperature
diff --git a/cpu/nrf5x_common/periph/flashpage.c b/cpu/nrf5x_common/periph/flashpage.c
index d37ad7fcdb..1450380a55 100644
--- a/cpu/nrf5x_common/periph/flashpage.c
+++ b/cpu/nrf5x_common/periph/flashpage.c
@@ -23,33 +23,7 @@
 #include "assert.h"
 #include "periph/flashpage.h"
 
-void flashpage_write_raw(void *target_addr, const void *data, size_t len)
-{
-    /* assert multiples of FLASHPAGE_RAW_BLOCKSIZE are written and no less of
-       that length. */
-    assert(!(len % FLASHPAGE_RAW_BLOCKSIZE));
-
-    /* ensure writes are aligned */
-    assert(!(((unsigned)target_addr % FLASHPAGE_RAW_ALIGNMENT) ||
-            ((unsigned)data % FLASHPAGE_RAW_ALIGNMENT)));
-
-    /* ensure the length doesn't exceed the actual flash size */
-    assert(((unsigned)target_addr + len) <
-           (CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
-
-    uint32_t *page_addr = target_addr;
-    const uint32_t *data_addr = data;
-
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
-    for (unsigned i = 0; i < (len / FLASHPAGE_RAW_BLOCKSIZE); i++) {
-        *page_addr++ = data_addr[i];
-    }
-
-    /* finish up */
-    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
-}
-
-void flashpage_write(int page, const void *data)
+void flashpage_erase(unsigned page)
 {
     assert(page < (int)FLASHPAGE_NUMOF);
 
@@ -59,9 +33,30 @@ void flashpage_write(int page, const void *data)
     NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
     NRF_NVMC->ERASEPAGE = (uint32_t)page_addr;
     while (NRF_NVMC->READY == 0) {}
-
-    /* write data to page */
-    if (data != NULL) {
-        flashpage_write_raw(page_addr, data, FLASHPAGE_SIZE);
-    }
+}
+
+void flashpage_write(void *target_addr, const void *data, size_t len)
+{
+    /* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of
+       that length. */
+    assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
+
+    /* ensure writes are aligned */
+    assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) ||
+            ((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT)));
+
+    /* ensure the length doesn't exceed the actual flash size */
+    assert(((unsigned)target_addr + len) <
+           (CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1);
+
+    uint32_t *page_addr = target_addr;
+    const uint32_t *data_addr = data;
+
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
+    for (unsigned i = 0; i < (len / FLASHPAGE_WRITE_BLOCK_SIZE); i++) {
+        *page_addr++ = data_addr[i];
+    }
+
+    /* finish up */
+    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
 }