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cpu/stm32f2f4f7: expose clock settings in Kconfig

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This commit is contained in:
Alexandre Abadie 2020-09-05 11:11:19 +02:00
parent b35e4f4a95
commit e1941d8976
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GPG Key ID: 1C919A403CAE1405
3 changed files with 98 additions and 6 deletions
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66
cpu/stm32/kconfigs/Kconfig.clk
View File

@ -11,7 +11,7 @@ config CLOCK_HAS_NO_MCO_PRE
Indicates that the CPU has no MCO prescaler
menu "STM32 clock configuration"
depends on !CPU_FAM_F2 && !CPU_FAM_F4 && !CPU_FAM_F7
depends on CPU_STM32
choice
bool "Clock source selection"
@ -56,9 +56,10 @@ config CUSTOM_PLL_PARAMS
bool "Configure PLL parameters"
depends on USE_CLOCK_PLL
if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
config CLOCK_PLL_M
int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
default 4 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
default 1 if CPU_FAM_G0
default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
default 4 if CPU_FAM_G4
@ -70,15 +71,68 @@ config CLOCK_PLL_M
config CLOCK_PLL_N
int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
default 120 if BOARD_HAS_HSE && CPU_FAM_F2
default 60 if CPU_FAM_F2
default 168 if CPU_FAM_F4 && CLOCK_MAX_84MHZ && BOARD_HAS_HSE
default 84 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default 96 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 48 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 100 if CPU_FAM_F4 && CLOCK_MAX_100MHZ && BOARD_HAS_HSE
default 50 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
default 168 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 84 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 180 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && BOARD_HAS_HSE
default 90 if CPU_FAM_F4 && CLOCK_MAX_180MHZ
default 216 if CPU_FAM_F7 && BOARD_HAS_HSE
default 108 if CPU_FAM_F7
default 16 if CPU_FAM_WB
default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX
default 27 if CPU_FAM_L5
default 20 if CPU_FAM_G0 || CPU_FAM_L4
default 85 if CPU_FAM_G4
range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5
range 50 432 if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
range 8 127 if CPU_FAM_G4
range 6 127 if CPU_FAM_WB
if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
choice
bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default PLL_P_DIV_2
config PLL_P_DIV_2
bool "Divide by 2"
config PLL_P_DIV_4
bool "Divide by 4"
config PLL_P_DIV_6
bool "Divide by 6"
config PLL_P_DIV_8
bool "Divide by 8"
endchoice
config CLOCK_PLL_P
int
default 2 if PLL_P_DIV_2
default 4 if PLL_P_DIV_4
default 6 if PLL_P_DIV_6
default 8 if PLL_P_DIV_8
config CLOCK_PLL_Q
int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
default 5 if CPU_FAM_F2
default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV || USEMODULE_PERIPH_USBDEV)
default 9 if CPU_FAM_F7
default 8
range 2 15
endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7
if CPU_FAM_G0 || CPU_FAM_WB
config CLOCK_PLL_R
int "Q: VCO division factor" if CUSTOM_PLL_PARAMS
@ -115,7 +169,7 @@ config CLOCK_PLL_R
default 8 if PLL_R_DIV_8
endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3
config CLOCK_PLL_PREDIV
@ -313,8 +367,8 @@ endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
default CLOCK_APB1_DIV_4 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_F4
default CLOCK_APB1_DIV_1
config CLOCK_APB1_DIV_1
@ -345,7 +399,7 @@ config CLOCK_APB1_DIV
choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on !CPU_FAM_G0 && !CPU_FAM_F0
default CLOCK_APB2_DIV_2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
default CLOCK_APB2_DIV_1
config CLOCK_APB2_DIV_1

15
cpu/stm32/kconfigs/f4/Kconfig
View File

@ -21,3 +21,18 @@ config HAS_CPU_STM32F4
bool
help
Indicates that the cpu being used belongs to the 'stm32f4' family.
config CLOCK_MAX_84MHZ
bool
help
Indicates that the CPU max core clock frequency is 84MHz
config CLOCK_MAX_100MHZ
bool
help
Indicates that the CPU max core clock frequency is 100MHz
config CLOCK_MAX_180MHZ
bool
help
Indicates that the CPU max core clock frequency is 180MHz

23
cpu/stm32/kconfigs/f4/Kconfig.lines
View File

@ -13,99 +13,122 @@
config CPU_LINE_STM32F401XC
bool
select CPU_FAM_F4
select CLOCK_MAX_84MHZ
config CPU_LINE_STM32F401XE
bool
select CPU_FAM_F4
select CLOCK_MAX_84MHZ
config CPU_LINE_STM32F405XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F407XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F410CX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F410RX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F410TX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F411XE
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412CX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412RX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412VX
bool
select CPU_FAM_F4
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F412ZX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F413XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_100MHZ
config CPU_LINE_STM32F415XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F417XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F423XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F427XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F429XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F437XX
bool
select CPU_FAM_F4
select HAS_PERIPH_HWRNG
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F439XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F446XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F469XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ
config CPU_LINE_STM32F479XX
bool
select CPU_FAM_F4
select CLOCK_MAX_180MHZ