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cpu/stm32_common: set ULP and regulator LP during stop/standby

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francisco 2019-03-12 12:18:36 +01:00
parent 4dda8abecb
commit e254235265
1 changed files with 4 additions and 20 deletions
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22
cpu/stm32_common/periph/pm.c
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@ -58,13 +58,8 @@ void pm_set(unsigned mode)
PWR->CR |= (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF);
/* Enable WKUP pin to use for wakeup from standby mode */
#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
/* Regarding ULP, it's up to the user to configure it :
* 0: Internal Vref enabled during Deepsleep/Sleep/Low-power run mode
* 1: Disable internal voltage reference
* Deepsleep/Sleep/Low-power run mode
*/
/* Enable Ultra Low Power mode */
// PWR->CR |= PWR_CR_ULP;
PWR->CR |= PWR_CR_ULP;
PWR->CSR |= PWR_CSR_EWUP1;
#if !defined(CPU_LINE_STM32L053xx)
@ -82,23 +77,12 @@ void pm_set(unsigned mode)
/* Clear Wakeup flag */
PWR->CR |= PWR_CR_CWUF;
/* Clear PDDS to enter stop mode on */
/*
* Regarding LPSDSR, it's up to the user to configure it :
* 0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode
* 1: Voltage regulator in low-power mode during
* Deepsleep/Sleep/Low-power run mode
* Regarding ULP, it's up to the user to configure it :
* 0: Internal Vref enabled during Deepsleep/Sleep/Low-power run mode
* 1: Disable internal voltage reference
* Deepsleep/Sleep/Low-power run mode
*/
PWR->CR &= ~(PWR_CR_PDDS);
/* Regulator in LP mode */
// PWR->CR |= PWR_CR_LPSDSR;
PWR->CR |= PWR_CR_LPSDSR;
/* Enable Ultra Low Power mode*/
// PWR->CR |= PWR_CR_ULP;
PWR->CR |= PWR_CR_ULP;
#else
/* Clear PDDS and LPDS bits to enter stop mode on */
/* deepsleep with voltage regulator on */