cpu/{stm32r1,stm32_common}: Allow exposing JTAG pins as GPIOs

- cpu/stm32f1: Removed previous code in gpio_init() to provide PB4 on the
  Nucleo-F103RB only
- cpu/stm32_common: Introduced STM32F1_DISABLE_JTAG which, if defined in
  board.h, exposes the JTAG only pins as GPIOs. This keeps the SWD pins, so that
  SWD debugging remains possible

cpu/stm32_common/cpu_init.c

@@ -37,6 +37,7 @@
 #include "stmclk.h"
 #include "periph_cpu.h"
 #include "periph/init.h"
+#include "board.h"
 
 #if defined (CPU_FAM_STM32L4)
 #define BIT_APB_PWREN       RCC_APB1ENR1_PWREN
@@ -163,6 +164,12 @@ void cpu_init(void)
 #endif
     /* initialize stdio prior to periph_init() to allow use of DEBUG() there */
     stdio_init();
+
+#ifdef STM32F1_DISABLE_JTAG
+    RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
+    AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
+#endif
+
     /* trigger static peripheral initialization */
     periph_init();
 }

cpu/stm32f1/periph/gpio.c

@@ -88,16 +88,6 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
     /* enable the clock for the selected port */
     periph_clk_en(APB2, (RCC_APB2ENR_IOPAEN << _port_num(pin)));
 
-#ifdef BOARD_NUCLEO_F103RB
-    /* disable the default SWJ RST mode to allow using the pin as IO
-       this may also work on other f103 based boards but it was only tested on
-       nucleo-f103rb */
-    if ((pin_num == 4) && _port_num(pin)) {
-        RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
-        AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_NOJNTRST;
-    }
-#endif
-
     /* set pin mode */
     port->CR[pin_num >> 3] &= ~(0xf << ((pin_num & 0x7) * 4));
     port->CR[pin_num >> 3] |=  ((mode & MODE_MASK) << ((pin_num & 0x7) * 4));