cpu/nrf5x: implement periph_timer_periodic
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c337089de5
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e3e89fe513
@ -13,6 +13,7 @@ config CPU_COMMON_NRF5X
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select HAS_PERIPH_GPIO_IRQ
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select HAS_PERIPH_HWRNG
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select HAS_PERIPH_TEMPERATURE
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select HAS_PERIPH_TIMER_PERIODIC
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select HAS_PERIPH_UART_MODECFG
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select HAS_PERIPH_WDT
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select HAS_PERIPH_WDT_CB
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@ -5,6 +5,7 @@ FEATURES_PROVIDED += periph_flashpage_pagewise
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FEATURES_PROVIDED += periph_gpio periph_gpio_irq
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FEATURES_PROVIDED += periph_hwrng
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FEATURES_PROVIDED += periph_temperature
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FEATURES_PROVIDED += periph_timer_periodic
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FEATURES_PROVIDED += periph_uart_modecfg
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FEATURES_PROVIDED += periph_wdt periph_wdt_cb
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@ -31,6 +31,7 @@ typedef struct {
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timer_cb_t cb;
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void *arg;
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uint8_t flags;
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uint8_t is_periodic;
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} tim_ctx_t;
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/**
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@ -106,6 +107,29 @@ int timer_set_absolute(tim_t tim, int chan, unsigned int value)
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return 0;
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}
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int timer_set_periodic(tim_t tim, int chan, unsigned int value, uint8_t flags)
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{
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/* see if channel is valid */
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if (chan >= timer_config[tim].channels) {
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return -1;
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}
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ctx[tim].flags |= (1 << chan);
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ctx[tim].is_periodic |= (1 << chan);
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dev(tim)->CC[chan] = value;
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if (flags & TIM_FLAG_RESET_ON_MATCH) {
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dev(tim)->SHORTS |= (1 << chan);
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}
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if (flags & TIM_FLAG_RESET_ON_SET) {
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dev(tim)->TASKS_CLEAR = 1;
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}
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dev(tim)->INTENSET = (TIMER_INTENSET_COMPARE0_Msk << chan);
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dev(tim)->TASKS_START = 1;
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return 0;
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}
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int timer_clear(tim_t tim, int chan)
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{
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/* see if channel is valid */
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@ -114,7 +138,10 @@ int timer_clear(tim_t tim, int chan)
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}
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dev(tim)->INTENCLR = (TIMER_INTENSET_COMPARE0_Msk << chan);
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/* Clear out the Compare->Clear flag of this channel */
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dev(tim)->SHORTS &= ~(1 << chan);
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ctx[tim].flags &= ~(1 << chan);
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ctx[tim].is_periodic &= ~(1 << chan);
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return 0;
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}
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@ -141,8 +168,10 @@ static inline void irq_handler(int num)
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if (dev(num)->EVENTS_COMPARE[i] == 1) {
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dev(num)->EVENTS_COMPARE[i] = 0;
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if (ctx[num].flags & (1 << i)) {
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if ((ctx[num].is_periodic & (1 << i)) == 0) {
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ctx[num].flags &= ~(1 << i);
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dev(num)->INTENCLR = (TIMER_INTENSET_COMPARE0_Msk << i);
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}
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ctx[num].cb(ctx[num].arg, i);
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}
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}
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