From e51279b228db25b19e832f44938fcf24f56da0ee Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 13 Oct 2020 08:34:57 +0200 Subject: [PATCH] cpu/stm32l0: fix clk control register reset on stm32l011, RCC_CR_CSSON is not defined --- cpu/stm32/stmclk/stmclk_l0l1.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cpu/stm32/stmclk/stmclk_l0l1.c b/cpu/stm32/stmclk/stmclk_l0l1.c index 52f8b8d936..e6460a3423 100644 --- a/cpu/stm32/stmclk/stmclk_l0l1.c +++ b/cpu/stm32/stmclk/stmclk_l0l1.c @@ -180,7 +180,11 @@ void stmclk_init_sysclk(void) /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Reset MSION, HSEON, CSSON and PLLON bits */ +#ifdef RCC_CR_CSSON RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); +#else + RCC->CR &= ~(RCC_CR_MSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON); +#endif /* use HSI as system clock while we do any further configuration and * configure the AHB and APB clock dividers as configured by the board */