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Merge pull request #4170 from haukepetersen/opt_sam3_uart

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cpu/sam3: cleaned up UART driver
This commit is contained in:
Andreas "Paul" Pauli 2015-11-11 16:21:10 +01:00
commit e5b6566c9a
6 changed files with 106 additions and 298 deletions
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2
boards/arduino-due/include/board.h
View File

@ -36,7 +36,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio
* @{
*/
#define STDIO UART_0
#define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */

54
boards/arduino-due/include/periph_conf.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -21,6 +21,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -60,51 +62,21 @@ extern "C" {
* @name UART configuration
* @{
*/
#define UART_NUMOF (4U)
#define UART_0_EN 1
#define UART_1_EN 1
#define UART_2_EN 1
#define UART_3_EN 1
static const uart_conf_t uart_config[] = {
/* device, rx port, tx port, rx pin, tx pin, mux, PMC bit, IRGn line */
{(Uart *)UART, PIOA, PIOA, 8, 9, GPIO_MUX_A, ID_UART, UART_IRQn},
{(Uart *)USART0, PIOA, PIOA, 10, 11, GPIO_MUX_A, ID_USART0, USART0_IRQn},
{(Uart *)USART1, PIOA, PIOA, 12, 13, GPIO_MUX_A, ID_USART1, USART1_IRQn},
{(Uart *)USART3, PIOD, PIOD, 4, 5, GPIO_MUX_B, ID_USART3, USART3_IRQn}
};
/* UART 0 device configuration */
#define UART_0_DEV UART
#define UART_0_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_UART))
#define UART_0_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_UART))
#define UART_0_IRQ UART_IRQn
/* define interrupt vectors */
#define UART_0_ISR isr_uart
/* UART 0 pin configuration */
#define UART_0_PORT PIOA
#define UART_0_PINS (PIO_PA8 | PIO_PA9)
/* UART 1 device configuration */
#define UART_1_DEV USART0
#define UART_1_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART0))
#define UART_1_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART0))
#define UART_1_IRQ USART0_IRQn
#define UART_1_ISR isr_usart0
/* UART 1 pin configuration */
#define UART_1_PORT PIOA
#define UART_1_PINS (PIO_PA10 | PIO_PA11)
/* UART 1 device configuration */
#define UART_2_DEV USART1
#define UART_2_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART1))
#define UART_2_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART1))
#define UART_2_IRQ USART1_IRQn
#define UART_2_ISR isr_usart1
/* UART 1 pin configuration */
#define UART_2_PORT PIOA
#define UART_2_PINS (PIO_PA12 | PIO_PA13)
/* UART 1 device configuration */
#define UART_3_DEV USART3
#define UART_3_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART3))
#define UART_3_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART3))
#define UART_3_IRQ USART3_IRQn
#define UART_3_ISR isr_usart3
/* UART 1 pin configuration */
#define UART_3_PORT PIOD
#define UART_3_PINS (PIO_PD4 | PIO_PD5)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**

2
boards/udoo/include/board.h
View File

@ -37,7 +37,7 @@ extern "C" {
* @name Define UART device and baudrate for stdio
* @{
*/
#define STDIO UART_0
#define STDIO UART_DEV(0)
#define STDIO_BAUDRATE (115200U)
#define STDIO_RX_BUFSIZE (64U)
/** @} */

55
boards/udoo/include/periph_conf.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -19,6 +19,8 @@
#ifndef PERIPH_CONF_H_
#define PERIPH_CONF_H_
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -58,52 +60,21 @@ extern "C" {
* @name UART configuration
* @{
*/
#define UART_NUMOF (4U)
#define UART_0_EN 1
#define UART_1_EN 1
#define UART_2_EN 1
#define UART_3_EN 1
#define UART_IRQ_PRIO 1
static const uart_conf_t uart_config[] = {
/* device, rx port, tx port, rx pin, tx pin, mux, PMC bit, IRGn line */
{(Uart *)UART, PIOA, PIOA, 8, 9, GPIO_MUX_A, ID_UART, UART_IRQn},
{(Uart *)USART0, PIOA, PIOA, 10, 11, GPIO_MUX_A, ID_USART0, USART0_IRQn},
{(Uart *)USART1, PIOA, PIOA, 12, 13, GPIO_MUX_A, ID_USART1, USART1_IRQn},
{(Uart *)USART3, PIOD, PIOD, 4, 5, GPIO_MUX_B, ID_USART3, USART3_IRQn}
};
/* UART 0 device configuration */
#define UART_0_DEV UART
#define UART_0_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_UART))
#define UART_0_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_UART))
#define UART_0_IRQ UART_IRQn
/* define interrupt vectors */
#define UART_0_ISR isr_uart
/* UART 0 pin configuration */
#define UART_0_PORT PIOA
#define UART_0_PINS (PIO_PA8 | PIO_PA9)
/* UART 1 device configuration */
#define UART_1_DEV USART0
#define UART_1_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART0))
#define UART_1_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART0))
#define UART_1_IRQ USART0_IRQn
#define UART_1_ISR isr_usart0
/* UART 1 pin configuration */
#define UART_1_PORT PIOA
#define UART_1_PINS (PIO_PA10 | PIO_PA11)
/* UART 1 device configuration */
#define UART_2_DEV USART1
#define UART_2_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART1))
#define UART_2_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART1))
#define UART_2_IRQ USART1_IRQn
#define UART_2_ISR isr_usart1
/* UART 1 pin configuration */
#define UART_2_PORT PIOA
#define UART_2_PINS (PIO_PA12 | PIO_PA13)
/* UART 1 device configuration */
#define UART_3_DEV USART3
#define UART_3_CLKEN() (PMC->PMC_PCER0 |= (1 << ID_USART3))
#define UART_3_CLKDIS() (PMC->PMC_PCER0 &= ~(1 << ID_USART3))
#define UART_3_IRQ USART3_IRQn
#define UART_3_ISR isr_usart3
/* UART 1 pin configuration */
#define UART_3_PORT PIOD
#define UART_3_PINS (PIO_PD4 | PIO_PD5)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**

24
cpu/sam3/include/periph_cpu.h
View File

@ -19,7 +19,7 @@
#ifndef PERIPH_CPU_H_
#define PERIPH_CPU_H_
#include "periph/dev_enums.h"
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
@ -34,6 +34,28 @@ extern "C" {
#define PERIPH_SPI_NEEDS_TRANSFER_REGS
/** @} */
/**
* @brief GPIO mux configuration
*/
typedef enum {
GPIO_MUX_A = 0, /**< alternate function A */
GPIO_MUX_B = 1, /**< alternate function B */
} gpio_mux_t;
/**
* @brief UART configuration data
*/
typedef struct {
Uart *dev; /**< U(S)ART device used */
Pio *rx_port; /**< port for RX pin */
Pio *tx_port; /**< port for TX pin */
uint8_t rx_pin; /**< RX pin */
uint8_t tx_pin; /**< TX pin */
gpio_mux_t mux; /**< MUX used for pins */
uint8_t pmc_id; /**< bit in the PMC register of the device*/
uint8_t irqn; /**< interrupt number of the device */
} uart_conf_t;
#ifdef __cplusplus
}
#endif

267
cpu/sam3/periph/uart.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2014 Freie Universität Berlin
* Copyright (C) 2014-2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -7,7 +7,7 @@
*/
/**
* @ingroup driver_periph
* @ingroup cpu_sam3
* @{
*
* @file
@ -18,12 +18,11 @@
* @}
*/
#include "board.h"
#include "cpu.h"
#include "board.h"
#include "sched.h"
#include "thread.h"
#include "periph/uart.h"
#include "periph_conf.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@ -31,155 +30,53 @@
/**
* @brief Allocate memory to store the callback functions.
*/
static uart_isr_ctx_t uart_config[UART_NUMOF];
static int init_base(uart_t uart, uint32_t baudrate);
static uart_isr_ctx_t ctx[UART_NUMOF];
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
/* initialize basic functionality */
int res = init_base(uart, baudrate);
if (res != 0) {
return res;
Uart *dev;
/* make sure given device is valid */
if (uart >= UART_NUMOF) {
return -1;
}
/* register callbacks */
uart_config[uart].rx_cb = rx_cb;
uart_config[uart].arg = arg;
/* get base register */
dev = uart_config[uart].dev;
/* configure interrupts and enable RX interrupt */
switch (uart) {
#if UART_0_EN
case UART_0:
NVIC_EnableIRQ(UART_0_IRQ);
UART_0_DEV->UART_IER = UART_IER_RXRDY;
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_EnableIRQ(UART_1_IRQ);
UART_1_DEV->US_IER = US_IER_RXRDY;
break;
#endif
#if UART_2_EN
case UART_2:
NVIC_EnableIRQ(UART_2_IRQ);
UART_2_DEV->US_IER = US_IER_RXRDY;
break;
#endif
#if UART_3_EN
case UART_3:
NVIC_EnableIRQ(UART_3_IRQ);
UART_3_DEV->US_IER = US_IER_RXRDY;
break;
#endif
}
return 0;
}
/* register callback */
ctx[uart].rx_cb = rx_cb;
ctx[uart].arg = arg;
static int init_base(uart_t uart, uint32_t baudrate)
{
switch (uart) {
#if UART_0_EN
case UART_0:
/* enable uart clock */
UART_0_CLKEN();
/* enable clock */
uart_poweron(uart);
/* configure PINS */
UART_0_PORT->PIO_PDR = UART_0_PINS;
UART_0_PORT->PIO_ABSR &= ~UART_0_PINS; /* periph function A */
/* configure pins
TODO: optimize once GPIO refactoring is merged */
uart_config[uart].rx_port->PIO_PDR = (1 << uart_config[uart].rx_pin);
uart_config[uart].rx_port->PIO_ABSR &= ~(1 << uart_config[uart].rx_pin);
uart_config[uart].tx_port->PIO_ABSR |= (uart_config[uart].mux <<
uart_config[uart].rx_pin);
uart_config[uart].tx_port->PIO_PDR = (1 << uart_config[uart].tx_pin);
uart_config[uart].tx_port->PIO_ABSR &= ~(1 << uart_config[uart].tx_pin);
uart_config[uart].tx_port->PIO_ABSR |= (uart_config[uart].mux <<
uart_config[uart].tx_pin);
/* set clock divider */
UART_0_DEV->UART_BRGR = (F_CPU / (16 * baudrate));
/* set to normal mode without parity */
UART_0_DEV->UART_MR = UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL;
/* enable receiver and transmitter and reset status bits */
UART_0_DEV->UART_CR = UART_CR_RXEN | UART_CR_TXEN | UART_CR_RSTSTA;
break;
#endif
#if UART_1_EN
case UART_1:
/* enable uart clock */
UART_1_CLKEN();
/* configure baud rate and set mode to 8N1 */
dev->UART_BRGR = (F_CPU / (16 * baudrate));
dev->UART_MR = UART_MR_PAR_NO | US_MR_CHRL_8_BIT;
dev->UART_CR = UART_CR_RXEN | UART_CR_TXEN | UART_CR_RSTSTA;
/* configure PINS */
UART_1_PORT->PIO_PDR = UART_1_PINS;
UART_1_PORT->PIO_ABSR &= ~UART_1_PINS; /* periph function A */
/* enable RX interrupt */
NVIC_EnableIRQ(uart_config[uart].irqn);
dev->UART_IER = UART_IER_RXRDY;
/* set clock divider */
UART_1_DEV->US_BRGR = (F_CPU / (16 * baudrate));
/* set to normal mode without parity */
UART_1_DEV->US_MR = US_MR_CHRL_8_BIT | US_MR_PAR_NO;
/* enable receiver and transmitter and reset status bits */
UART_1_DEV->US_CR = US_CR_RXEN | US_CR_TXEN | US_CR_RSTSTA;
break;
#endif
#if UART_2_EN
case UART_2:
/* enable uart clock */
UART_2_CLKEN();
/* configure PINS */
UART_2_PORT->PIO_PDR = UART_2_PINS;
UART_2_PORT->PIO_ABSR &= ~UART_2_PINS; /* periph function A */
/* set clock divider */
UART_2_DEV->US_BRGR = (F_CPU / (16 * baudrate));
/* set to normal mode without parity */
UART_2_DEV->US_MR = US_MR_CHRL_8_BIT | US_MR_PAR_NO;
/* enable receiver and transmitter and reset status bits */
UART_2_DEV->US_CR = US_CR_RXEN | US_CR_TXEN | US_CR_RSTSTA;
break;
#endif
#if UART_3_EN
case UART_3:
/* enable uart clock */
UART_3_CLKEN();
/* configure PINS */
UART_3_PORT->PIO_PDR = UART_3_PINS;
UART_3_PORT->PIO_ABSR |= UART_3_PINS; /* periph function B */
/* set clock divider */
UART_3_DEV->US_BRGR = (F_CPU / (16 * baudrate));
/* set to normal mode without parity */
UART_3_DEV->US_MR = US_MR_CHRL_8_BIT | US_MR_PAR_NO;
/* enable receiver and transmitter and reset status bits */
UART_3_DEV->US_CR = US_CR_RXEN | US_CR_TXEN | US_CR_RSTSTA;
break;
#endif
}
return 0;
}
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
Uart *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = (Uart *)UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = (Uart *)UART_1_DEV;
break;
#endif
#if UART_2_EN
case UART_2:
dev = (Uart *)UART_2_DEV;
break;
#endif
#if UART_3_EN
case UART_3:
dev = (Uart *)UART_3_DEV;
break;
#endif
default:
return;
}
Uart *dev = uart_config[uart].dev;
for (size_t i = 0; i < len; i++) {
while (!(dev->UART_SR & UART_SR_TXRDY));
@ -189,104 +86,50 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
void uart_poweron(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_CLKEN();
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_CLKEN();
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_CLKEN();
break;
#endif
#if UART_3_EN
case UART_3:
UART_3_CLKEN();
break;
#endif
}
PMC->PMC_PCER0 |= (1 << uart_config[uart].pmc_id);
}
void uart_poweroff(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_CLKDIS();
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_CLKDIS();
break;
#endif
#if UART_2_EN
case UART_2:
UART_2_CLKDIS();
break;
#endif
#if UART_3_EN
case UART_3:
UART_3_CLKDIS();
break;
#endif
PMC->PMC_PCER0 &= ~(1 << uart_config[uart].pmc_id);
}
static inline void isr_handler(int num)
{
Uart *dev = uart_config[num].dev;
if (dev->UART_SR & UART_SR_RXRDY) {
ctx[num].rx_cb(ctx[num].arg, (char)dev->UART_RHR);
}
if (sched_context_switch_request) {
thread_yield();
}
}
#if UART_0_EN
#ifdef UART_0_ISR
void UART_0_ISR(void)
{
if (UART_0_DEV->UART_SR & UART_SR_RXRDY) {
char data = (char)UART_0_DEV->UART_RHR;
uart_config[UART_0].rx_cb(uart_config[UART_0].arg, data);
}
if (sched_context_switch_request) {
thread_yield();
}
isr_handler(0);
}
#endif
#if UART_1_EN
#ifdef UART_1_ISR
void UART_1_ISR(void)
{
if (UART_1_DEV->US_CSR & US_CSR_RXRDY) {
char data = (char)UART_1_DEV->US_RHR;
uart_config[UART_1].rx_cb(uart_config[UART_1].arg, data);
}
if (sched_context_switch_request) {
thread_yield();
}
isr_handler(1);
}
#endif
#if UART_2_EN
#ifdef UART_2_ISR
void UART_2_ISR(void)
{
if (UART_2_DEV->US_CSR & US_CSR_RXRDY) {
char data = (char)UART_2_DEV->US_RHR;
uart_config[UART_2].rx_cb(uart_config[UART_2].arg, data);
}
if (sched_context_switch_request) {
thread_yield();
}
isr_handler(2);
}
#endif
#if UART_3_EN
#ifdef UART_3_ISR
void UART_3_ISR(void)
{
if (UART_3_DEV->US_CSR & US_CSR_RXRDY) {
char data = (char)UART_3_DEV->US_RHR;
uart_config[UART_3].rx_cb(uart_config[UART_3].arg, data);
}
if (sched_context_switch_request) {
thread_yield();
}
isr_handler(3);
}
#endif