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Merge pull request #12558 from kaspar030/fix_typos

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fix typos
This commit is contained in:
Gunar Schorcht 2019-11-24 04:59:07 +01:00 committed by GitHub
commit eafa381a06
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407 changed files with 754 additions and 750 deletions
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2
boards/airfy-beacon/doc.txt
View File

@ -98,7 +98,7 @@ file](https://github.com/texane/stlink/blob/master/README) if you need help.
Second you need to enable the standalone ST-Link mode of the discovery board
by removing the two `CN2` jumpers, found somewhere in the upper left part of the
board. This disconnects the ST-Link programmer from the micro-controller part of
the port and enables direct access through the pin-header `CN3`, also labled
the port and enables direct access through the pin-header `CN3`, also labeled
`SWD`.
This module supports the Serial Wire Debug (SWD) interface. To access the

2
boards/arduino-leonardo/doc.txt
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@ -44,7 +44,7 @@ avrdude (the tool used to flash the firmware) to connect to the bootloader.
3. Hit enter
In case the compilation takes longer than the bootloader waits before starting
the user program, flashing will fail. See below to work arround
the user program, flashing will fail. See below to work around
### On a Slow Host

2
boards/blackpill-128kib/include/board.h
View File

@ -45,7 +45,7 @@ extern "C" {
}
#endif
/* Beware: This include must come *after* LED0 paramters have been defined */
/* Beware: This include must come *after* LED0 parameters have been defined */
#include "board_common.h"
#endif /* BOARD_H */

2
boards/blackpill/include/board.h
View File

@ -45,7 +45,7 @@ extern "C" {
}
#endif
/* Beware: This include must come *after* LED0 paramters have been defined */
/* Beware: This include must come *after* LED0 parameters have been defined */
#include "board_common.h"
#endif /* BOARD_H */

2
boards/cc2650stk/doc.txt
View File

@ -143,7 +143,7 @@ rfc_ble_param_advertiser_t
| Field | Size | RIOT variable | Description|
|:----------------------|:--------|:--------------|:------------------------------------------------------------|
| PDU Type | 4 bits | `ropCmd.commandNo` | PDU Type is solely dependant on the command type. See below. |
| PDU Type | 4 bits | `ropCmd.commandNo` | PDU Type is solely dependent on the command type. See below. |
| RFU | 2 bits | - | Reserved for Future Use (RFU): [You can't touch this.](https://www.youtube.com/watch?v=otCpCn0l4Wo) Assumed to be 0.|
| TxAdd | 1 bit | `pParams->advConfig.deviceAddrType` | The field value is specific to the PDU type. |
| RxAdd | 1 bit | - | The field value is specific to the PDU type. According to the TI documentation ([23.6.4.4](http://www.ti.com/lit/ug/swcu117d/swcu117d.pdf)), this field is not available to configure and thus assumed to be 0. |

2
boards/common/atmega/doc.txt
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@ -13,5 +13,5 @@ To enable only a specific bank, simply add `USEMODULE += atmega_pcintN` to your
Makefile. To enable all interrupts you can use `USEMODULE += atmega_pcint`.
In case you want to add a new CPU, simply provide an `atmega_pcint.h` with your
CPU and adapt your Makefile.dep and Makefile.featues files.
CPU and adapt your Makefile.dep and Makefile.features files.
*/

2
boards/common/atmega/include/periph_conf_atmega_common.h
View File

@ -91,7 +91,7 @@ extern "C" {
* ATmega2560
* ==========
* The timer driver only supports the four 16-bit timers (Timer1, Timer3,
* Timer4, Timer5), so those are the only onces we can use here.
* Timer4, Timer5), so those are the only ones we can use here.
*
*
* ATmega32U4

2
boards/common/esp32/include/board_common.h
View File

@ -108,7 +108,7 @@
/**
* @brief MTD drive start address in SPI flash memory
*
* Defines the start adress of the MTD system device in the SPI
* Defines the start address of the MTD system device in the SPI
* flash memory. It can be overridden by \ref esp32_app_spec_conf
* "application-specific board configuration"
*

8
boards/common/msb-430/board_init.c
View File

@ -135,7 +135,7 @@ void msp430_init_dco(void)
unsigned int oldcapture = 0;
unsigned int i;
BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
BCSCTL1 = 0xa4; /* ACLK is divided by 4. RSEL=6 no division for MCLK
and SSMCLK. XT2 is off. */
/* Init FLL to desired frequency using the 32762Hz crystal */
@ -151,15 +151,15 @@ void msp430_init_dco(void)
for (i = 0xffff; i > 0; i--); /* Delay for XTAL to settle */
CCTL2 = CCIS0 + CM0 + CAP; /* Define CCR2, CAP, ACLK */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continous mode */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continuous mode */
while (1) {
unsigned int compare;
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occurred! */
CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
CCTL2 &= ~CCIFG; /* Capture occurred, clear flag */
compare = CCR2; /* Get current captured SMCLK */
compare = compare - oldcapture; /* SMCLK difference */
oldcapture = CCR2; /* Save current captured SMCLK */

4
boards/common/msba2/tools/src/download.c
View File

@ -369,7 +369,7 @@ static void download_main(int event)
}
if (strcmp(parsed_response_buf, "OK\r\n") == 0) {
printf("Baud sync sucessful\r\n");
printf("Baud sync successful\r\n");
state = CHIP_ID;
event = BEGIN;
break;
@ -851,7 +851,7 @@ static void download_main(int event)
// would be nice if we could simply jump to the user's code, but
// Philips didn't think of that. The interrupt vector table stays
// mapped to the bootloader, so jumping to zero only runs the
// bootloader again. Intead, we need to download a tiny ARM
// bootloader again. Instead, we need to download a tiny ARM
// program that reconfigures the hardware and then jumps to zero.
//snprintf(buf, sizeof(buf), "G %d A\r\n", 0);
snprintf(buf, sizeof(buf), "W %u %u\r\n", chip->ram_addr, chip->bootprog[0] * 4);

2
boards/common/msba2/tools/src/ihex.c
View File

@ -113,7 +113,7 @@ int read_intel_hex(const char *filename)
/* parses a line of intel hex code, stores the data in bytes[] */
/* and the beginning address in addr, and returns a 1 if the */
/* line was valid, or a 0 if an error occured. The variable */
/* line was valid, or a 0 if an error occurred. The variable */
/* num gets the number of bytes that were stored into bytes[] */

2
boards/common/msba2/tools/src/serial.c
View File

@ -131,7 +131,7 @@ static void report_open_error(const char *filename, int err)
printf("You don't have permission to access %s\r\n", filename);
}
//printf("Attemping to find more information about %s....\r\n", filename);
//printf("Attempting to find more information about %s....\r\n", filename);
r = stat(filename, &info);
if (r < 0) {

2
boards/esp32-mh-et-live-minikit/doc.txt
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@ -39,7 +39,7 @@ MH-ET LIVE MiniKit for ESP32 belongs to the class of general purpose boards wher
\htmlonly<style>div.image img[src="https://gitlab.com/gschorcht/RIOT.wiki-Images/raw/master/esp32/MH-ET_LIVE_D1_mini_ESP32_2.png?inline=false"]{width:250px;}</style>\endhtmlonly
@image html "https://gitlab.com/gschorcht/RIOT.wiki-Images/raw/master/esp32/MH-ET_LIVE_D1_mini_ESP32_2.png?inline=false" "MH-ET LIVE MiniKit for ESP32"
This stackable plattform was tested in an RIOT application with:
This stackable platform was tested in an RIOT application with:
- [Micro SD-Card Shield](https://wiki.wemos.cc/products:d1_mini_shields:micro_sd_card_shield)
- MRF24J40 IEEE 802.15.4 radio Shield (contact gunar@schorcht.net for more information)

8
boards/esp32-mh-et-live-minikit/include/board_modules.h
View File

@ -46,16 +46,16 @@ extern "C" {
#define MRF24J40_PARAM_SPI SPI_DEV(0) /**< SPI_DEV(0) is used (fixed) */
#ifndef MRF24J40_PARAM_SPI_CLK
#define MRF24J40_PARAM_SPI_CLK SPI_CLK_1MHZ /**< SPI bus speed used (can be overriden) */
#define MRF24J40_PARAM_SPI_CLK SPI_CLK_1MHZ /**< SPI bus speed used (can be overridden) */
#endif
#ifndef MRF24J40_PARAM_CS
#define MRF24J40_PARAM_CS GPIO26 /**< MRF24J40 CS signal (can be overriden) */
#define MRF24J40_PARAM_CS GPIO26 /**< MRF24J40 CS signal (can be overridden) */
#endif
#ifndef MRF24J40_PARAM_INT
#define MRF24J40_PARAM_INT GPIO17 /**< MRF24J40 INT signal (can be overriden) */
#define MRF24J40_PARAM_INT GPIO17 /**< MRF24J40 INT signal (can be overridden) */
#endif
#ifndef MRF24J40_PARAM_RESET
#define MRF24J40_PARAM_RESET GPIO16 /**< MRF24J40 RESET signal (can be overriden) */
#define MRF24J40_PARAM_RESET GPIO16 /**< MRF24J40 RESET signal (can be overridden) */
#endif
/** @} */
#endif /* MODULE_MRF24J40 || DOXYGEN */

2
boards/esp32-mh-et-live-minikit/include/periph_conf.h
View File

@ -140,7 +140,7 @@
/**
* @name UART configuration
*
* ESP32 provides 3 UART interaces at maximum:
* ESP32 provides 3 UART interfaces at maximum:
*
* UART_DEV(0) uses fixed standard configuration.<br>
* UART_DEV(1) is defined here.<br>

8
boards/esp32-olimex-evb/include/periph_conf.h
View File

@ -73,11 +73,11 @@ extern "C" {
/**
* @name CAN configuration
*
* Olimex ESP32-EVB has a CAN interface including a CAN tranceiver on board.
* Olimex ESP32-EVB has a CAN interface including a CAN transceiver on board.
*/
#ifndef MODULE_OLIMEX_ESP32_GATEWAY
#define CAN_TX GPIO5 /**< CAN TX tranceiver signal */
#define CAN_RX GPIO35 /**< CAN RX tranceiver signal */
#define CAN_TX GPIO5 /**< CAN TX transceiver signal */
#define CAN_RX GPIO35 /**< CAN RX transceiver signal */
#endif
/**
@ -192,7 +192,7 @@ extern "C" {
/**
* @name UART configuration
*
* ESP32 provides 3 UART interaces at maximum:
* ESP32 provides 3 UART interfaces at maximum:
*
* UART_DEV(0) uses fixed standard configuration.<br>
* UART_DEV(1) is defined here.<br>

2
boards/esp32-wemos-lolin-d32-pro/include/board.h
View File

@ -60,7 +60,7 @@
* @name SD card interface configuration
*
* SD card interface uses SPI_DEV(0) on this board. This configuration cannot
* be overriden.
* be overridden.
* @{
*/
#if MODULE_SDCARD_SPI

2
boards/esp32-wemos-lolin-d32-pro/include/periph_conf.h
View File

@ -170,7 +170,7 @@
/**
* @name UART configuration
*
* ESP32 provides 3 UART interaces at maximum:
* ESP32 provides 3 UART interfaces at maximum:
*
* UART_DEV(0) uses fixed standard configuration.<br>
* UART_DEV(1) is not used.<br>

2
boards/esp32-wroom-32/include/periph_conf.h
View File

@ -171,7 +171,7 @@ extern "C" {
/**
* @name UART configuration
*
* ESP32 provides 3 UART interaces at maximum:
* ESP32 provides 3 UART interfaces at maximum:
*
* UART_DEV(0) uses fixed standard configuration.<br>
* UART_DEV(1) is defined here.<br>

2
boards/esp32-wrover-kit/doc.txt
View File

@ -257,7 +257,7 @@ For detailed information about ESP32 as well as configuring and compiling RIOT f
## <a name="debugging"> On-Chip Debugging with the Device </a> &nbsp;&nbsp; [[TOC](#toc)]
Since the USB bridge based on FDI FT2232HL provides a JTAG interface for debugging through an USB interface, using ESP-ROVER-KIT is the easiest and most convinient way for On-Chip debugging. Please refer the [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/jtag-debugging/index.html) for details on how to setup and how to use ESP-WROVER-KIT and OpenOCD.
Since the USB bridge based on FDI FT2232HL provides a JTAG interface for debugging through an USB interface, using ESP-ROVER-KIT is the easiest and most convenient way for On-Chip debugging. Please refer the [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/jtag-debugging/index.html) for details on how to setup and how to use ESP-WROVER-KIT and OpenOCD.
## <a name="other-resources"> Other Documentation Resources </a> &nbsp;&nbsp; [[TOC](#toc)]

2
boards/esp32-wrover-kit/include/periph_conf.h
View File

@ -196,7 +196,7 @@
/**
* @name UART configuration
*
* ESP32 provides 3 UART interaces at maximum:
* ESP32 provides 3 UART interfaces at maximum:
*
* UART_DEV(0) uses fixed standard configuration.<br>
* UART_DEV(1) is not available.<br>

2
boards/fox/doc.txt
View File

@ -121,7 +121,7 @@ In some cases it
seems necessary to prepend a `monitor reset run` before executing continue.
In general you can
use openocd commands prepended by `monitor`.
In the case the node crashes it can be reseted with the following sequence
In the case the node crashes it can be reset with the following sequence
```
Bash
(gdb) monitor reset halt

2
boards/frdm-k64f/doc.txt
View File

@ -31,7 +31,7 @@ M-K64F_BDTN.jpg)
| Vcc | TODO |
| Reference Manual | TODO |
The board has an integrated debuger adapter (k20dx128) with the firmware from
The board has an integrated debugger adapter (k20dx128) with the firmware from
ARMmbed.
There are three interfaces available:
* Drag-n-drop programming over Mass Storage Device

4
boards/iotlab-m3/doc.txt
View File

@ -67,7 +67,7 @@ eabi-gdb`), which provided by most toolchains. Most Linux distributions provide
also a package for OpenOCD. The required configuration files are provided by
RIOT.
When starting the debugger with `make debug BOARD=iotlab-m3` GDB connects to
openocd, loads the elf-file and puts the MCU into halt state. Befor setting
openocd, loads the elf-file and puts the MCU into halt state. Before setting
breakpoints it is sometimes needed to use the following workflow
```
bash
@ -148,7 +148,7 @@ In some cases it
seems necessary to prepend a `monitor reset run` before executing continue.
In general you can
use openocd commands prepended by `monitor`.
In the case the node crashes it can be reseted with the following sequence
In the case the node crashes it can be reset with the following sequence
```
Bash
(gdb) monitor reset halt

2
boards/lsn50/doc.txt
View File

@ -41,7 +41,7 @@ application.
### STDIO
STDIO is connected to pins PA9 (TX) and PA10 (RX) so an USB to UART adapter is
required. Use the `term` targed to open a terminal:
required. Use the `term` target to open a terminal:
make BOARD=lsn50 -C examples/hello-world term

2
boards/mbed_lpc1768/dist/flash.sh vendored
View File

@ -68,5 +68,5 @@ then
fi
echo ""
echo "UPLOAD SUCCESFUL"
echo "UPLOAD SUCCESSFUL"
echo ""

2
boards/microbit/doc.txt
View File

@ -48,7 +48,7 @@ or you can flash the board using Segger's JLink.
The [DAPLink interface](https://www.mbed.com/en/development/hardware/prototyping-production/daplink/daplink-on-kl26z/) is the default way to flash the board and
works out of the box. When you plug the board to your host computer, it shows up
as a flash drive. To flash the board, you can simply copy your compiled `.hex`
file onto the board, and thats it.
file onto the board, and that's it.
The `micro:bit` port comes with a little script that does this automatically,
so you can flash the board as usual with

2
boards/msba2/doc.txt
View File

@ -70,7 +70,7 @@ The following wires need to be soldered on:
As debugger an FT2232HL is used, the cheapest version costs less 10€ (often
nicknamed CJMCU-2232HL).
Connect as fallows:
Connect as follows:
| FT2232HL | MSB-A2 |
|:----------|:----------|

2
boards/nucleo-l4r5zi/doc.txt
View File

@ -26,7 +26,7 @@ make BOARD=nucleo-l4r5zi flash -C examples/hello-world
STDIO is available via the ST-Link programmer.
Use the `term` targed to open a terminal:
Use the `term` target to open a terminal:
make BOARD=nucleo-l4r5zi -C examples/hello-world term

2
boards/p-l496g-cell02/doc.txt
View File

@ -24,7 +24,7 @@ make BOARD=p-l496g-cell02 flash -C examples/hello-world
STDIO is available via the ST-Link programmer.
Use the `term` targed to open a terminal:
Use the `term` target to open a terminal:
make BOARD=p-l496g-cell02 -C examples/hello-world term

2
boards/remote-pa/board.c
View File

@ -46,7 +46,7 @@ void board_init(void)
/**
* @brief Initialize the 2.4GHz Radio Frequency SW-controlled Switch
*
* The Re-Mote features an on-board RF switch to programatically select to
* The Re-Mote features an on-board RF switch to programmatically select to
* enable either the internal ceramic antenna, or an external antenna over an
* uFL connector. As default we prefer to use the internal one.
*

2
boards/remote-reva/README.md
View File

@ -28,7 +28,7 @@ In terms of hardware support, the following drivers have been implemented:
* LEDs
* Buttons
* ADC
* RF switch to programatically drive either 2.4GHz or sub-1GHz to a single RP-SMA
* RF switch to programmatically drive either 2.4GHz or sub-1GHz to a single RP-SMA
* RF 2.4GHz built-in in CC2538
And under work or pending at cc2538 base cpu:

2
boards/remote-reva/board.c
View File

@ -56,7 +56,7 @@ static inline void leds_init(void)
/**
* @brief Initialize the Radio interface SW-controlled Switch
*
* The RE-Mote features an on-board RF switch to programatically select to
* The RE-Mote features an on-board RF switch to programmatically select to
* enable either the 2.4GHz or Sub-1GHz RF interface to the RP-SMA connector
* to use an external antenna. As default we prefer to use the 2.4GHz RF.
*

2
boards/remote-reva/doc.txt
View File

@ -35,7 +35,7 @@ In terms of hardware support, the following drivers have been implemented:
* LEDs
* Buttons
* RF 2.4GHz built-in in CC2538
* RF switch to programatically drive either 2.4GHz or sub-1GHz to a single
* RF switch to programmatically drive either 2.4GHz or sub-1GHz to a single
RP-SMA
And under work or pending at cc2538 base cpu:

2
boards/remote-revb/README.md
View File

@ -33,7 +33,7 @@ In terms of hardware support, the following drivers have been implemented:
* I2C/SPI library
* LEDs
* Buttons
* RF switch to programatically drive either 2.4GHz or sub-1GHz to a single RP-SMA
* RF switch to programmatically drive either 2.4GHz or sub-1GHz to a single RP-SMA
* RF 2.4GHz built-in in CC2538
And under work or pending at cc2538 base cpu:

2
boards/remote-revb/board.c
View File

@ -56,7 +56,7 @@ static inline void leds_init(void)
/**
* @brief Initialize the Radio interface SW-controlled Switch
*
* The RE-Mote features an on-board RF switch to programatically select to
* The RE-Mote features an on-board RF switch to programmatically select to
* enable either the 2.4GHz or Sub-1GHz RF interface to the RP-SMA connector
* to use an external antenna. As default we prefer to use the 2.4GHz RF.
*

2
boards/saml21-xpro/doc.txt
View File

@ -79,7 +79,7 @@ Please note that even the latest official OpenOCD (v0.9 at the time of this
writing) does not support B-variant SAML21 devices.
If you attempt to flash a board, and OpenOCD throws a `Couldn't find part
correspoding to DID XXXXXXXX` error, you will need to compile your own OpenOCD
corresponding to DID XXXXXXXX` error, you will need to compile your own OpenOCD
from source.
Refer to https://github.com/RIOT-OS/RIOT/wiki/OpenOCD for general

4
boards/sensebox_samd21/doc.txt
View File

@ -45,13 +45,13 @@ connected to the ports is reset before use.
#### SX127X radio
The pin configuration for the SX127X radio on the
*boards/sensebox_samd21/include/board.h** file assumes that it will be connected to
the XBEE1 port. If a different configuraion is needed please modify this
the XBEE1 port. If a different configuration is needed please modify this
file.
#### SD card
The pin configuration for the mSD-Bee module radio on the
*boards/sensebox_samd21/include/sdcard_spi_params.h** file assumes that it will be
connected to the XBEE2 port. If a different configuraion is needed please
connected to the XBEE2 port. If a different configuration is needed please
modify this file.
#### Limitations

2
boards/stm32f723e-disco/doc.txt
View File

@ -24,7 +24,7 @@ make BOARD=stm32f723e-disco flash -C examples/hello-world
STDIO is available via the ST-Link programmer.
Use the `term` targed to open a terminal:
Use the `term` target to open a terminal:
make BOARD=stm32f723e-disco -C examples/hello-world term

2
boards/stm32l0538-disco/doc.txt
View File

@ -31,7 +31,7 @@ Then use the following command:
### STDIO
STDIO is connected to pins PA9 (TX) and PA10 (RX) so an USB to UART adapter is
required. Use the `term` targed to open a terminal:
required. Use the `term` target to open a terminal:
make BOARD=stm32l0538-disco -C examples/hello-world term

6
boards/telosb/board.c
View File

@ -71,14 +71,14 @@ void msp430_init_dco(void)
}
CCTL2 = CCIS0 + CM0 + CAP; /* Define CCR2, CAP, ACLK */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continous mode */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continuous mode */
while (1) {
unsigned int compare;
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured!*/
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occurred!*/
CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
CCTL2 &= ~CCIFG; /* Capture occurred, clear flag */
compare = CCR2; /* Get current captured SMCLK */
compare = compare - oldcapture; /* SMCLK difference */
oldcapture = CCR2; /* Save current captured SMCLK */

2
boards/telosb/include/board.h
View File

@ -10,7 +10,7 @@
/**
* @ingroup boards_telosb
*
* <h2>Compontents</h2>
* <h2>Components</h2>
* \li MSP430
* \li CC2420
*

2
boards/thingy52/doc.txt
View File

@ -12,7 +12,7 @@ Components:
- nRF52832 main controller (providing Bluetooth and NFC)
- an LIS2DH12 low-power three-axis linear accelerometer
- an MPU-9250 nine-axis motion sensor
- an LPS22HB air pressure and temperatur sensor
- an LPS22HB air pressure and temperature sensor
- an HTS221 air temperature and humidity sensor
- a BH1745NUC color sensor
- a CCS811 gas sensor

2
boards/yunjia-nrf51822/doc.txt
View File

@ -67,7 +67,7 @@ Second you need to enable the stand-alone ST-Link mode of the discovery board
by removing the two `CN2` jumpers, found somewhere in the upper right part of
the board. This disconnects the ST-Link programmer from the micro-controller
part of the port and enables direct access through the pin-header `CN3`, also
labled `SWD`.
labeled `SWD`.
The Yunjia NRF51822 module supports the Serial Wire Debug (SWD) interface. To
access the device the following four lines need to be connected with the

6
boards/z1/board.c
View File

@ -142,14 +142,14 @@ void msp430_init_dco(void)
}
CCTL2 = CCIS0 + CM0 + CAP; /* Define CCR2, CAP, ACLK */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continous mode */
TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continuous mode */
while (1) {
unsigned int compare;
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured!*/
while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occurred!*/
CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
CCTL2 &= ~CCIFG; /* Capture occurred, clear flag */
compare = CCR2; /* Get current captured SMCLK */
compare = compare - oldcapture; /* SMCLK difference */
oldcapture = CCR2; /* Save current captured SMCLK */

2
core/include/byteorder.h
View File

@ -367,7 +367,7 @@ static inline le_uint64_t byteorder_btolll(be_uint64_t v)
}
/**
* @brief Swaps the byteorder according to the endianess
* @brief Swaps the byteorder according to the endianness
*/
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
# define _byteorder_swap(V, T) (byteorder_swap##T((V)))

2
core/include/kernel_init.h
View File

@ -12,7 +12,7 @@
* @{
*
* @file
* @brief prototypes for kernel intitialization
* @brief prototypes for kernel initialization
*
* @author Oliver Hahm <oliver.hahm@inria.fr>
* @author Kaspar Schleiser <kaspar@schleiser.de>

2
core/include/sched.h
View File

@ -149,7 +149,7 @@ int sched_run(void);
void sched_set_status(thread_t *process, thread_status_t status);
/**
* @brief Yield if approriate.
* @brief Yield if appropriate.
*
* @details Either yield if other_prio is higher than the current priority,
* or if the current thread is not on the runqueue.

4
core/include/thread.h
View File

@ -348,10 +348,10 @@ kernel_pid_t thread_create(char *stack,
const char *name);
/**
* @brief Retreive a thread control block by PID.
* @brief Retrieve a thread control block by PID.
* @details This is a bound-checked variant of accessing `sched_threads[pid]` directly.
* If you know that the PID is valid, then don't use this function.
* @param[in] pid Thread to retreive.
* @param[in] pid Thread to retrieve.
* @return `NULL` if the PID is invalid or there is no such thread.
*/
volatile thread_t *thread_get(kernel_pid_t pid);

2
core/kernel_init.c
View File

@ -12,7 +12,7 @@
* @{
*
* @file
* @brief Platform-independent kernel initilization
* @brief Platform-independent kernel initialization
*
* @author Kaspar Schleiser <kaspar@schleiser.de>
*

6
core/rmutex.c
View File

@ -51,7 +51,7 @@ static int _lock(rmutex_t *rmutex, int trylock)
* mutex_lock(). However the read access to owner is not
* locked, and owner can be changed by a thread that is
* holding the lock (e.g.: holder unlocks the mutex, new
* holder aquired the lock). The atomic access strategy
* holder acquired the lock). The atomic access strategy
* 'relaxed' ensures, that the value of rmutex->owner is read
* consistent.
*
@ -72,7 +72,7 @@ static int _lock(rmutex_t *rmutex, int trylock)
* Note for Case 2:
*
* Because the mutex rmutex->owner is only written be the
* owner (me), rmutex->owner stays constant througout the
* owner (me), rmutex->owner stays constant throughout the
* complete call and rmutex->refcount is protected
* (read/write) by the mutex.
*/
@ -100,7 +100,7 @@ static int _lock(rmutex_t *rmutex, int trylock)
DEBUG("rmutex %" PRIi16" : I am now holding the mutex\n", thread_getpid());
/* I am holding the recursive mutex */
DEBUG("rmutex %" PRIi16" : settting the owner\n", thread_getpid());
DEBUG("rmutex %" PRIi16" : setting the owner\n", thread_getpid());
/* ensure that owner is written atomically, since others need a consistent value */
atomic_store_explicit(&rmutex->owner, thread_getpid(), memory_order_relaxed);

2
cpu/atmega1281/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega1284p/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega128rfa1/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega2560/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega256rfr2/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega328p/ldscripts_compat/README.md
View File

@ -2,7 +2,7 @@ avr linkerscript
================
Starting from avr-binutils 2.26, the linker defines symbol that can be
overriden to configure ROM and RAM length.
overridden to configure ROM and RAM length.
This ldscript is used for supporting older versions on avr-binutils like on
ubuntu xenial.

2
cpu/atmega_common/cpu.c
View File

@ -39,7 +39,7 @@
/*
* Since atmega MCUs do not feature a software reset, the watchdog timer
* is being used. It will be set to the shortest time and then force a
* reset. Therefore the MCUSR register needs to be resetted as fast as
* reset. Therefore the MCUSR register needs to be reset as fast as
* possible.
* Which means in the bootloader or in the following init0 if no bootloader is used.
* Bootloader resets watchdog and pass MCUSR in r2 (e.g. Optiboot) in order to pass

2
cpu/atmega_common/periph/i2c.c
View File

@ -12,7 +12,7 @@
* @{
*
* @file
* @brief Low-level I2C driver implementation fot atmega common
* @brief Low-level I2C driver implementation for atmega common
*
* @note This implementation only implements the 7-bit addressing mode.
*

4
cpu/atmega_common/thread_arch.c
View File

@ -66,7 +66,7 @@ static void __enter_thread_mode(void);
*
* After the invocation of __context_restore() the pointer to task_func is
* on top of the stack and can be returned to. This way we can actually place
* it inside of the programm counter of the MCU.
* it inside of the program counter of the MCU.
* if task_func returns sched_task_exit gets popped into the PC
*/
char *thread_stack_init(thread_task_func_t task_func, void *arg,
@ -172,7 +172,7 @@ char *thread_stack_init(thread_task_func_t task_func, void *arg,
* @brief thread_stack_print prints the stack to stdout.
* It depends on getting the correct values for stack_start, stack_size and sp
* from sched_active_thread.
* Maybe it would be good to change that to way that is less dependant on
* Maybe it would be good to change that to way that is less dependent on
* getting correct values elsewhere (since it is a debugging tool and in the
* presence of bugs the data may be corrupted).
*/

64
cpu/cc2538/include/cc2538.h
View File

@ -609,38 +609,38 @@ typedef volatile uint32_t cc2538_reg_t; /**< Least-significant 32 bits of the IE
#define IOC_PD5_SEL ( *(cc2538_reg_t*)0x400d4074 ) /**< Peripheral select control for PD5 */
#define IOC_PD6_SEL ( *(cc2538_reg_t*)0x400d4078 ) /**< Peripheral select control for PD6 */
#define IOC_PD7_SEL ( *(cc2538_reg_t*)0x400d407c ) /**< Peripheral select control for PD7 */
#define IOC_PA0_OVER ( *(cc2538_reg_t*)0x400d4080 ) /**< Overide configuration register for PA0. */
#define IOC_PA1_OVER ( *(cc2538_reg_t*)0x400d4084 ) /**< Overide configuration register for PA1. */
#define IOC_PA2_OVER ( *(cc2538_reg_t*)0x400d4088 ) /**< Overide configuration register for PA2. */
#define IOC_PA3_OVER ( *(cc2538_reg_t*)0x400d408c ) /**< Overide configuration register for PA3. */
#define IOC_PA4_OVER ( *(cc2538_reg_t*)0x400d4090 ) /**< Overide configuration register for PA4. */
#define IOC_PA5_OVER ( *(cc2538_reg_t*)0x400d4094 ) /**< Overide configuration register for PA5. */
#define IOC_PA6_OVER ( *(cc2538_reg_t*)0x400d4098 ) /**< Overide configuration register for PA6. */
#define IOC_PA7_OVER ( *(cc2538_reg_t*)0x400d409c ) /**< Overide configuration register for PA7. */
#define IOC_PB0_OVER ( *(cc2538_reg_t*)0x400d40a0 ) /**< Overide configuration register for PB0. */
#define IOC_PB1_OVER ( *(cc2538_reg_t*)0x400d40a4 ) /**< Overide configuration register for PB1. */
#define IOC_PB2_OVER ( *(cc2538_reg_t*)0x400d40a8 ) /**< Overide configuration register for PB2. */
#define IOC_PB3_OVER ( *(cc2538_reg_t*)0x400d40ac ) /**< Overide configuration register for PB3. */
#define IOC_PB4_OVER ( *(cc2538_reg_t*)0x400d40b0 ) /**< Overide configuration register for PB4. */
#define IOC_PB5_OVER ( *(cc2538_reg_t*)0x400d40b4 ) /**< Overide configuration register for PB5. */
#define IOC_PB6_OVER ( *(cc2538_reg_t*)0x400d40b8 ) /**< Overide configuration register for PB6. */
#define IOC_PB7_OVER ( *(cc2538_reg_t*)0x400d40bc ) /**< Overide configuration register for PB7. */
#define IOC_PC0_OVER ( *(cc2538_reg_t*)0x400d40c0 ) /**< Overide configuration register for PC0. PC0 has high drive capability. */
#define IOC_PC1_OVER ( *(cc2538_reg_t*)0x400d40c4 ) /**< Overide configuration register for PC1. PC1 has high drive capability. */
#define IOC_PC2_OVER ( *(cc2538_reg_t*)0x400d40c8 ) /**< Overide configuration register for PC2. PC2 has high drive capability. */
#define IOC_PC3_OVER ( *(cc2538_reg_t*)0x400d40cc ) /**< Overide configuration register for PC3. PC3 has high drive capability. */
#define IOC_PC4_OVER ( *(cc2538_reg_t*)0x400d40d0 ) /**< Overide configuration register for PC4. */
#define IOC_PC5_OVER ( *(cc2538_reg_t*)0x400d40d4 ) /**< Overide configuration register for PC5. */
#define IOC_PC6_OVER ( *(cc2538_reg_t*)0x400d40d8 ) /**< Overide configuration register for PC6. */
#define IOC_PC7_OVER ( *(cc2538_reg_t*)0x400d40dc ) /**< Overide configuration register for PC7. */
#define IOC_PD0_OVER ( *(cc2538_reg_t*)0x400d40e0 ) /**< Overide configuration register for PD0. */
#define IOC_PD1_OVER ( *(cc2538_reg_t*)0x400d40e4 ) /**< Overide configuration register for PD1. */
#define IOC_PD2_OVER ( *(cc2538_reg_t*)0x400d40e8 ) /**< Overide configuration register for PD2. */
#define IOC_PD3_OVER ( *(cc2538_reg_t*)0x400d40ec ) /**< Overide configuration register for PD3. */
#define IOC_PD4_OVER ( *(cc2538_reg_t*)0x400d40f0 ) /**< Overide configuration register for PD4. */
#define IOC_PD5_OVER ( *(cc2538_reg_t*)0x400d40f4 ) /**< Overide configuration register for PD5. */
#define IOC_PD6_OVER ( *(cc2538_reg_t*)0x400d40f8 ) /**< Overide configuration register for PD6. */
#define IOC_PD7_OVER ( *(cc2538_reg_t*)0x400d40fc ) /**< Overide configuration register for PD7. */
#define IOC_PA0_OVER ( *(cc2538_reg_t*)0x400d4080 ) /**< Override configuration register for PA0. */
#define IOC_PA1_OVER ( *(cc2538_reg_t*)0x400d4084 ) /**< Override configuration register for PA1. */
#define IOC_PA2_OVER ( *(cc2538_reg_t*)0x400d4088 ) /**< Override configuration register for PA2. */
#define IOC_PA3_OVER ( *(cc2538_reg_t*)0x400d408c ) /**< Override configuration register for PA3. */
#define IOC_PA4_OVER ( *(cc2538_reg_t*)0x400d4090 ) /**< Override configuration register for PA4. */
#define IOC_PA5_OVER ( *(cc2538_reg_t*)0x400d4094 ) /**< Override configuration register for PA5. */
#define IOC_PA6_OVER ( *(cc2538_reg_t*)0x400d4098 ) /**< Override configuration register for PA6. */
#define IOC_PA7_OVER ( *(cc2538_reg_t*)0x400d409c ) /**< Override configuration register for PA7. */
#define IOC_PB0_OVER ( *(cc2538_reg_t*)0x400d40a0 ) /**< Override configuration register for PB0. */
#define IOC_PB1_OVER ( *(cc2538_reg_t*)0x400d40a4 ) /**< Override configuration register for PB1. */
#define IOC_PB2_OVER ( *(cc2538_reg_t*)0x400d40a8 ) /**< Override configuration register for PB2. */
#define IOC_PB3_OVER ( *(cc2538_reg_t*)0x400d40ac ) /**< Override configuration register for PB3. */
#define IOC_PB4_OVER ( *(cc2538_reg_t*)0x400d40b0 ) /**< Override configuration register for PB4. */
#define IOC_PB5_OVER ( *(cc2538_reg_t*)0x400d40b4 ) /**< Override configuration register for PB5. */
#define IOC_PB6_OVER ( *(cc2538_reg_t*)0x400d40b8 ) /**< Override configuration register for PB6. */
#define IOC_PB7_OVER ( *(cc2538_reg_t*)0x400d40bc ) /**< Override configuration register for PB7. */
#define IOC_PC0_OVER ( *(cc2538_reg_t*)0x400d40c0 ) /**< Override configuration register for PC0. PC0 has high drive capability. */
#define IOC_PC1_OVER ( *(cc2538_reg_t*)0x400d40c4 ) /**< Override configuration register for PC1. PC1 has high drive capability. */
#define IOC_PC2_OVER ( *(cc2538_reg_t*)0x400d40c8 ) /**< Override configuration register for PC2. PC2 has high drive capability. */
#define IOC_PC3_OVER ( *(cc2538_reg_t*)0x400d40cc ) /**< Override configuration register for PC3. PC3 has high drive capability. */
#define IOC_PC4_OVER ( *(cc2538_reg_t*)0x400d40d0 ) /**< Override configuration register for PC4. */
#define IOC_PC5_OVER ( *(cc2538_reg_t*)0x400d40d4 ) /**< Override configuration register for PC5. */
#define IOC_PC6_OVER ( *(cc2538_reg_t*)0x400d40d8 ) /**< Override configuration register for PC6. */
#define IOC_PC7_OVER ( *(cc2538_reg_t*)0x400d40dc ) /**< Override configuration register for PC7. */
#define IOC_PD0_OVER ( *(cc2538_reg_t*)0x400d40e0 ) /**< Override configuration register for PD0. */
#define IOC_PD1_OVER ( *(cc2538_reg_t*)0x400d40e4 ) /**< Override configuration register for PD1. */
#define IOC_PD2_OVER ( *(cc2538_reg_t*)0x400d40e8 ) /**< Override configuration register for PD2. */
#define IOC_PD3_OVER ( *(cc2538_reg_t*)0x400d40ec ) /**< Override configuration register for PD3. */
#define IOC_PD4_OVER ( *(cc2538_reg_t*)0x400d40f0 ) /**< Override configuration register for PD4. */
#define IOC_PD5_OVER ( *(cc2538_reg_t*)0x400d40f4 ) /**< Override configuration register for PD5. */
#define IOC_PD6_OVER ( *(cc2538_reg_t*)0x400d40f8 ) /**< Override configuration register for PD6. */
#define IOC_PD7_OVER ( *(cc2538_reg_t*)0x400d40fc ) /**< Override configuration register for PD7. */
#define IOC_UARTRXD_UART0 ( *(cc2538_reg_t*)0x400d4100 ) /**< Pin selection for UART0 RX. */
#define IOC_UARTCTS_UART1 ( *(cc2538_reg_t*)0x400d4104 ) /**< Pin selection for UART1 CTS. */
#define IOC_UARTRXD_UART1 ( *(cc2538_reg_t*)0x400d4108 ) /**< Pin selection for UART1 RX. */

2
cpu/cc2538/include/periph_cpu.h
View File

@ -60,7 +60,7 @@ typedef uint32_t gpio_t;
/** @} */
/**
* @brief Define custom value to speficy undefined or unused GPIOs
* @brief Define custom value to specify undefined or unused GPIOs
*/
#define GPIO_UNDEF (0xffffffff)

8
cpu/cc2538/periph/adc.c
View File

@ -43,7 +43,7 @@ int adc_init(adc_t line)
/* stop random number generator, and set STSEL = 1 */
soc_adc->ADCCON1 = (SOC_ADC_ADCCON1_STSEL_M | SOC_ADC_ADCCON1_RCTRL_M);
/* disable any DMA, continous ADC settings */
/* disable any DMA, continuous ADC settings */
soc_adc->ADCCON2 = 0x0;
/* configure ADC GPIO as analog input */
gpio_init(adc_config[line], GPIO_IN_ANALOG);
@ -75,14 +75,14 @@ int adc_sample(adc_t line, adc_res_t res)
rshift = SOCADC_12_BIT_RSHIFT;
break;
default:
DEBUG("adc_sample: invalid resultion!\n");
DEBUG("adc_sample: invalid resolution!\n");
return -1;
}
/**
* @attention CC2538 ADC supports differential comparision of two analog
* @attention CC2538 ADC supports differential comparison of two analog
* GPIO inputs, hence negative values are possible. RIOT currently allows
* positive ADC output only. Thus, reduce shift by one to compensate and
* get full value range according to ADC resolution. E.g. 10 Bit resultion
* get full value range according to ADC resolution. E.g. 10 Bit resolution
* with diff ADC would have [-512,511] range but RIOT expects [0,1023].
*/
rshift--;

2
cpu/cc2538/periph/timer.c
View File

@ -187,7 +187,7 @@ int timer_clear(tim_t tim, int channel)
if ( (tim >= TIMER_NUMOF) || (channel >= (int)timer_config[tim].chn) ) {
return -1;
}
/* clear interupt flags */
/* clear interrupt flags */
dev(tim)->IMR &= ~(chn_isr_cfg[channel].flag);
return 0;

4
cpu/cc2538/radio/cc2538_rf_netdev.c
View File

@ -88,7 +88,7 @@ static int _get(netdev_t *netdev, netopt_t opt, void *value, size_t max_len)
if (max_len < sizeof(uint16_t)) {
return -EOVERFLOW;
}
/* This tranceiver only supports page 0 */
/* This transceiver only supports page 0 */
*((uint16_t *)value) = 0;
return sizeof(uint16_t);
@ -201,7 +201,7 @@ static int _set(netdev_t *netdev, netopt_t opt, const void *value, size_t value_
break;
case NETOPT_CHANNEL_PAGE:
/* This tranceiver only supports page 0 */
/* This transceiver only supports page 0 */
if (value_len != sizeof(uint16_t) ||
*((const uint16_t *)value) != 0 ) {
res = -EINVAL;

6
cpu/cortexm_common/cortexm_init.c
View File

@ -93,11 +93,11 @@ bool cpu_check_address(volatile const char *address)
*address;
/* Check BFARVALID flag */
if ((SCB->CFSR & BFARVALID_MASK) != 0) {
/* Bus Fault occured reading the address */
/* Bus Fault occurred reading the address */
is_valid = false;
}
/* Reenable BusFault by clearing BFHFNMIGN */
/* Re-enable BusFault by clearing BFHFNMIGN */
SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
__set_FAULTMASK(mask);
@ -110,7 +110,7 @@ bool cpu_check_address(volatile const char *address)
__asm__ volatile (
"movs r5, #1 \n" /* R5 will be set to 0 by HardFault handler */
/* to indicate HardFault has occured */
/* to indicate HardFault has occurred */
"ldr r1, =0xDEADF00D \n" /* set magic number */
"ldr r2, =0xCAFEBABE \n" /* 2nd magic to be sure */
"ldrb r3, %1 \n" /* probe address */

4
cpu/efm32/periph/i2c.c
View File

@ -191,7 +191,7 @@ int i2c_read_regs(i2c_t dev, uint16_t address, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}
@ -237,7 +237,7 @@ int i2c_write_regs(i2c_t dev, uint16_t address, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}

2
cpu/efm32/periph/rtc_series0.c
View File

@ -74,7 +74,7 @@ void rtc_init(void)
/* initialize the state */
rtc_state.overflows = 0;
/* reset and initialze the peripheral */
/* reset and initialize the peripheral */
RTC_Init_TypeDef init = RTC_INIT_DEFAULT;
init.enable = false;

2
cpu/esp32/cxx/cxa_guard.cpp
View File

@ -75,7 +75,7 @@ namespace __cxxabiv1
assert(0);
}
/* mark the initialization in process and aquire */
/* mark the initialization in process and acquire */
_gt->pending = 1;
critical_exit();

18
cpu/esp32/doc.txt
View File

@ -73,8 +73,8 @@ The following table gives a short reference of all board configuration parameter
Parameter | Short Description | Type*
----------|----------------------------------------|------
[ADC_GPIOS](#esp32_adc_channels) | GPIOs that can be used as ADC channels | m
[CAN_TX](#esp32_can_interfaces) | GPIO used as CAN tranceiver TX signal | o
[CAN_RX](#esp32_can_interfaces) | GPIO used as CAN tranceiver RX signal | o
[CAN_TX](#esp32_can_interfaces) | GPIO used as CAN transceiver TX signal | o
[CAN_RX](#esp32_can_interfaces) | GPIO used as CAN transceiver RX signal | o
[DAC_GPIOS](#esp32_adc_channels) | GPIOs that can be used as DAC channels | m
[I2C0_SPEED](#esp32_i2c_interfaces)| Bus speed of I2C_DEV(0) | o
[I2C0_SCL](#esp32_i2c_interfaces) | GPIO used as SCL for I2C_DEV(0) | o
@ -877,11 +877,11 @@ in SJA1000 PeliCAN mode. Please refer the
[SJA1000 Datasheet](https://www.nxp.com/documents/data_sheet/SJA1000.pdf)
for detailed information about the CAN controller and its programming.
The pin configuration of the CAN tranceiver interface is usually defined
The pin configuration of the CAN transceiver interface is usually defined
in board specific peripheral configuration by
- <b>```CAN_TX```</b>, the GPIO used as TX tranceiver signal, and
- <b>```CAN_RX```</b>, the GPIO used as RX tranceiver signal.
- <b>```CAN_TX```</b>, the GPIO used as TX transceiver signal, and
- <b>```CAN_RX```</b>, the GPIO used as RX transceiver signal.
If the pin configuration is not defined, the following default configuration
is used which can be overridden by the application, see section
@ -894,8 +894,8 @@ CAN | RX | GPIO35 |`CAN_RX` | optional, can be overridden
Example:
```
#define CAN_TX GPIO10 /* CAN TX tranceiver signal */
#define CAN_RX GPIO9 /* CAN RX tranceiver signal */
#define CAN_TX GPIO10 /* CAN TX transceiver signal */
#define CAN_RX GPIO9 /* CAN RX transceiver signal */
```
If the board has an external transceiver module connected to the ESP32 on-board,
@ -1035,7 +1035,7 @@ USEMODULE += esp_now
For ESP-NOW, ESP32 nodes are used in WiFi SoftAP + Station mode to advertise their SSID and become visible to other ESP32 nodes. The SSID of an ESP32 node is the concatenation of the prefix ```RIOT_ESP_``` with the MAC address of its SoftAP WiFi interface. The driver periodically scans all visible ESP32 nodes.
The following parameters are defined for ESP-NOW nodes. These parameters can be overriden by [application-specific board configurations](#esp32_application_specific_board_configuration).
The following parameters are defined for ESP-NOW nodes. These parameters can be overridden by [application-specific board configurations](#esp32_application_specific_board_configuration).
<center>
@ -1173,7 +1173,7 @@ It is important to ensure that the application-specific driver parameter file ``
INCLUDES += -I$(APPDIR)
```
**Pleae note:** To make such application-specific board configurations dependent on the ESP32 MCU or a particular ESP32 board, you should always enclose these definitions in the following constructs:
**Please note:** To make such application-specific board configurations dependent on the ESP32 MCU or a particular ESP32 board, you should always enclose these definitions in the following constructs:
```
#ifdef CPU_ESP32
...

2
cpu/esp32/esp-eth/esp_eth_netdev.c
View File

@ -63,7 +63,7 @@
/**
* There is only one ESP-ETH device. We define it as static device variable
* to have accesss to the device inside ESP-ETH interrupt routines which do
* to have access to the device inside ESP-ETH interrupt routines which do
* not provide an argument that could be used as pointer to the ESP-ETH
* device which triggers the interrupt.
*/

4
cpu/esp32/esp-wifi/esp_wifi_netdev.c
View File

@ -69,7 +69,7 @@
/*
* There is only one ESP WiFi device. We define it as static device variable
* to have accesss to the device inside ESP WiFi interrupt routines which do
* to have access to the device inside ESP WiFi interrupt routines which do
* not provide an argument that could be used as pointer to the ESP WiFi
* device which triggers the interrupt.
*/
@ -79,7 +79,7 @@ static const netdev_driver_t _esp_wifi_driver;
/*
* Ring buffer for rx_buf elements which hold a pointer to the WiFi frame
* buffer, a pointer to the ethernet frame and the frame length for each
* received frame. Since we have anly one device, it the ring buffer can be
* received frame. Since we have only one device, it the ring buffer can be
* static and has not to be exposed as part of the network device.
*/
#ifndef ESP_WIFI_MAX_RX_BUF

2
cpu/esp32/freertos/queue.c
View File

@ -132,7 +132,7 @@ BaseType_t IRAM_ATTR _queue_generic_send(QueueHandle_t xQueue,
/* is there still space in the queue */
if (queue->item_level < queue->item_num || xCopyPosition == queueOVERWRITE) {
uint32_t write_pos;
/* determin the write position in the queue and update positions */
/* determine the write position in the queue and update positions */
if (xCopyPosition == queueSEND_TO_BACK) {
write_pos = queue->item_tail;
queue->item_tail = (queue->item_tail + 1) % queue->item_num;

2
cpu/esp32/include/can_params.h
View File

@ -34,7 +34,7 @@ extern "C" {
#endif
#ifndef CAN_RX
/** Default CAN tranceiver RX pin if not defined in board configuration */
/** Default CAN transceiver RX pin if not defined in board configuration */
#define CAN_RX GPIO35
#endif

2
cpu/esp32/include/esp_common.h
View File

@ -101,7 +101,7 @@ extern "C" {
#endif
/**
* @brief funcion name mappings for source code compatibility with ESP8266 port
* @brief function name mappings for source code compatibility with ESP8266 port
* @{
*/
#define system_get_cpu_freq ets_get_cpu_frequency

2
cpu/esp32/include/exceptions.h
View File

@ -24,7 +24,7 @@
extern "C" {
#endif
/** Initalize exception handler */
/** Initialize exception handler */
extern void init_exceptions(void);
#ifdef __cplusplus

6
cpu/esp32/include/gpio_arch.h
View File

@ -64,7 +64,7 @@ extern const uint32_t _gpio_to_iomux_reg[];
* @brief Set the usage type of the pin
* @param pin GPIO pin
* @param usage GPIO pin usage type
* @return 0 on succes
* @return 0 on success
* -1 on error
*/
int gpio_set_pin_usage(gpio_t pin, gpio_pin_usage_t usage);
@ -72,7 +72,7 @@ int gpio_set_pin_usage(gpio_t pin, gpio_pin_usage_t usage);
/**
* @brief Get the usage type of the pin
* @param pin GPIO pin
* @return GPIO pin usage type on succes
* @return GPIO pin usage type on success
* _NOT_EXIST on error
*/
gpio_pin_usage_t gpio_get_pin_usage(gpio_t pin);
@ -80,7 +80,7 @@ gpio_pin_usage_t gpio_get_pin_usage(gpio_t pin);
/**
* @brief Get the usage type of the pin as string
* @param pin GPIO pin
* @return GPIO pin usage type string on succes
* @return GPIO pin usage type string on success
* _NOT_EXIST on error
*/
const char* gpio_get_pin_usage_str(gpio_t pin);

8
cpu/esp32/include/sdk_conf.h
View File

@ -13,7 +13,7 @@
* @file
* @brief SDK configuration compatible to the ESP-IDF
*
* The SDK configuration can be partially overriden by application-specific
* The SDK configuration can be partially overridden by application-specific
* board configuration.
*
* @author Gunar Schorcht <gunar@schorcht.net>
@ -31,7 +31,7 @@ extern "C" {
#include "board.h"
/**
* @brief Defines the CPU frequency [vallues = 2, 40, 80, 160 and 240]
* @brief Defines the CPU frequency [values = 2, 40, 80, 160 and 240]
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
@ -41,7 +41,7 @@ extern "C" {
* Default console configuration
*
* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
* can be overriden by an application specific configuration.
* can be overridden by an application specific configuration.
*/
#define CONFIG_CONSOLE_UART_NUM 0
@ -59,7 +59,7 @@ extern "C" {
/**
* ESP32 specific configuration
*
* CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ can be overriden by an application
* CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ can be overridden by an application
* specific SDK configuration file.
*/
#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ

2
cpu/esp32/include/syscalls.h
View File

@ -47,7 +47,7 @@ uint64_t system_get_time_64 (void);
/** Time since boot in ms (32bit version) */
uint32_t system_get_time_ms (void);
/** initialize system watchdog timer ans start it */
/** initialize system watchdog timer and start it */
void system_wdt_init (void);
/** start the initialized system watchdog timer */

2
cpu/esp32/ld/esp32.common.ld
View File

@ -85,7 +85,7 @@ SECTIONS
.iram0.text :
{
/* Code marked as runnning out of IRAM */
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)

4
cpu/esp32/periph/adc_ctrl.c
View File

@ -110,7 +110,7 @@ static bool _adc2_ctrl_initialized = false;
void _adc1_ctrl_init(void)
{
/* return if already intialized */
/* return if already initialized */
if (_adc1_ctrl_initialized) {
return;
}
@ -149,7 +149,7 @@ void _adc1_ctrl_init(void)
void _adc2_ctrl_init(void)
{
/* return if already intialized */
/* return if already initialized */
if (_adc2_ctrl_initialized) {
return;
}

2
cpu/esp32/periph/can.c
View File

@ -251,7 +251,7 @@ static int _esp_can_send(candev_t *candev, const struct can_frame *frame)
/* save reference to frame in transmission (marks transmitter as busy) */
dev->tx_frame = (struct can_frame*)frame;
/* prepare the frame as exected by ESP32 */
/* prepare the frame as expected by ESP32 */
_esp_can_frame_t esp_frame = {};
esp_frame.dlc = frame->can_dlc;

2
cpu/esp32/periph/dac.c
View File

@ -61,7 +61,7 @@ int8_t dac_init (dac_t line)
uint8_t rtcio = _gpio_rtcio_map[dac_channels[line]];
uint8_t idx;
/* try to initialize the pin as DAC ouput */
/* try to initialize the pin as DAC output */
if (gpio_get_pin_usage(_adc_hw[rtcio].gpio) != _GPIO) {
LOG_TAG_ERROR("dac", "GPIO%d is used for %s and cannot be used as "
"DAC output\n", _adc_hw[rtcio].gpio,

4
cpu/esp32/periph/gpio.c
View File

@ -189,7 +189,7 @@ gpio_pin_usage_t _gpio_pin_usage [GPIO_PIN_NUMOF] = {
_SPIF, /* gpio7 not configurable, used as SPI MISO */
_SPIF, /* gpio8 not configurable, used as SPI MOSI */
#if defined(FLASH_MODE_QIO) || defined(FLASH_MODE_QOUT)
/* in qio and qout mode thes pins are used for quad SPI */
/* in qio and qout mode these pins are used for quad SPI */
_SPIF, /* gpio9 not configurable, used as SPI HD */
_SPIF, /* gpio10 not configurable, used as SPI WP */
#else
@ -274,7 +274,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
case GPIO_IN_PD:
case GPIO_IN_PU:
/* GPIOs 34 ... 39 have no software controlable pullups/pulldowns */
/* GPIOs 34 ... 39 have no software controllable pullups/pulldowns */
LOG_TAG_ERROR("gpio",
"GPIO%d has no pullups/pulldowns\n", pin);
return -1;

2
cpu/esp32/periph/i2c_hw.c
View File

@ -685,7 +685,7 @@ void _i2c_transfer_timeout (void *arg)
{
i2c_t dev = (i2c_t)arg;
/* reset the hardware if it I2C got stucked */
/* reset the hardware if it I2C got stuck */
_i2c_reset_hw(dev);
/* set result to timeout */

4
cpu/esp32/periph/i2c_sw.c
View File

@ -220,7 +220,7 @@ int /* IRAM */ i2c_read_bytes(i2c_t dev, uint16_t addr, void *data, size_t len,
/* prepare 10 bit address bytes */
uint8_t addr1 = 0xf0 | (addr & 0x0300) >> 7 | I2C_READ;
uint8_t addr2 = addr & 0xff;
/* send address bytes wit read flag */
/* send address bytes with read flag */
if ((res = _i2c_write_byte (bus, addr1)) != 0 ||
(res = _i2c_write_byte (bus, addr2)) != 0) {
/* abort transfer */
@ -472,7 +472,7 @@ static /* IRAM */ int _i2c_start_cond(_i2c_bus_t* bus)
/* SDA = passive HIGH (floating and pulled-up) */
_i2c_sda_high (bus);
/* t_VD;DAT not neccessary */
/* t_VD;DAT not necessary */
/* _i2c_delay (bus); */
/* SCL = passive HIGH (floating and pulled-up) */

8
cpu/esp32/periph/pwm.c
View File

@ -41,7 +41,7 @@
#define PWM_CLK (160000000UL) /* base clock of PWM devices */
#define PWM_CPS_MAX (10000000UL) /* maximum cycles per second supported */
#define PWM_CPS_MIN (2500UL) /* minumum cycles per second supported */
#define PWM_CPS_MIN (2500UL) /* minimum cycles per second supported */
#define PWM_TIMER_MOD_FREEZE 0 /* timer is disabled */
#define PWM_TIMER_MOD_UP 1 /* timer counts up */
@ -54,7 +54,7 @@
#define PWM_TIMER_STARTS_STOPS_AT_TEZ 3 /* PWM starts and stops at next TEZ */
#define PWM_TIMER_STARTS_STOPS_AT_TEP 4 /* PWM starts and stops at next TEP */
#define PWM_TIMER_UPDATE_IMMIDIATE 0 /* update period immediatly */
#define PWM_TIMER_UPDATE_IMMIDIATE 0 /* update period immediately */
#define PWM_TIMER_UPDATE_AT_TEZ 1 /* update period at TEZ */
#define PWM_TIMER_UPDATE_AT_SYNC 2 /* update period at sync */
#define PWM_TIMER_UPDATE_AT_TEZ_SYNC 3 /* update period at TEZ and sync */
@ -319,7 +319,7 @@ static void _pwm_start(pwm_t pwm)
uint32_t cps = period * freq;
/* maximum number of timer clock cycles per second (freq*period) must not
be greater than PWM_CPS_MAX, reduce the freq if neccessary and keep
be greater than PWM_CPS_MAX, reduce the freq if necessary and keep
the resolution */
if (cps > PWM_CPS_MAX) {
freq = PWM_CPS_MAX / period;
@ -328,7 +328,7 @@ static void _pwm_start(pwm_t pwm)
__func__, freq);
}
/* minimum number of timer clock cycles per second (freq*period) must not
be less than PWM_CPS_MIN, increase the freq if neccessary and keep
be less than PWM_CPS_MIN, increase the freq if necessary and keep
the resolution */
else if (cps < PWM_CPS_MIN) {
freq = PWM_CPS_MIN / period;

4
cpu/esp32/periph/rtc.c
View File

@ -21,7 +21,7 @@
/*
* If RTC_TIMER_USED is 0, the microsecond system timer is used to emulate an
* RTC, otherwise the RTC timer is used. Advantage of using RTC over sytem
* RTC, otherwise the RTC timer is used. Advantage of using RTC over system
* timer is that it also continues in deep sleep and after software reset.
*/
#define RTC_TIMER_USED 1
@ -175,7 +175,7 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
/*
* RTC doesn't provide alarm functionality in active mode. At least
* the RTC main timer seems not to work. Therefore we always use the
* system timer for alarms. The Advantage of using RTC over sytem timer
* system timer for alarms. The Advantage of using RTC over system timer
* is that it also continues in deep sleep and after software reset.
*/
#if 0 /* TODO should be RTC_TIMER_USED */

4
cpu/esp32/periph/spi.c
View File

@ -49,7 +49,7 @@
#define FSPI_MISO GPIO7
#define FSPI_MOSI GPIO8
/** stucture which decribes all properties of one SPI bus */
/** structure which describes all properties of one SPI bus */
struct _spi_bus_t {
spi_dev_t* regs; /* pointer to register data struct of the SPI device */
uint8_t mod; /* peripheral hardware module of the SPI interface */
@ -180,7 +180,7 @@ static void _spi_init_internal (spi_t bus)
_spi[bus].regs->ctrl.fastrd_mode = 0;
_spi[bus].regs->ctrl.wp = 0;
/* aquire and release to set default parameters */
/* acquire and release to set default parameters */
spi_acquire(bus, GPIO_UNDEF, SPI_MODE_0, SPI_CLK_1MHZ);
spi_release(bus);
}

4
cpu/esp32/periph/timer.c
View File

@ -79,7 +79,7 @@ struct hw_timer_regs_t {
uint32_t unused : 10;
uint32_t ALARM_EN : 1; /* alarms are enabled */
uint32_t LEVEL_INT_EN: 1; /* alarms will generate level type interrupt */
uint32_t EDGE_INT_EN : 1; /* alarms will generate egde type interrupt */
uint32_t EDGE_INT_EN : 1; /* alarms will generate edge type interrupt */
uint32_t DIVIDER : 16; /* timer clock prescale value (basis is ABP) */
uint32_t AUTORELOAD : 1; /* auto-reload on alarms */
uint32_t INCREASE : 1; /* count up */
@ -173,7 +173,7 @@ void IRAM hw_timer_handler(void* arg)
(void)arg;
/* since all timer interrupt sources are routed to the same cpu interrupt */
/* signal, we can't use arg to identify the timer wich caused the it */
/* signal, we can't use arg to identify the timer which caused the it */
irq_isr_enter();

4
cpu/esp32/periph/uart.c
View File

@ -62,7 +62,7 @@ struct uart_hw_t {
uint8_t int_src; /* peripheral interrupt source used by the UART device */
};
/* hardware ressources */
/* hardware resources */
static struct uart_hw_t _uarts[] = {
{
.regs = &UART0,
@ -259,7 +259,7 @@ static uint8_t IRAM _uart_rx_one_char (uart_t uart)
/* send one data byte with wait */
static void _uart_tx_one_char(uart_t uart, uint8_t data)
{
/* wait until at least one byte is avaiable in the TX FIFO */
/* wait until at least one byte is available in the TX FIFO */
while (_uarts[uart].regs->status.txfifo_cnt >= UART_FIFO_MAX) {}
/* send the byte by placing it in the TX FIFO using MPU */

6
cpu/esp32/startup.c
View File

@ -208,7 +208,7 @@ static void IRAM system_clk_init (void)
/* set SLOW_CLK to internal low power clock of 150 kHz */
rtc_select_slow_clk(RTC_SLOW_FREQ_RTC);
/* wait until UART is idle to avoid loosing output */
/* wait until UART is idle to avoid losing output */
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
ets_printf("Switching system clocks can lead to some unreadable characters\n");
ets_printf("This message is usually not visible at the console\n");
@ -216,7 +216,7 @@ static void IRAM system_clk_init (void)
/* determine configured CPU clock frequency from sdk_conf.h */
rtc_cpu_freq_t freq;
switch (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
case 40: freq = RTC_CPU_FREQ_XTAL; /* derived from external cristal */
case 40: freq = RTC_CPU_FREQ_XTAL; /* derived from external crystal */
break; /* normally 40 MHz */
case 80: freq = RTC_CPU_FREQ_80M; /* derived from PLL */
break;
@ -266,7 +266,7 @@ static NORETURN void IRAM system_init (void)
/* initialize the RTC module (restore timer values from RTC RAM) */
rtc_init();
/* install execption handlers */
/* install exception handlers */
init_exceptions();
/* clear interrupt matrix */

6
cpu/esp32/syscalls.c
View File

@ -241,7 +241,7 @@ void heap_stats(void)
#else /* MODULE_ESP_IDF_HEAP */
/* for compatibiliy with ESP-IDF heap functions */
/* for compatibility with ESP-IDF heap functions */
void* IRAM heap_caps_malloc( size_t size, uint32_t caps )
{
(void)caps;
@ -433,8 +433,8 @@ void system_wdt_init (void)
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; /* disable write protection */
TIMERG0.wdt_config0.stg0 = TIMG_WDT_STG_SEL_INT; /* stage0 timeout: interrupt */
TIMERG0.wdt_config0.stg1 = TIMG_WDT_STG_SEL_RESET_SYSTEM; /* stage1 timeout: sys reset */
TIMERG0.wdt_config0.sys_reset_length = 7; /* sys reset signal lenght: 3.2 us */
TIMERG0.wdt_config0.cpu_reset_length = 7; /* sys reset signal lenght: 3.2 us */
TIMERG0.wdt_config0.sys_reset_length = 7; /* sys reset signal length: 3.2 us */
TIMERG0.wdt_config0.cpu_reset_length = 7; /* sys reset signal length: 3.2 us */
TIMERG0.wdt_config0.edge_int_en = 0;
TIMERG0.wdt_config0.level_int_en = 1;

2
cpu/esp32/thread_arch.c
View File

@ -140,7 +140,7 @@ char* thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_sta
/* Clear whole stack with a known value to assist debugging */
#if !defined(DEVELHELP) && !defined(SCHED_TEST_STACK)
/* Unfortunatly, this affects thread_measure_stack_free function */
/* Unfortunately, this affects thread_measure_stack_free function */
memset(stack_start, 0, stack_size);
#else
memset(sp, 0, XT_STK_FRMSZ + XT_CP_SIZE);

2
cpu/esp_common/esp-now/esp_now_netdev.h
View File

@ -61,7 +61,7 @@ extern "C" {
extern const netdev_driver_t esp_now_driver;
/**
* @brief Header with neccesary flags for ESP-NOW packets
* @brief Header with necessary flags for ESP-NOW packets
*/
typedef struct __attribute__((packed))
{

6
cpu/fe310/periph/gpio.c
View File

@ -115,7 +115,7 @@ void gpio_isr(int num)
isr_ctx[pin].cb(isr_ctx[pin].arg);
}
/* Clear interupt */
/* Clear interrupt */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IP) |= (1 << pin);
@ -169,7 +169,7 @@ void gpio_irq_enable(gpio_t pin)
return;
}
/* Enable interupt for pin */
/* Enable interrupt for pin */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IE) |= (1 << pin);
@ -196,7 +196,7 @@ void gpio_irq_disable(gpio_t pin)
return;
}
/* Disable interupt for pin */
/* Disable interrupt for pin */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IE) &= ~(1 << pin);

2
cpu/kinetis/dist/check-fcfield.sh vendored
View File

@ -35,7 +35,7 @@ get_fc_field()
elif [ ${1##*.} = hex ]; then
"${OBJDUMP}" --start-address=${FCFIELD_START} --stop-address=${FCFIELD_END} ${1} -s
else
echo "Unkown file extension: ${1##*.}"
echo "Unknown file extension: ${1##*.}"
exit 1
fi
}

2
cpu/kinetis/doc.txt
View File

@ -114,7 +114,7 @@ RTC is clocked by a 32.768 kHz clock.
Please note the manual of your MCU or SiP for the clock setting for the RTC
module. After initialization Time Seconds Register (TSR) increments once a
second. The TSR (also TAR) value will be converted to the stuct tm and back
second. The TSR (also TAR) value will be converted to the struct tm and back
with the help of stdlib functions that are defined in time.h. The driver
supports alarm, it is stored in the Time Alarm Registers (TAR) and the unit is
seconds.

2
cpu/kinetis/include/vectors_kinetis.h
View File

@ -92,7 +92,7 @@ void isr_dma14_dma30(void); /**< DMA channel 14, 30 transfer complete interrupt
void isr_dma15_dma31(void); /**< DMA channel 15, 31 transfer complete interrupt handler */
void isr_dma_error(void); /**< DMA Error interrupt handler */
void isr_enet_1588_timer(void); /**< Ethernet MAC IEEE 1588 timer interrupt handler */
void isr_enet_error(void); /**< Ethernet MAC error and miscelaneous interrupt handler */
void isr_enet_error(void); /**< Ethernet MAC error and miscellaneous interrupt handler */
void isr_enet_receive(void); /**< Ethernet MAC receive interrupt handler */
void isr_enet_transmit(void); /**< Ethernet MAC transmit interrupt handler */
void isr_ftfa(void); /**< FTFA Command complete interrupt handler */

2
cpu/kinetis/periph/ics.c
View File

@ -50,7 +50,7 @@
** - rev. 1.0 (2013-07-30)
** Initial version.
** - rev. 1.1 (2013-10-29)
** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
** Definition of BITBAND macros updated to support peripherals with 32-bit access disabled.
** - rev. 1.2 (2014-01-10)
** CAN - Corrected address of TSIDR1 register.
** CAN - Corrected name of MSCAN_TDLR bit DLC to TDLC.

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