diff --git a/cpu/cc2538/periph/uart.c b/cpu/cc2538/periph/uart.c
index a8904d7492..4e3de23b8e 100644
--- a/cpu/cc2538/periph/uart.c
+++ b/cpu/cc2538/periph/uart.c
@@ -30,8 +30,6 @@
 #undef BIT
 #define BIT(n) ( 1 << (n) )
 
-#define UART_WORD_LENGTH        8
-
 enum {
     FIFO_LEVEL_1_8TH = 0,
     FIFO_LEVEL_2_8TH = 1,
@@ -40,6 +38,17 @@ enum {
     FIFO_LEVEL_7_8TH = 4,
 };
 
+/* Valid word lengths for the LCRHbits.WLEN bit field: */
+enum {
+    WLEN_5_BITS = 0,
+    WLEN_6_BITS = 1,
+    WLEN_7_BITS = 2,
+    WLEN_8_BITS = 3,
+};
+
+/* Bit field definitions for the UART Line Control Register: */
+#define FEN   BIT( 4) /**< Enable FIFOs */
+
 /* Bit masks for the UART Masked Interrupt Status (MIS) Register: */
 #define OEMIS BIT(10) /**< UART overrun error masked status */
 #define BEMIS BIT( 9) /**< UART break error masked status */
@@ -87,10 +96,10 @@ static void reset(cc2538_uart_t *u)
     u->cc2538_uart_dr.ECR = 0xFF;
 
     /* Flush FIFOs by clearing LCHR.FEN */
-    u->cc2538_uart_lcrh.LCRHbits.FEN = 0;
+    u->cc2538_uart_lcrh.LCRH &= ~FEN;
 
     /* Restore LCHR configuration */
-    u->cc2538_uart_lcrh.LCRHbits.FEN = 1;
+    u->cc2538_uart_lcrh.LCRH |= FEN;
 
     /* UART Enable */
     u->cc2538_uart_ctl.CTLbits.UARTEN = 1;
@@ -303,10 +312,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
     u->FBRD = divisor & DIVFRAC_MASK;
 
     /* Configure line control for 8-bit, no parity, 1 stop bit and enable  */
-    u->cc2538_uart_lcrh.LCRH = 0;
-    u->cc2538_uart_lcrh.LCRHbits.WLEN = UART_WORD_LENGTH - 5;
-    u->cc2538_uart_lcrh.LCRHbits.FEN  = 1;                    /**< Enable FIFOs */
-    u->cc2538_uart_lcrh.LCRHbits.PEN  = 0;                    /**< No parity */
+    u->cc2538_uart_lcrh.LCRH = (WLEN_8_BITS << 5) | FEN;
 
     /* UART Enable */
     u->cc2538_uart_ctl.CTLbits.UARTEN = 1;