diff --git a/boards/nucleo-l4r5zi/include/periph_conf.h b/boards/nucleo-l4r5zi/include/periph_conf.h
index d7f8ac8ed8..de1e1f49c7 100644
--- a/boards/nucleo-l4r5zi/include/periph_conf.h
+++ b/boards/nucleo-l4r5zi/include/periph_conf.h
@@ -19,11 +19,7 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-#include "periph_cpu.h"
-
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(120)
-
 #ifndef CONFIG_BOARD_HAS_LSE
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
@@ -32,7 +28,8 @@
 #define CONFIG_CLOCK_PLL_N              (30)
 #endif
 
-#include "l4/cfg_clock_default.h"
+#include "periph_cpu.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 
diff --git a/boards/nucleo-l552ze-q/include/periph_conf.h b/boards/nucleo-l552ze-q/include/periph_conf.h
index 985c14a895..f2331145a8 100644
--- a/boards/nucleo-l552ze-q/include/periph_conf.h
+++ b/boards/nucleo-l552ze-q/include/periph_conf.h
@@ -20,9 +20,7 @@
 #define PERIPH_CONF_H
 
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(110)
-
-/* Reach 108MHz by by default setting custom PLL_N factor */
+/* Reach 108MHz by default by setting custom PLL_N factor */
 #ifndef CONFIG_CLOCK_PLL_N
 #define CONFIG_CLOCK_PLL_N              27
 #endif
@@ -33,7 +31,7 @@
 #endif
 
 #include "periph_cpu.h"
-#include "l4/cfg_clock_default.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim5.h"
diff --git a/boards/p-nucleo-wb55/include/periph_conf.h b/boards/p-nucleo-wb55/include/periph_conf.h
index 5cc010830a..dacc45b1c8 100644
--- a/boards/p-nucleo-wb55/include/periph_conf.h
+++ b/boards/p-nucleo-wb55/include/periph_conf.h
@@ -20,11 +20,7 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-#include "periph_cpu.h"
-
 /* Add specific clock configuration (HSE, LSE) for this board here */
-#define CLOCK_CORECLOCK_MAX             MHZ(64)
-
 #ifndef CONFIG_BOARD_HAS_LSE
 #define CONFIG_BOARD_HAS_LSE            1
 #endif
@@ -39,8 +35,8 @@
 #define CLOCK_EXTAHB_DIV    RCC_EXTCFGR_C2HPRE_3
 #define CLOCK_EXTAHB        (CLOCK_CORECLOCK / 2)
 
-#include "l4/cfg_clock_default.h"
-
+#include "periph_cpu.h"
+#include "clk_conf.h"
 #include "cfg_i2c1_pb8_pb9.h"
 #include "cfg_rtt_default.h"
 #include "cfg_timer_tim2.h"
diff --git a/cpu/stm32/include/clk/clk_conf.h b/cpu/stm32/include/clk/clk_conf.h
index cc668aab03..797f00284f 100644
--- a/cpu/stm32/include/clk/clk_conf.h
+++ b/cpu/stm32/include/clk/clk_conf.h
@@ -37,7 +37,7 @@
 #include "l0l1/cfg_clock_default.h"
 #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32L5) || \
       defined(CPU_FAM_STM32WB)
-#include "l4/cfg_clock_default.h"
+#include "l4l5wb/cfg_clock_default.h"
 #else
 #error "No clock configuration available"
 #endif
diff --git a/cpu/stm32/include/clk/l4/cfg_clock_default.h b/cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h
similarity index 89%
rename from cpu/stm32/include/clk/l4/cfg_clock_default.h
rename to cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h
index 650ee3ac49..a403958143 100644
--- a/cpu/stm32/include/clk/l4/cfg_clock_default.h
+++ b/cpu/stm32/include/clk/l4l5wb/cfg_clock_default.h
@@ -18,8 +18,8 @@
  * @author      Alexandre Abadie <alexandre.abadie@inria.fr>
  */
 
-#ifndef CLK_L4_CFG_CLOCK_DEFAULT_H
-#define CLK_L4_CFG_CLOCK_DEFAULT_H
+#ifndef CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
+#define CLK_L4L5WB_CFG_CLOCK_DEFAULT_H
 
 #ifdef __cplusplus
 extern "C" {
@@ -167,9 +167,22 @@ extern "C" {
  */
 #define CLOCK_CORECLOCK                 \
         ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
-#ifndef CLOCK_CORECLOCK_MAX
+
+/* Set max allowed sysclk */
+#if defined(CPU_FAM_STM32WB)
+#define CLOCK_CORECLOCK_MAX             MHZ(64)
+#elif defined(CPU_FAM_STM32L5)
+#define CLOCK_CORECLOCK_MAX             MHZ(110)
+#elif defined(CPU_LINE_STM32L4A6xx) || defined(CPU_LINE_STM32L4P5xx) || \
+      defined(CPU_LINE_STM32L4Q5xx) || defined(CPU_LINE_STM32L4R5xx) || \
+      defined(CPU_LINE_STM32L4R7xx) || defined(CPU_LINE_STM32L4R9xx) || \
+      defined(CPU_LINE_STM32L4S5xx) || defined(CPU_LINE_STM32L4S7xx) || \
+      defined(CPU_LINE_STM32L4S9xx)
+#define CLOCK_CORECLOCK_MAX             MHZ(120)
+#else /* all the other L4 */
 #define CLOCK_CORECLOCK_MAX             MHZ(80)
 #endif
+
 #if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
 #if CLOCK_CORECLOCK_MAX == MHZ(64)
 #error "SYSCLK cannot exceed 64MHz"
@@ -200,5 +213,5 @@ extern "C" {
 }
 #endif
 
-#endif /* CLK_L4_CFG_CLOCK_DEFAULT_H */
+#endif /* CLK_L4L5WB_CFG_CLOCK_DEFAULT_H */
 /** @} */