diff --git a/cpu/cc26x0/Makefile.include b/cpu/cc26x0/Makefile.include
index afe2d78fa8..0d7b49ff1c 100644
--- a/cpu/cc26x0/Makefile.include
+++ b/cpu/cc26x0/Makefile.include
@@ -3,7 +3,7 @@ CPU_VARIANT = x0
 ROM_START_ADDR ?= 0x00000000
 RAM_START_ADDR ?= 0x20000000
 
-ROM_LEN ?= 0x1FFA8 # 128K - 88 bytes
+ROM_LEN ?= 128K
 RAM_LEN ?= 20K
 
 include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
diff --git a/cpu/cc26x2_cc13x2/Makefile.include b/cpu/cc26x2_cc13x2/Makefile.include
index b14d2261a7..f3fc3769ca 100644
--- a/cpu/cc26x2_cc13x2/Makefile.include
+++ b/cpu/cc26x2_cc13x2/Makefile.include
@@ -2,7 +2,7 @@ CPU_VARIANT = x2
 
 ROM_START_ADDR ?= 0x00000000
 RAM_START_ADDR ?= 0x20000000
-ROM_LEN ?= 0x57FA8 # 352K - 88 config bytes
+ROM_LEN ?= 352K
 RAM_LEN ?= 80K
 
 include ${RIOTCPU}/cc26xx_cc13xx/Makefile.include
diff --git a/cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld b/cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld
index 62cb3d8042..109ba9033c 100644
--- a/cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld
+++ b/cpu/cc26xx_cc13xx/ldscripts/cc26xx_cc13xx.ld
@@ -22,7 +22,8 @@ INCLUDE cortexm_rom_offset.ld
 MEMORY
 {
     rom      (rx)   : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
-    ccfg     (rx)   : ORIGIN = 0x00057FA8,                    LENGTH = 88
+    /* CCFG starts at the end of ROM */
+    ccfg     (rx)   : ORIGIN = _rom_length - 88,              LENGTH = 88
     /* GPRAM is only available when cache is disabled. When GPRAM is enabled it
      * is used as a backup RAM at the expense of slower CPU execution time */
     gpram           : ORIGIN = 0x11000000,                    LENGTH = 8K