From efa4f985ef7690c7c20253d17a0da3b9bd9e5d1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joakim=20Nohlg=C3=A5rd?= Date: Fri, 4 Aug 2017 06:32:41 +0200 Subject: [PATCH] k60: Update to latest vendor headers --- cpu/k60/include/vendor/MK60D10.h | 21095 +++++++++++++---------------- 1 file changed, 9742 insertions(+), 11353 deletions(-) diff --git a/cpu/k60/include/vendor/MK60D10.h b/cpu/k60/include/vendor/MK60D10.h index b2bc3fd15f..041e21f15c 100644 --- a/cpu/k60/include/vendor/MK60D10.h +++ b/cpu/k60/include/vendor/MK60D10.h @@ -1,21 +1,33 @@ /* ** ################################################################### +** Processors: MK60DN256VLL10 +** MK60DN256VLQ10 +** MK60DN256VMC10 +** MK60DN256VMD10 +** MK60DN512VLL10 +** MK60DN512VLQ10 +** MK60DN512VMC10 +** MK60DN512VMD10 +** MK60DX256VLL10 +** MK60DX256VLQ10 +** MK60DX256VMC10 +** MK60DX256VMD10 +** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler -** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler ** ** Reference manual: K60P144M100SF2V2RM Rev. 2, Jun 2012 -** Version: rev. 1.8, 2014-10-14 -** Build: b141015 +** Version: rev. 1.9, 2015-07-29 +** Build: b170112 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK60D10 ** -** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. -** All rights reserved. -** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** @@ -26,7 +38,7 @@ ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** o Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -41,8 +53,8 @@ ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2012-01-03) @@ -68,48 +80,29 @@ ** Update of startup files - possibility to override DefaultISR added. ** - rev. 1.8 (2014-10-14) ** Renamed interrupt vector Watchdog to WDOG_EWM and LPTimer to LPTMR0 -** - rev. 1.8-jg (2015-05-18) -** Removed BITBAND_REG macro. +** - rev. 1.9 (2015-07-29) +** Correction of backward compatibility. ** ** ################################################################### */ /*! * @file MK60D10.h - * @version 1.8-jg - * @date 2015-05-18 + * @version 1.9 + * @date 2015-07-29 * @brief CMSIS Peripheral Access Layer for MK60D10 * * CMSIS Peripheral Access Layer for MK60D10 */ -#ifdef __cplusplus -extern "C" -{ -#endif - -/* ---------------------------------------------------------------------------- - -- MCU activation - ---------------------------------------------------------------------------- */ - -/* Prevention from multiple including the same memory map */ -#if !defined(MK60D10_H_) /* Check if memory map has not been already included */ -#define MK60D10_H_ -#define MCU_MK60D10 - -/* Check if another memory map has not been also included */ -#if (defined(MCU_ACTIVE)) - #error MK60D10 memory map: There is already included another memory map. Only one memory map can be included. -#endif /* (defined(MCU_ACTIVE)) */ -#define MCU_ACTIVE - -#include +#ifndef _MK60D10_H_ +#define _MK60D10_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100u +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0008u +#define MCU_MEM_MAP_VERSION_MINOR 0x0009U /** * @brief Macro to calculate address of an aliased word in the peripheral @@ -128,7 +121,8 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -137,7 +131,7 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can @@ -146,7 +140,7 @@ extern "C" * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ -#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers @@ -197,7 +191,7 @@ typedef enum IRQn { FTFL_IRQn = 18, /**< FTFL command complete */ Read_Collision_IRQn = 19, /**< FTFL read collision */ LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ - LLW_IRQn = 21, /**< Low leakage wakeup */ + LLWU_IRQn = 21, /**< Low leakage wakeup */ WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ RNG_IRQn = 23, /**< Randon number generator */ I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ @@ -308,6 +302,108 @@ typedef enum IRQn { */ /* end of group Cortex_Core_Configuration */ +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< Disable */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 receive complete */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 transmit complete */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 receive complete */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 transmit complete */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 receive complete */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 transmit complete */ + kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 receive complete */ + kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 transmit complete */ + kDmaRequestMux0UART4Rx = 10|0x100U, /**< UART4 receive complete */ + kDmaRequestMux0UART4Tx = 11|0x100U, /**< UART4 transmit complete */ + kDmaRequestMux0UART5Rx = 12|0x100U, /**< UART5 receive complete */ + kDmaRequestMux0UART5Tx = 13|0x100U, /**< UART5 transmit complete */ + kDmaRequestMux0I2S0Rx = 14|0x100U, /**< I2S0 receive complete */ + kDmaRequestMux0I2S0Tx = 15|0x100U, /**< I2S0 transmit complete */ + kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 receive complete */ + kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 transmit complete */ + kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 receive complete */ + kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 transmit complete */ + kDmaRequestMux0SPI2Rx = 20|0x100U, /**< SPI2 receive complete */ + kDmaRequestMux0SPI2Tx = 21|0x100U, /**< SPI2 transmit complete */ + kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0 transmission complete */ + kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1 transmission complete */ + kDmaRequestMux0FTM0Channel0 = 24|0x100U, /**< FTM0 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel1 = 25|0x100U, /**< FTM0 channel 1 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel2 = 26|0x100U, /**< FTM0 channel 2 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel3 = 27|0x100U, /**< FTM0 channel 3 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel4 = 28|0x100U, /**< FTM0 channel 4 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel5 = 29|0x100U, /**< FTM0 channel 5 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel6 = 30|0x100U, /**< FTM0 channel 6 event (CMP or CAP) */ + kDmaRequestMux0FTM0Channel7 = 31|0x100U, /**< FTM0 channel 7 event (CMP or CAP) */ + kDmaRequestMux0FTM1Channel0 = 32|0x100U, /**< FTM1 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM1Channel1 = 33|0x100U, /**< FTM1 channel 1 event (CMP or CAP) */ + kDmaRequestMux0FTM2Channel0 = 34|0x100U, /**< FTM2 channel 0 event (CMP or CAP) */ + kDmaRequestMux0FTM2Channel1 = 35|0x100U, /**< FTM2 channel 1 event (CMP or CAP) */ + kDmaRequestMux0IEEE1588Timer0 = 36|0x100U, /**< Ethernet IEEE 1588 timer 0 */ + kDmaRequestMux0IEEE1588Timer1 = 37|0x100U, /**< Ethernet IEEE 1588 timer 1 */ + kDmaRequestMux0IEEE1588Timer2 = 38|0x100U, /**< Ethernet IEEE 1588 timer 2 */ + kDmaRequestMux0IEEE1588Timer3 = 39|0x100U, /**< Ethernet IEEE 1588 timer 3 */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0 conversion complete */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1 conversion complete */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0 Output */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1 Output */ + kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 Output */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0 buffer pointer reaches upper or lower limit */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1 buffer pointer reaches upper or lower limit */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT end of modulation cycle event */ + kDmaRequestMux0PDB0 = 48|0x100U, /**< PDB0 programmable interrupt delay event */ + kDmaRequestMux0PortA = 49|0x100U, /**< PORTA rising, falling or both edges */ + kDmaRequestMux0PortB = 50|0x100U, /**< PORTB rising, falling or both edges */ + kDmaRequestMux0PortC = 51|0x100U, /**< PORTC rising, falling or both edges */ + kDmaRequestMux0PortD = 52|0x100U, /**< PORTD rising, falling or both edges */ + kDmaRequestMux0PortE = 53|0x100U, /**< PORTE rising, falling or both edges */ + kDmaRequestMux0AlwaysOn54 = 54|0x100U, /**< Always enabled 54 */ + kDmaRequestMux0AlwaysOn55 = 55|0x100U, /**< Always enabled 55 */ + kDmaRequestMux0AlwaysOn56 = 56|0x100U, /**< Always enabled 56 */ + kDmaRequestMux0AlwaysOn57 = 57|0x100U, /**< Always enabled 57 */ + kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< Always enabled 58 */ + kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< Always enabled 59 */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< Always enabled 60 */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< Always enabled 61 */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< Always enabled 62 */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< Always enabled 63 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -373,50 +469,7 @@ typedef struct { __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ -} ADC_Type, *ADC_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- ADC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros - * @{ - */ - - -/* ADC - Register accessors */ -#define ADC_SC1_REG(base,index) ((base)->SC1[index]) -#define ADC_CFG1_REG(base) ((base)->CFG1) -#define ADC_CFG2_REG(base) ((base)->CFG2) -#define ADC_R_REG(base,index) ((base)->R[index]) -#define ADC_CV1_REG(base) ((base)->CV1) -#define ADC_CV2_REG(base) ((base)->CV2) -#define ADC_SC2_REG(base) ((base)->SC2) -#define ADC_SC3_REG(base) ((base)->SC3) -#define ADC_OFS_REG(base) ((base)->OFS) -#define ADC_PG_REG(base) ((base)->PG) -#define ADC_MG_REG(base) ((base)->MG) -#define ADC_CLPD_REG(base) ((base)->CLPD) -#define ADC_CLPS_REG(base) ((base)->CLPS) -#define ADC_CLP4_REG(base) ((base)->CLP4) -#define ADC_CLP3_REG(base) ((base)->CLP3) -#define ADC_CLP2_REG(base) ((base)->CLP2) -#define ADC_CLP1_REG(base) ((base)->CLP1) -#define ADC_CLP0_REG(base) ((base)->CLP0) -#define ADC_PGA_REG(base) ((base)->PGA) -#define ADC_CLMD_REG(base) ((base)->CLMD) -#define ADC_CLMS_REG(base) ((base)->CLMS) -#define ADC_CLM4_REG(base) ((base)->CLM4) -#define ADC_CLM3_REG(base) ((base)->CLM3) -#define ADC_CLM2_REG(base) ((base)->CLM2) -#define ADC_CLM1_REG(base) ((base)->CLM1) -#define ADC_CLM0_REG(base) ((base)->CLM0) - -/*! - * @} - */ /* end of group ADC_Register_Accessor_Macros */ - +} ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks @@ -427,156 +480,208 @@ typedef struct { * @{ */ -/* SC1 Bit Fields */ -#define ADC_SC1_ADCH_MASK 0x1Fu -#define ADC_SC1_ADCH_SHIFT 0 -#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) -#define AIPS_PACRA_REG(base) ((base)->PACRA) -#define AIPS_PACRB_REG(base) ((base)->PACRB) -#define AIPS_PACRC_REG(base) ((base)->PACRC) -#define AIPS_PACRD_REG(base) ((base)->PACRD) -#define AIPS_PACRE_REG(base) ((base)->PACRE) -#define AIPS_PACRF_REG(base) ((base)->PACRF) -#define AIPS_PACRG_REG(base) ((base)->PACRG) -#define AIPS_PACRH_REG(base) ((base)->PACRH) -#define AIPS_PACRI_REG(base) ((base)->PACRI) -#define AIPS_PACRJ_REG(base) ((base)->PACRJ) -#define AIPS_PACRK_REG(base) ((base)->PACRK) -#define AIPS_PACRL_REG(base) ((base)->PACRL) -#define AIPS_PACRM_REG(base) ((base)->PACRM) -#define AIPS_PACRN_REG(base) ((base)->PACRN) -#define AIPS_PACRO_REG(base) ((base)->PACRO) -#define AIPS_PACRP_REG(base) ((base)->PACRP) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - +} AIPS_Type; /* ---------------------------------------------------------------------------- -- AIPS Register Masks @@ -762,827 +750,1246 @@ typedef struct { * @{ */ -/* MPRA Bit Fields */ -#define AIPS_MPRA_MPL5_MASK 0x100u -#define AIPS_MPRA_MPL5_SHIFT 8 -#define AIPS_MPRA_MTW5_MASK 0x200u -#define AIPS_MPRA_MTW5_SHIFT 9 -#define AIPS_MPRA_MTR5_MASK 0x400u -#define AIPS_MPRA_MTR5_SHIFT 10 -#define AIPS_MPRA_MPL4_MASK 0x1000u -#define AIPS_MPRA_MPL4_SHIFT 12 -#define AIPS_MPRA_MTW4_MASK 0x2000u -#define AIPS_MPRA_MTW4_SHIFT 13 -#define AIPS_MPRA_MTR4_MASK 0x4000u -#define AIPS_MPRA_MTR4_SHIFT 14 -#define AIPS_MPRA_MPL3_MASK 0x10000u -#define AIPS_MPRA_MPL3_SHIFT 16 -#define AIPS_MPRA_MTW3_MASK 0x20000u -#define AIPS_MPRA_MTW3_SHIFT 17 -#define AIPS_MPRA_MTR3_MASK 0x40000u -#define AIPS_MPRA_MTR3_SHIFT 18 -#define AIPS_MPRA_MPL2_MASK 0x100000u -#define AIPS_MPRA_MPL2_SHIFT 20 -#define AIPS_MPRA_MTW2_MASK 0x200000u -#define AIPS_MPRA_MTW2_SHIFT 21 -#define AIPS_MPRA_MTR2_MASK 0x400000u -#define AIPS_MPRA_MTR2_SHIFT 22 -#define AIPS_MPRA_MPL1_MASK 0x1000000u -#define AIPS_MPRA_MPL1_SHIFT 24 -#define AIPS_MPRA_MTW1_MASK 0x2000000u -#define AIPS_MPRA_MTW1_SHIFT 25 -#define AIPS_MPRA_MTR1_MASK 0x4000000u -#define AIPS_MPRA_MTR1_SHIFT 26 -#define AIPS_MPRA_MPL0_MASK 0x10000000u -#define AIPS_MPRA_MPL0_SHIFT 28 -#define AIPS_MPRA_MTW0_MASK 0x20000000u -#define AIPS_MPRA_MTW0_SHIFT 29 -#define AIPS_MPRA_MTR0_MASK 0x40000000u -#define AIPS_MPRA_MTR0_SHIFT 30 -/* PACRA Bit Fields */ -#define AIPS_PACRA_TP7_MASK 0x1u -#define AIPS_PACRA_TP7_SHIFT 0 -#define AIPS_PACRA_WP7_MASK 0x2u -#define AIPS_PACRA_WP7_SHIFT 1 -#define AIPS_PACRA_SP7_MASK 0x4u -#define AIPS_PACRA_SP7_SHIFT 2 -#define AIPS_PACRA_TP6_MASK 0x10u -#define AIPS_PACRA_TP6_SHIFT 4 -#define AIPS_PACRA_WP6_MASK 0x20u -#define AIPS_PACRA_WP6_SHIFT 5 -#define AIPS_PACRA_SP6_MASK 0x40u -#define AIPS_PACRA_SP6_SHIFT 6 -#define AIPS_PACRA_TP5_MASK 0x100u -#define AIPS_PACRA_TP5_SHIFT 8 -#define AIPS_PACRA_WP5_MASK 0x200u -#define AIPS_PACRA_WP5_SHIFT 9 -#define AIPS_PACRA_SP5_MASK 0x400u -#define AIPS_PACRA_SP5_SHIFT 10 -#define AIPS_PACRA_TP4_MASK 0x1000u -#define AIPS_PACRA_TP4_SHIFT 12 -#define AIPS_PACRA_WP4_MASK 0x2000u -#define AIPS_PACRA_WP4_SHIFT 13 -#define AIPS_PACRA_SP4_MASK 0x4000u -#define AIPS_PACRA_SP4_SHIFT 14 -#define AIPS_PACRA_TP3_MASK 0x10000u -#define AIPS_PACRA_TP3_SHIFT 16 -#define AIPS_PACRA_WP3_MASK 0x20000u -#define AIPS_PACRA_WP3_SHIFT 17 -#define AIPS_PACRA_SP3_MASK 0x40000u -#define AIPS_PACRA_SP3_SHIFT 18 -#define AIPS_PACRA_TP2_MASK 0x100000u -#define AIPS_PACRA_TP2_SHIFT 20 -#define AIPS_PACRA_WP2_MASK 0x200000u -#define AIPS_PACRA_WP2_SHIFT 21 -#define AIPS_PACRA_SP2_MASK 0x400000u -#define AIPS_PACRA_SP2_SHIFT 22 -#define AIPS_PACRA_TP1_MASK 0x1000000u -#define AIPS_PACRA_TP1_SHIFT 24 -#define AIPS_PACRA_WP1_MASK 0x2000000u -#define AIPS_PACRA_WP1_SHIFT 25 -#define AIPS_PACRA_SP1_MASK 0x4000000u -#define AIPS_PACRA_SP1_SHIFT 26 -#define AIPS_PACRA_TP0_MASK 0x10000000u -#define AIPS_PACRA_TP0_SHIFT 28 -#define AIPS_PACRA_WP0_MASK 0x20000000u -#define AIPS_PACRA_WP0_SHIFT 29 -#define AIPS_PACRA_SP0_MASK 0x40000000u -#define AIPS_PACRA_SP0_SHIFT 30 -/* PACRB Bit Fields */ -#define AIPS_PACRB_TP7_MASK 0x1u -#define AIPS_PACRB_TP7_SHIFT 0 -#define AIPS_PACRB_WP7_MASK 0x2u -#define AIPS_PACRB_WP7_SHIFT 1 -#define AIPS_PACRB_SP7_MASK 0x4u -#define AIPS_PACRB_SP7_SHIFT 2 -#define AIPS_PACRB_TP6_MASK 0x10u -#define AIPS_PACRB_TP6_SHIFT 4 -#define AIPS_PACRB_WP6_MASK 0x20u -#define AIPS_PACRB_WP6_SHIFT 5 -#define AIPS_PACRB_SP6_MASK 0x40u -#define AIPS_PACRB_SP6_SHIFT 6 -#define AIPS_PACRB_TP5_MASK 0x100u -#define AIPS_PACRB_TP5_SHIFT 8 -#define AIPS_PACRB_WP5_MASK 0x200u -#define AIPS_PACRB_WP5_SHIFT 9 -#define AIPS_PACRB_SP5_MASK 0x400u -#define AIPS_PACRB_SP5_SHIFT 10 -#define AIPS_PACRB_TP4_MASK 0x1000u -#define AIPS_PACRB_TP4_SHIFT 12 -#define AIPS_PACRB_WP4_MASK 0x2000u -#define AIPS_PACRB_WP4_SHIFT 13 -#define AIPS_PACRB_SP4_MASK 0x4000u -#define AIPS_PACRB_SP4_SHIFT 14 -#define AIPS_PACRB_TP3_MASK 0x10000u -#define AIPS_PACRB_TP3_SHIFT 16 -#define AIPS_PACRB_WP3_MASK 0x20000u -#define AIPS_PACRB_WP3_SHIFT 17 -#define AIPS_PACRB_SP3_MASK 0x40000u -#define AIPS_PACRB_SP3_SHIFT 18 -#define AIPS_PACRB_TP2_MASK 0x100000u -#define AIPS_PACRB_TP2_SHIFT 20 -#define AIPS_PACRB_WP2_MASK 0x200000u -#define AIPS_PACRB_WP2_SHIFT 21 -#define AIPS_PACRB_SP2_MASK 0x400000u -#define AIPS_PACRB_SP2_SHIFT 22 -#define AIPS_PACRB_TP1_MASK 0x1000000u -#define AIPS_PACRB_TP1_SHIFT 24 -#define AIPS_PACRB_WP1_MASK 0x2000000u -#define AIPS_PACRB_WP1_SHIFT 25 -#define AIPS_PACRB_SP1_MASK 0x4000000u -#define AIPS_PACRB_SP1_SHIFT 26 -#define AIPS_PACRB_TP0_MASK 0x10000000u -#define AIPS_PACRB_TP0_SHIFT 28 -#define AIPS_PACRB_WP0_MASK 0x20000000u -#define AIPS_PACRB_WP0_SHIFT 29 -#define AIPS_PACRB_SP0_MASK 0x40000000u -#define AIPS_PACRB_SP0_SHIFT 30 -/* PACRC Bit Fields */ -#define AIPS_PACRC_TP7_MASK 0x1u -#define AIPS_PACRC_TP7_SHIFT 0 -#define AIPS_PACRC_WP7_MASK 0x2u -#define AIPS_PACRC_WP7_SHIFT 1 -#define AIPS_PACRC_SP7_MASK 0x4u -#define AIPS_PACRC_SP7_SHIFT 2 -#define AIPS_PACRC_TP6_MASK 0x10u -#define AIPS_PACRC_TP6_SHIFT 4 -#define AIPS_PACRC_WP6_MASK 0x20u -#define AIPS_PACRC_WP6_SHIFT 5 -#define AIPS_PACRC_SP6_MASK 0x40u -#define AIPS_PACRC_SP6_SHIFT 6 -#define AIPS_PACRC_TP5_MASK 0x100u -#define AIPS_PACRC_TP5_SHIFT 8 -#define AIPS_PACRC_WP5_MASK 0x200u -#define AIPS_PACRC_WP5_SHIFT 9 -#define AIPS_PACRC_SP5_MASK 0x400u -#define AIPS_PACRC_SP5_SHIFT 10 -#define AIPS_PACRC_TP4_MASK 0x1000u -#define AIPS_PACRC_TP4_SHIFT 12 -#define AIPS_PACRC_WP4_MASK 0x2000u -#define AIPS_PACRC_WP4_SHIFT 13 -#define AIPS_PACRC_SP4_MASK 0x4000u -#define AIPS_PACRC_SP4_SHIFT 14 -#define AIPS_PACRC_TP3_MASK 0x10000u -#define AIPS_PACRC_TP3_SHIFT 16 -#define AIPS_PACRC_WP3_MASK 0x20000u -#define AIPS_PACRC_WP3_SHIFT 17 -#define AIPS_PACRC_SP3_MASK 0x40000u -#define AIPS_PACRC_SP3_SHIFT 18 -#define AIPS_PACRC_TP2_MASK 0x100000u -#define AIPS_PACRC_TP2_SHIFT 20 -#define AIPS_PACRC_WP2_MASK 0x200000u -#define AIPS_PACRC_WP2_SHIFT 21 -#define AIPS_PACRC_SP2_MASK 0x400000u -#define AIPS_PACRC_SP2_SHIFT 22 -#define AIPS_PACRC_TP1_MASK 0x1000000u -#define AIPS_PACRC_TP1_SHIFT 24 -#define AIPS_PACRC_WP1_MASK 0x2000000u -#define AIPS_PACRC_WP1_SHIFT 25 -#define AIPS_PACRC_SP1_MASK 0x4000000u -#define AIPS_PACRC_SP1_SHIFT 26 -#define AIPS_PACRC_TP0_MASK 0x10000000u -#define AIPS_PACRC_TP0_SHIFT 28 -#define AIPS_PACRC_WP0_MASK 0x20000000u -#define AIPS_PACRC_WP0_SHIFT 29 -#define AIPS_PACRC_SP0_MASK 0x40000000u -#define AIPS_PACRC_SP0_SHIFT 30 -/* PACRD Bit Fields */ -#define AIPS_PACRD_TP7_MASK 0x1u -#define AIPS_PACRD_TP7_SHIFT 0 -#define AIPS_PACRD_WP7_MASK 0x2u -#define AIPS_PACRD_WP7_SHIFT 1 -#define AIPS_PACRD_SP7_MASK 0x4u -#define AIPS_PACRD_SP7_SHIFT 2 -#define AIPS_PACRD_TP6_MASK 0x10u -#define AIPS_PACRD_TP6_SHIFT 4 -#define AIPS_PACRD_WP6_MASK 0x20u -#define AIPS_PACRD_WP6_SHIFT 5 -#define AIPS_PACRD_SP6_MASK 0x40u -#define AIPS_PACRD_SP6_SHIFT 6 -#define AIPS_PACRD_TP5_MASK 0x100u -#define AIPS_PACRD_TP5_SHIFT 8 -#define AIPS_PACRD_WP5_MASK 0x200u -#define AIPS_PACRD_WP5_SHIFT 9 -#define AIPS_PACRD_SP5_MASK 0x400u -#define AIPS_PACRD_SP5_SHIFT 10 -#define AIPS_PACRD_TP4_MASK 0x1000u -#define AIPS_PACRD_TP4_SHIFT 12 -#define AIPS_PACRD_WP4_MASK 0x2000u -#define AIPS_PACRD_WP4_SHIFT 13 -#define AIPS_PACRD_SP4_MASK 0x4000u -#define AIPS_PACRD_SP4_SHIFT 14 -#define AIPS_PACRD_TP3_MASK 0x10000u -#define AIPS_PACRD_TP3_SHIFT 16 -#define AIPS_PACRD_WP3_MASK 0x20000u -#define AIPS_PACRD_WP3_SHIFT 17 -#define AIPS_PACRD_SP3_MASK 0x40000u -#define AIPS_PACRD_SP3_SHIFT 18 -#define AIPS_PACRD_TP2_MASK 0x100000u -#define AIPS_PACRD_TP2_SHIFT 20 -#define AIPS_PACRD_WP2_MASK 0x200000u -#define AIPS_PACRD_WP2_SHIFT 21 -#define AIPS_PACRD_SP2_MASK 0x400000u -#define AIPS_PACRD_SP2_SHIFT 22 -#define AIPS_PACRD_TP1_MASK 0x1000000u -#define AIPS_PACRD_TP1_SHIFT 24 -#define AIPS_PACRD_WP1_MASK 0x2000000u -#define AIPS_PACRD_WP1_SHIFT 25 -#define AIPS_PACRD_SP1_MASK 0x4000000u -#define AIPS_PACRD_SP1_SHIFT 26 -#define AIPS_PACRD_TP0_MASK 0x10000000u -#define AIPS_PACRD_TP0_SHIFT 28 -#define AIPS_PACRD_WP0_MASK 0x20000000u -#define AIPS_PACRD_WP0_SHIFT 29 -#define AIPS_PACRD_SP0_MASK 0x40000000u -#define AIPS_PACRD_SP0_SHIFT 30 -/* PACRE Bit Fields */ -#define AIPS_PACRE_TP7_MASK 0x1u -#define AIPS_PACRE_TP7_SHIFT 0 -#define AIPS_PACRE_WP7_MASK 0x2u -#define AIPS_PACRE_WP7_SHIFT 1 -#define AIPS_PACRE_SP7_MASK 0x4u -#define AIPS_PACRE_SP7_SHIFT 2 -#define AIPS_PACRE_TP6_MASK 0x10u -#define AIPS_PACRE_TP6_SHIFT 4 -#define AIPS_PACRE_WP6_MASK 0x20u -#define AIPS_PACRE_WP6_SHIFT 5 -#define AIPS_PACRE_SP6_MASK 0x40u -#define AIPS_PACRE_SP6_SHIFT 6 -#define AIPS_PACRE_TP5_MASK 0x100u -#define AIPS_PACRE_TP5_SHIFT 8 -#define AIPS_PACRE_WP5_MASK 0x200u -#define AIPS_PACRE_WP5_SHIFT 9 -#define AIPS_PACRE_SP5_MASK 0x400u -#define AIPS_PACRE_SP5_SHIFT 10 -#define AIPS_PACRE_TP4_MASK 0x1000u -#define AIPS_PACRE_TP4_SHIFT 12 -#define AIPS_PACRE_WP4_MASK 0x2000u -#define AIPS_PACRE_WP4_SHIFT 13 -#define AIPS_PACRE_SP4_MASK 0x4000u -#define AIPS_PACRE_SP4_SHIFT 14 -#define AIPS_PACRE_TP3_MASK 0x10000u -#define AIPS_PACRE_TP3_SHIFT 16 -#define AIPS_PACRE_WP3_MASK 0x20000u -#define AIPS_PACRE_WP3_SHIFT 17 -#define AIPS_PACRE_SP3_MASK 0x40000u -#define AIPS_PACRE_SP3_SHIFT 18 -#define AIPS_PACRE_TP2_MASK 0x100000u -#define AIPS_PACRE_TP2_SHIFT 20 -#define AIPS_PACRE_WP2_MASK 0x200000u -#define AIPS_PACRE_WP2_SHIFT 21 -#define AIPS_PACRE_SP2_MASK 0x400000u -#define AIPS_PACRE_SP2_SHIFT 22 -#define AIPS_PACRE_TP1_MASK 0x1000000u -#define AIPS_PACRE_TP1_SHIFT 24 -#define AIPS_PACRE_WP1_MASK 0x2000000u -#define AIPS_PACRE_WP1_SHIFT 25 -#define AIPS_PACRE_SP1_MASK 0x4000000u -#define AIPS_PACRE_SP1_SHIFT 26 -#define AIPS_PACRE_TP0_MASK 0x10000000u -#define AIPS_PACRE_TP0_SHIFT 28 -#define AIPS_PACRE_WP0_MASK 0x20000000u -#define AIPS_PACRE_WP0_SHIFT 29 -#define AIPS_PACRE_SP0_MASK 0x40000000u -#define AIPS_PACRE_SP0_SHIFT 30 -/* PACRF Bit Fields */ -#define AIPS_PACRF_TP7_MASK 0x1u -#define AIPS_PACRF_TP7_SHIFT 0 -#define AIPS_PACRF_WP7_MASK 0x2u -#define AIPS_PACRF_WP7_SHIFT 1 -#define AIPS_PACRF_SP7_MASK 0x4u -#define AIPS_PACRF_SP7_SHIFT 2 -#define AIPS_PACRF_TP6_MASK 0x10u -#define AIPS_PACRF_TP6_SHIFT 4 -#define AIPS_PACRF_WP6_MASK 0x20u -#define AIPS_PACRF_WP6_SHIFT 5 -#define AIPS_PACRF_SP6_MASK 0x40u -#define AIPS_PACRF_SP6_SHIFT 6 -#define AIPS_PACRF_TP5_MASK 0x100u -#define AIPS_PACRF_TP5_SHIFT 8 -#define AIPS_PACRF_WP5_MASK 0x200u -#define AIPS_PACRF_WP5_SHIFT 9 -#define AIPS_PACRF_SP5_MASK 0x400u -#define AIPS_PACRF_SP5_SHIFT 10 -#define AIPS_PACRF_TP4_MASK 0x1000u -#define AIPS_PACRF_TP4_SHIFT 12 -#define AIPS_PACRF_WP4_MASK 0x2000u -#define AIPS_PACRF_WP4_SHIFT 13 -#define AIPS_PACRF_SP4_MASK 0x4000u -#define AIPS_PACRF_SP4_SHIFT 14 -#define AIPS_PACRF_TP3_MASK 0x10000u -#define AIPS_PACRF_TP3_SHIFT 16 -#define AIPS_PACRF_WP3_MASK 0x20000u -#define AIPS_PACRF_WP3_SHIFT 17 -#define AIPS_PACRF_SP3_MASK 0x40000u -#define AIPS_PACRF_SP3_SHIFT 18 -#define AIPS_PACRF_TP2_MASK 0x100000u -#define AIPS_PACRF_TP2_SHIFT 20 -#define AIPS_PACRF_WP2_MASK 0x200000u -#define AIPS_PACRF_WP2_SHIFT 21 -#define AIPS_PACRF_SP2_MASK 0x400000u -#define AIPS_PACRF_SP2_SHIFT 22 -#define AIPS_PACRF_TP1_MASK 0x1000000u -#define AIPS_PACRF_TP1_SHIFT 24 -#define AIPS_PACRF_WP1_MASK 0x2000000u -#define AIPS_PACRF_WP1_SHIFT 25 -#define AIPS_PACRF_SP1_MASK 0x4000000u -#define AIPS_PACRF_SP1_SHIFT 26 -#define AIPS_PACRF_TP0_MASK 0x10000000u -#define AIPS_PACRF_TP0_SHIFT 28 -#define AIPS_PACRF_WP0_MASK 0x20000000u -#define AIPS_PACRF_WP0_SHIFT 29 -#define AIPS_PACRF_SP0_MASK 0x40000000u -#define AIPS_PACRF_SP0_SHIFT 30 -/* PACRG Bit Fields */ -#define AIPS_PACRG_TP7_MASK 0x1u -#define AIPS_PACRG_TP7_SHIFT 0 -#define AIPS_PACRG_WP7_MASK 0x2u -#define AIPS_PACRG_WP7_SHIFT 1 -#define AIPS_PACRG_SP7_MASK 0x4u -#define AIPS_PACRG_SP7_SHIFT 2 -#define AIPS_PACRG_TP6_MASK 0x10u -#define AIPS_PACRG_TP6_SHIFT 4 -#define AIPS_PACRG_WP6_MASK 0x20u -#define AIPS_PACRG_WP6_SHIFT 5 -#define AIPS_PACRG_SP6_MASK 0x40u -#define AIPS_PACRG_SP6_SHIFT 6 -#define AIPS_PACRG_TP5_MASK 0x100u -#define AIPS_PACRG_TP5_SHIFT 8 -#define AIPS_PACRG_WP5_MASK 0x200u -#define AIPS_PACRG_WP5_SHIFT 9 -#define AIPS_PACRG_SP5_MASK 0x400u -#define AIPS_PACRG_SP5_SHIFT 10 -#define AIPS_PACRG_TP4_MASK 0x1000u -#define AIPS_PACRG_TP4_SHIFT 12 -#define AIPS_PACRG_WP4_MASK 0x2000u -#define AIPS_PACRG_WP4_SHIFT 13 -#define AIPS_PACRG_SP4_MASK 0x4000u -#define AIPS_PACRG_SP4_SHIFT 14 -#define AIPS_PACRG_TP3_MASK 0x10000u -#define AIPS_PACRG_TP3_SHIFT 16 -#define AIPS_PACRG_WP3_MASK 0x20000u -#define AIPS_PACRG_WP3_SHIFT 17 -#define AIPS_PACRG_SP3_MASK 0x40000u -#define AIPS_PACRG_SP3_SHIFT 18 -#define AIPS_PACRG_TP2_MASK 0x100000u -#define AIPS_PACRG_TP2_SHIFT 20 -#define AIPS_PACRG_WP2_MASK 0x200000u -#define AIPS_PACRG_WP2_SHIFT 21 -#define AIPS_PACRG_SP2_MASK 0x400000u -#define AIPS_PACRG_SP2_SHIFT 22 -#define AIPS_PACRG_TP1_MASK 0x1000000u -#define AIPS_PACRG_TP1_SHIFT 24 -#define AIPS_PACRG_WP1_MASK 0x2000000u -#define AIPS_PACRG_WP1_SHIFT 25 -#define AIPS_PACRG_SP1_MASK 0x4000000u -#define AIPS_PACRG_SP1_SHIFT 26 -#define AIPS_PACRG_TP0_MASK 0x10000000u -#define AIPS_PACRG_TP0_SHIFT 28 -#define AIPS_PACRG_WP0_MASK 0x20000000u -#define AIPS_PACRG_WP0_SHIFT 29 -#define AIPS_PACRG_SP0_MASK 0x40000000u -#define AIPS_PACRG_SP0_SHIFT 30 -/* PACRH Bit Fields */ -#define AIPS_PACRH_TP7_MASK 0x1u -#define AIPS_PACRH_TP7_SHIFT 0 -#define AIPS_PACRH_WP7_MASK 0x2u -#define AIPS_PACRH_WP7_SHIFT 1 -#define AIPS_PACRH_SP7_MASK 0x4u -#define AIPS_PACRH_SP7_SHIFT 2 -#define AIPS_PACRH_TP6_MASK 0x10u -#define AIPS_PACRH_TP6_SHIFT 4 -#define AIPS_PACRH_WP6_MASK 0x20u -#define AIPS_PACRH_WP6_SHIFT 5 -#define AIPS_PACRH_SP6_MASK 0x40u -#define AIPS_PACRH_SP6_SHIFT 6 -#define AIPS_PACRH_TP5_MASK 0x100u -#define AIPS_PACRH_TP5_SHIFT 8 -#define AIPS_PACRH_WP5_MASK 0x200u -#define AIPS_PACRH_WP5_SHIFT 9 -#define AIPS_PACRH_SP5_MASK 0x400u -#define AIPS_PACRH_SP5_SHIFT 10 -#define AIPS_PACRH_TP4_MASK 0x1000u -#define AIPS_PACRH_TP4_SHIFT 12 -#define AIPS_PACRH_WP4_MASK 0x2000u -#define AIPS_PACRH_WP4_SHIFT 13 -#define AIPS_PACRH_SP4_MASK 0x4000u -#define AIPS_PACRH_SP4_SHIFT 14 -#define AIPS_PACRH_TP3_MASK 0x10000u -#define AIPS_PACRH_TP3_SHIFT 16 -#define AIPS_PACRH_WP3_MASK 0x20000u -#define AIPS_PACRH_WP3_SHIFT 17 -#define AIPS_PACRH_SP3_MASK 0x40000u -#define AIPS_PACRH_SP3_SHIFT 18 -#define AIPS_PACRH_TP2_MASK 0x100000u -#define AIPS_PACRH_TP2_SHIFT 20 -#define AIPS_PACRH_WP2_MASK 0x200000u -#define AIPS_PACRH_WP2_SHIFT 21 -#define AIPS_PACRH_SP2_MASK 0x400000u -#define AIPS_PACRH_SP2_SHIFT 22 -#define AIPS_PACRH_TP1_MASK 0x1000000u -#define AIPS_PACRH_TP1_SHIFT 24 -#define AIPS_PACRH_WP1_MASK 0x2000000u -#define AIPS_PACRH_WP1_SHIFT 25 -#define AIPS_PACRH_SP1_MASK 0x4000000u -#define AIPS_PACRH_SP1_SHIFT 26 -#define AIPS_PACRH_TP0_MASK 0x10000000u -#define AIPS_PACRH_TP0_SHIFT 28 -#define AIPS_PACRH_WP0_MASK 0x20000000u -#define AIPS_PACRH_WP0_SHIFT 29 -#define AIPS_PACRH_SP0_MASK 0x40000000u -#define AIPS_PACRH_SP0_SHIFT 30 -/* PACRI Bit Fields */ -#define AIPS_PACRI_TP7_MASK 0x1u -#define AIPS_PACRI_TP7_SHIFT 0 -#define AIPS_PACRI_WP7_MASK 0x2u -#define AIPS_PACRI_WP7_SHIFT 1 -#define AIPS_PACRI_SP7_MASK 0x4u -#define AIPS_PACRI_SP7_SHIFT 2 -#define AIPS_PACRI_TP6_MASK 0x10u -#define AIPS_PACRI_TP6_SHIFT 4 -#define AIPS_PACRI_WP6_MASK 0x20u -#define AIPS_PACRI_WP6_SHIFT 5 -#define AIPS_PACRI_SP6_MASK 0x40u -#define AIPS_PACRI_SP6_SHIFT 6 -#define AIPS_PACRI_TP5_MASK 0x100u -#define AIPS_PACRI_TP5_SHIFT 8 -#define AIPS_PACRI_WP5_MASK 0x200u -#define AIPS_PACRI_WP5_SHIFT 9 -#define AIPS_PACRI_SP5_MASK 0x400u -#define AIPS_PACRI_SP5_SHIFT 10 -#define AIPS_PACRI_TP4_MASK 0x1000u -#define AIPS_PACRI_TP4_SHIFT 12 -#define AIPS_PACRI_WP4_MASK 0x2000u -#define AIPS_PACRI_WP4_SHIFT 13 -#define AIPS_PACRI_SP4_MASK 0x4000u -#define AIPS_PACRI_SP4_SHIFT 14 -#define AIPS_PACRI_TP3_MASK 0x10000u -#define AIPS_PACRI_TP3_SHIFT 16 -#define AIPS_PACRI_WP3_MASK 0x20000u -#define AIPS_PACRI_WP3_SHIFT 17 -#define AIPS_PACRI_SP3_MASK 0x40000u -#define AIPS_PACRI_SP3_SHIFT 18 -#define AIPS_PACRI_TP2_MASK 0x100000u -#define AIPS_PACRI_TP2_SHIFT 20 -#define AIPS_PACRI_WP2_MASK 0x200000u -#define AIPS_PACRI_WP2_SHIFT 21 -#define AIPS_PACRI_SP2_MASK 0x400000u -#define AIPS_PACRI_SP2_SHIFT 22 -#define AIPS_PACRI_TP1_MASK 0x1000000u -#define AIPS_PACRI_TP1_SHIFT 24 -#define AIPS_PACRI_WP1_MASK 0x2000000u -#define AIPS_PACRI_WP1_SHIFT 25 -#define AIPS_PACRI_SP1_MASK 0x4000000u -#define AIPS_PACRI_SP1_SHIFT 26 -#define AIPS_PACRI_TP0_MASK 0x10000000u -#define AIPS_PACRI_TP0_SHIFT 28 -#define AIPS_PACRI_WP0_MASK 0x20000000u -#define AIPS_PACRI_WP0_SHIFT 29 -#define AIPS_PACRI_SP0_MASK 0x40000000u -#define AIPS_PACRI_SP0_SHIFT 30 -/* PACRJ Bit Fields */ -#define AIPS_PACRJ_TP7_MASK 0x1u -#define AIPS_PACRJ_TP7_SHIFT 0 -#define AIPS_PACRJ_WP7_MASK 0x2u -#define AIPS_PACRJ_WP7_SHIFT 1 -#define AIPS_PACRJ_SP7_MASK 0x4u -#define AIPS_PACRJ_SP7_SHIFT 2 -#define AIPS_PACRJ_TP6_MASK 0x10u -#define AIPS_PACRJ_TP6_SHIFT 4 -#define AIPS_PACRJ_WP6_MASK 0x20u -#define AIPS_PACRJ_WP6_SHIFT 5 -#define AIPS_PACRJ_SP6_MASK 0x40u -#define AIPS_PACRJ_SP6_SHIFT 6 -#define AIPS_PACRJ_TP5_MASK 0x100u -#define AIPS_PACRJ_TP5_SHIFT 8 -#define AIPS_PACRJ_WP5_MASK 0x200u -#define AIPS_PACRJ_WP5_SHIFT 9 -#define AIPS_PACRJ_SP5_MASK 0x400u -#define AIPS_PACRJ_SP5_SHIFT 10 -#define AIPS_PACRJ_TP4_MASK 0x1000u -#define AIPS_PACRJ_TP4_SHIFT 12 -#define AIPS_PACRJ_WP4_MASK 0x2000u -#define AIPS_PACRJ_WP4_SHIFT 13 -#define AIPS_PACRJ_SP4_MASK 0x4000u -#define AIPS_PACRJ_SP4_SHIFT 14 -#define AIPS_PACRJ_TP3_MASK 0x10000u -#define AIPS_PACRJ_TP3_SHIFT 16 -#define AIPS_PACRJ_WP3_MASK 0x20000u -#define AIPS_PACRJ_WP3_SHIFT 17 -#define AIPS_PACRJ_SP3_MASK 0x40000u -#define AIPS_PACRJ_SP3_SHIFT 18 -#define AIPS_PACRJ_TP2_MASK 0x100000u -#define AIPS_PACRJ_TP2_SHIFT 20 -#define AIPS_PACRJ_WP2_MASK 0x200000u -#define AIPS_PACRJ_WP2_SHIFT 21 -#define AIPS_PACRJ_SP2_MASK 0x400000u -#define AIPS_PACRJ_SP2_SHIFT 22 -#define AIPS_PACRJ_TP1_MASK 0x1000000u -#define AIPS_PACRJ_TP1_SHIFT 24 -#define AIPS_PACRJ_WP1_MASK 0x2000000u -#define AIPS_PACRJ_WP1_SHIFT 25 -#define AIPS_PACRJ_SP1_MASK 0x4000000u -#define AIPS_PACRJ_SP1_SHIFT 26 -#define AIPS_PACRJ_TP0_MASK 0x10000000u -#define AIPS_PACRJ_TP0_SHIFT 28 -#define AIPS_PACRJ_WP0_MASK 0x20000000u -#define AIPS_PACRJ_WP0_SHIFT 29 -#define AIPS_PACRJ_SP0_MASK 0x40000000u -#define AIPS_PACRJ_SP0_SHIFT 30 -/* PACRK Bit Fields */ -#define AIPS_PACRK_TP7_MASK 0x1u -#define AIPS_PACRK_TP7_SHIFT 0 -#define AIPS_PACRK_WP7_MASK 0x2u -#define AIPS_PACRK_WP7_SHIFT 1 -#define AIPS_PACRK_SP7_MASK 0x4u -#define AIPS_PACRK_SP7_SHIFT 2 -#define AIPS_PACRK_TP6_MASK 0x10u -#define AIPS_PACRK_TP6_SHIFT 4 -#define AIPS_PACRK_WP6_MASK 0x20u -#define AIPS_PACRK_WP6_SHIFT 5 -#define AIPS_PACRK_SP6_MASK 0x40u -#define AIPS_PACRK_SP6_SHIFT 6 -#define AIPS_PACRK_TP5_MASK 0x100u -#define AIPS_PACRK_TP5_SHIFT 8 -#define AIPS_PACRK_WP5_MASK 0x200u -#define AIPS_PACRK_WP5_SHIFT 9 -#define AIPS_PACRK_SP5_MASK 0x400u -#define AIPS_PACRK_SP5_SHIFT 10 -#define AIPS_PACRK_TP4_MASK 0x1000u -#define AIPS_PACRK_TP4_SHIFT 12 -#define AIPS_PACRK_WP4_MASK 0x2000u -#define AIPS_PACRK_WP4_SHIFT 13 -#define AIPS_PACRK_SP4_MASK 0x4000u -#define AIPS_PACRK_SP4_SHIFT 14 -#define AIPS_PACRK_TP3_MASK 0x10000u -#define AIPS_PACRK_TP3_SHIFT 16 -#define AIPS_PACRK_WP3_MASK 0x20000u -#define AIPS_PACRK_WP3_SHIFT 17 -#define AIPS_PACRK_SP3_MASK 0x40000u -#define AIPS_PACRK_SP3_SHIFT 18 -#define AIPS_PACRK_TP2_MASK 0x100000u -#define AIPS_PACRK_TP2_SHIFT 20 -#define AIPS_PACRK_WP2_MASK 0x200000u -#define AIPS_PACRK_WP2_SHIFT 21 -#define AIPS_PACRK_SP2_MASK 0x400000u -#define AIPS_PACRK_SP2_SHIFT 22 -#define AIPS_PACRK_TP1_MASK 0x1000000u -#define AIPS_PACRK_TP1_SHIFT 24 -#define AIPS_PACRK_WP1_MASK 0x2000000u -#define AIPS_PACRK_WP1_SHIFT 25 -#define AIPS_PACRK_SP1_MASK 0x4000000u -#define AIPS_PACRK_SP1_SHIFT 26 -#define AIPS_PACRK_TP0_MASK 0x10000000u -#define AIPS_PACRK_TP0_SHIFT 28 -#define AIPS_PACRK_WP0_MASK 0x20000000u -#define AIPS_PACRK_WP0_SHIFT 29 -#define AIPS_PACRK_SP0_MASK 0x40000000u -#define AIPS_PACRK_SP0_SHIFT 30 -/* PACRL Bit Fields */ -#define AIPS_PACRL_TP7_MASK 0x1u -#define AIPS_PACRL_TP7_SHIFT 0 -#define AIPS_PACRL_WP7_MASK 0x2u -#define AIPS_PACRL_WP7_SHIFT 1 -#define AIPS_PACRL_SP7_MASK 0x4u -#define AIPS_PACRL_SP7_SHIFT 2 -#define AIPS_PACRL_TP6_MASK 0x10u -#define AIPS_PACRL_TP6_SHIFT 4 -#define AIPS_PACRL_WP6_MASK 0x20u -#define AIPS_PACRL_WP6_SHIFT 5 -#define AIPS_PACRL_SP6_MASK 0x40u -#define AIPS_PACRL_SP6_SHIFT 6 -#define AIPS_PACRL_TP5_MASK 0x100u -#define AIPS_PACRL_TP5_SHIFT 8 -#define AIPS_PACRL_WP5_MASK 0x200u -#define AIPS_PACRL_WP5_SHIFT 9 -#define AIPS_PACRL_SP5_MASK 0x400u -#define AIPS_PACRL_SP5_SHIFT 10 -#define AIPS_PACRL_TP4_MASK 0x1000u -#define AIPS_PACRL_TP4_SHIFT 12 -#define AIPS_PACRL_WP4_MASK 0x2000u -#define AIPS_PACRL_WP4_SHIFT 13 -#define AIPS_PACRL_SP4_MASK 0x4000u -#define AIPS_PACRL_SP4_SHIFT 14 -#define AIPS_PACRL_TP3_MASK 0x10000u -#define AIPS_PACRL_TP3_SHIFT 16 -#define AIPS_PACRL_WP3_MASK 0x20000u -#define AIPS_PACRL_WP3_SHIFT 17 -#define AIPS_PACRL_SP3_MASK 0x40000u -#define AIPS_PACRL_SP3_SHIFT 18 -#define AIPS_PACRL_TP2_MASK 0x100000u -#define AIPS_PACRL_TP2_SHIFT 20 -#define AIPS_PACRL_WP2_MASK 0x200000u -#define AIPS_PACRL_WP2_SHIFT 21 -#define AIPS_PACRL_SP2_MASK 0x400000u -#define AIPS_PACRL_SP2_SHIFT 22 -#define AIPS_PACRL_TP1_MASK 0x1000000u -#define AIPS_PACRL_TP1_SHIFT 24 -#define AIPS_PACRL_WP1_MASK 0x2000000u -#define AIPS_PACRL_WP1_SHIFT 25 -#define AIPS_PACRL_SP1_MASK 0x4000000u -#define AIPS_PACRL_SP1_SHIFT 26 -#define AIPS_PACRL_TP0_MASK 0x10000000u -#define AIPS_PACRL_TP0_SHIFT 28 -#define AIPS_PACRL_WP0_MASK 0x20000000u -#define AIPS_PACRL_WP0_SHIFT 29 -#define AIPS_PACRL_SP0_MASK 0x40000000u -#define AIPS_PACRL_SP0_SHIFT 30 -/* PACRM Bit Fields */ -#define AIPS_PACRM_TP7_MASK 0x1u -#define AIPS_PACRM_TP7_SHIFT 0 -#define AIPS_PACRM_WP7_MASK 0x2u -#define AIPS_PACRM_WP7_SHIFT 1 -#define AIPS_PACRM_SP7_MASK 0x4u -#define AIPS_PACRM_SP7_SHIFT 2 -#define AIPS_PACRM_TP6_MASK 0x10u -#define AIPS_PACRM_TP6_SHIFT 4 -#define AIPS_PACRM_WP6_MASK 0x20u -#define AIPS_PACRM_WP6_SHIFT 5 -#define AIPS_PACRM_SP6_MASK 0x40u -#define AIPS_PACRM_SP6_SHIFT 6 -#define AIPS_PACRM_TP5_MASK 0x100u -#define AIPS_PACRM_TP5_SHIFT 8 -#define AIPS_PACRM_WP5_MASK 0x200u -#define AIPS_PACRM_WP5_SHIFT 9 -#define AIPS_PACRM_SP5_MASK 0x400u -#define AIPS_PACRM_SP5_SHIFT 10 -#define AIPS_PACRM_TP4_MASK 0x1000u -#define AIPS_PACRM_TP4_SHIFT 12 -#define AIPS_PACRM_WP4_MASK 0x2000u -#define AIPS_PACRM_WP4_SHIFT 13 -#define AIPS_PACRM_SP4_MASK 0x4000u -#define AIPS_PACRM_SP4_SHIFT 14 -#define AIPS_PACRM_TP3_MASK 0x10000u -#define AIPS_PACRM_TP3_SHIFT 16 -#define AIPS_PACRM_WP3_MASK 0x20000u -#define AIPS_PACRM_WP3_SHIFT 17 -#define AIPS_PACRM_SP3_MASK 0x40000u -#define AIPS_PACRM_SP3_SHIFT 18 -#define AIPS_PACRM_TP2_MASK 0x100000u -#define AIPS_PACRM_TP2_SHIFT 20 -#define AIPS_PACRM_WP2_MASK 0x200000u -#define AIPS_PACRM_WP2_SHIFT 21 -#define AIPS_PACRM_SP2_MASK 0x400000u -#define AIPS_PACRM_SP2_SHIFT 22 -#define AIPS_PACRM_TP1_MASK 0x1000000u -#define AIPS_PACRM_TP1_SHIFT 24 -#define AIPS_PACRM_WP1_MASK 0x2000000u -#define AIPS_PACRM_WP1_SHIFT 25 -#define AIPS_PACRM_SP1_MASK 0x4000000u -#define AIPS_PACRM_SP1_SHIFT 26 -#define AIPS_PACRM_TP0_MASK 0x10000000u -#define AIPS_PACRM_TP0_SHIFT 28 -#define AIPS_PACRM_WP0_MASK 0x20000000u -#define AIPS_PACRM_WP0_SHIFT 29 -#define AIPS_PACRM_SP0_MASK 0x40000000u -#define AIPS_PACRM_SP0_SHIFT 30 -/* PACRN Bit Fields */ -#define AIPS_PACRN_TP7_MASK 0x1u -#define AIPS_PACRN_TP7_SHIFT 0 -#define AIPS_PACRN_WP7_MASK 0x2u -#define AIPS_PACRN_WP7_SHIFT 1 -#define AIPS_PACRN_SP7_MASK 0x4u -#define AIPS_PACRN_SP7_SHIFT 2 -#define AIPS_PACRN_TP6_MASK 0x10u -#define AIPS_PACRN_TP6_SHIFT 4 -#define AIPS_PACRN_WP6_MASK 0x20u -#define AIPS_PACRN_WP6_SHIFT 5 -#define AIPS_PACRN_SP6_MASK 0x40u -#define AIPS_PACRN_SP6_SHIFT 6 -#define AIPS_PACRN_TP5_MASK 0x100u -#define AIPS_PACRN_TP5_SHIFT 8 -#define AIPS_PACRN_WP5_MASK 0x200u -#define AIPS_PACRN_WP5_SHIFT 9 -#define AIPS_PACRN_SP5_MASK 0x400u -#define AIPS_PACRN_SP5_SHIFT 10 -#define AIPS_PACRN_TP4_MASK 0x1000u -#define AIPS_PACRN_TP4_SHIFT 12 -#define AIPS_PACRN_WP4_MASK 0x2000u -#define AIPS_PACRN_WP4_SHIFT 13 -#define AIPS_PACRN_SP4_MASK 0x4000u -#define AIPS_PACRN_SP4_SHIFT 14 -#define AIPS_PACRN_TP3_MASK 0x10000u -#define AIPS_PACRN_TP3_SHIFT 16 -#define AIPS_PACRN_WP3_MASK 0x20000u -#define AIPS_PACRN_WP3_SHIFT 17 -#define AIPS_PACRN_SP3_MASK 0x40000u -#define AIPS_PACRN_SP3_SHIFT 18 -#define AIPS_PACRN_TP2_MASK 0x100000u -#define AIPS_PACRN_TP2_SHIFT 20 -#define AIPS_PACRN_WP2_MASK 0x200000u -#define AIPS_PACRN_WP2_SHIFT 21 -#define AIPS_PACRN_SP2_MASK 0x400000u -#define AIPS_PACRN_SP2_SHIFT 22 -#define AIPS_PACRN_TP1_MASK 0x1000000u -#define AIPS_PACRN_TP1_SHIFT 24 -#define AIPS_PACRN_WP1_MASK 0x2000000u -#define AIPS_PACRN_WP1_SHIFT 25 -#define AIPS_PACRN_SP1_MASK 0x4000000u -#define AIPS_PACRN_SP1_SHIFT 26 -#define AIPS_PACRN_TP0_MASK 0x10000000u -#define AIPS_PACRN_TP0_SHIFT 28 -#define AIPS_PACRN_WP0_MASK 0x20000000u -#define AIPS_PACRN_WP0_SHIFT 29 -#define AIPS_PACRN_SP0_MASK 0x40000000u -#define AIPS_PACRN_SP0_SHIFT 30 -/* PACRO Bit Fields */ -#define AIPS_PACRO_TP7_MASK 0x1u -#define AIPS_PACRO_TP7_SHIFT 0 -#define AIPS_PACRO_WP7_MASK 0x2u -#define AIPS_PACRO_WP7_SHIFT 1 -#define AIPS_PACRO_SP7_MASK 0x4u -#define AIPS_PACRO_SP7_SHIFT 2 -#define AIPS_PACRO_TP6_MASK 0x10u -#define AIPS_PACRO_TP6_SHIFT 4 -#define AIPS_PACRO_WP6_MASK 0x20u -#define AIPS_PACRO_WP6_SHIFT 5 -#define AIPS_PACRO_SP6_MASK 0x40u -#define AIPS_PACRO_SP6_SHIFT 6 -#define AIPS_PACRO_TP5_MASK 0x100u -#define AIPS_PACRO_TP5_SHIFT 8 -#define AIPS_PACRO_WP5_MASK 0x200u -#define AIPS_PACRO_WP5_SHIFT 9 -#define AIPS_PACRO_SP5_MASK 0x400u -#define AIPS_PACRO_SP5_SHIFT 10 -#define AIPS_PACRO_TP4_MASK 0x1000u -#define AIPS_PACRO_TP4_SHIFT 12 -#define AIPS_PACRO_WP4_MASK 0x2000u -#define AIPS_PACRO_WP4_SHIFT 13 -#define AIPS_PACRO_SP4_MASK 0x4000u -#define AIPS_PACRO_SP4_SHIFT 14 -#define AIPS_PACRO_TP3_MASK 0x10000u -#define AIPS_PACRO_TP3_SHIFT 16 -#define AIPS_PACRO_WP3_MASK 0x20000u -#define AIPS_PACRO_WP3_SHIFT 17 -#define AIPS_PACRO_SP3_MASK 0x40000u -#define AIPS_PACRO_SP3_SHIFT 18 -#define AIPS_PACRO_TP2_MASK 0x100000u -#define AIPS_PACRO_TP2_SHIFT 20 -#define AIPS_PACRO_WP2_MASK 0x200000u -#define AIPS_PACRO_WP2_SHIFT 21 -#define AIPS_PACRO_SP2_MASK 0x400000u -#define AIPS_PACRO_SP2_SHIFT 22 -#define AIPS_PACRO_TP1_MASK 0x1000000u -#define AIPS_PACRO_TP1_SHIFT 24 -#define AIPS_PACRO_WP1_MASK 0x2000000u -#define AIPS_PACRO_WP1_SHIFT 25 -#define AIPS_PACRO_SP1_MASK 0x4000000u -#define AIPS_PACRO_SP1_SHIFT 26 -#define AIPS_PACRO_TP0_MASK 0x10000000u -#define AIPS_PACRO_TP0_SHIFT 28 -#define AIPS_PACRO_WP0_MASK 0x20000000u -#define AIPS_PACRO_WP0_SHIFT 29 -#define AIPS_PACRO_SP0_MASK 0x40000000u -#define AIPS_PACRO_SP0_SHIFT 30 -/* PACRP Bit Fields */ -#define AIPS_PACRP_TP7_MASK 0x1u -#define AIPS_PACRP_TP7_SHIFT 0 -#define AIPS_PACRP_WP7_MASK 0x2u -#define AIPS_PACRP_WP7_SHIFT 1 -#define AIPS_PACRP_SP7_MASK 0x4u -#define AIPS_PACRP_SP7_SHIFT 2 -#define AIPS_PACRP_TP6_MASK 0x10u -#define AIPS_PACRP_TP6_SHIFT 4 -#define AIPS_PACRP_WP6_MASK 0x20u -#define AIPS_PACRP_WP6_SHIFT 5 -#define AIPS_PACRP_SP6_MASK 0x40u -#define AIPS_PACRP_SP6_SHIFT 6 -#define AIPS_PACRP_TP5_MASK 0x100u -#define AIPS_PACRP_TP5_SHIFT 8 -#define AIPS_PACRP_WP5_MASK 0x200u -#define AIPS_PACRP_WP5_SHIFT 9 -#define AIPS_PACRP_SP5_MASK 0x400u -#define AIPS_PACRP_SP5_SHIFT 10 -#define AIPS_PACRP_TP4_MASK 0x1000u -#define AIPS_PACRP_TP4_SHIFT 12 -#define AIPS_PACRP_WP4_MASK 0x2000u -#define AIPS_PACRP_WP4_SHIFT 13 -#define AIPS_PACRP_SP4_MASK 0x4000u -#define AIPS_PACRP_SP4_SHIFT 14 -#define AIPS_PACRP_TP3_MASK 0x10000u -#define AIPS_PACRP_TP3_SHIFT 16 -#define AIPS_PACRP_WP3_MASK 0x20000u -#define AIPS_PACRP_WP3_SHIFT 17 -#define AIPS_PACRP_SP3_MASK 0x40000u -#define AIPS_PACRP_SP3_SHIFT 18 -#define AIPS_PACRP_TP2_MASK 0x100000u -#define AIPS_PACRP_TP2_SHIFT 20 -#define AIPS_PACRP_WP2_MASK 0x200000u -#define AIPS_PACRP_WP2_SHIFT 21 -#define AIPS_PACRP_SP2_MASK 0x400000u -#define AIPS_PACRP_SP2_SHIFT 22 -#define AIPS_PACRP_TP1_MASK 0x1000000u -#define AIPS_PACRP_TP1_SHIFT 24 -#define AIPS_PACRP_WP1_MASK 0x2000000u -#define AIPS_PACRP_WP1_SHIFT 25 -#define AIPS_PACRP_SP1_MASK 0x4000000u -#define AIPS_PACRP_SP1_SHIFT 26 -#define AIPS_PACRP_TP0_MASK 0x10000000u -#define AIPS_PACRP_TP0_SHIFT 28 -#define AIPS_PACRP_WP0_MASK 0x20000000u -#define AIPS_PACRP_WP0_SHIFT 29 -#define AIPS_PACRP_SP0_MASK 0x40000000u -#define AIPS_PACRP_SP0_SHIFT 30 +/*! @name MPRA - Master Privilege Register A */ +#define AIPS_MPRA_MPL5_MASK (0x100U) +#define AIPS_MPRA_MPL5_SHIFT (8U) +#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) +#define AIPS_MPRA_MTW5_MASK (0x200U) +#define AIPS_MPRA_MTW5_SHIFT (9U) +#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) +#define AIPS_MPRA_MTR5_MASK (0x400U) +#define AIPS_MPRA_MTR5_SHIFT (10U) +#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) +#define AIPS_MPRA_MPL4_MASK (0x1000U) +#define AIPS_MPRA_MPL4_SHIFT (12U) +#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) +#define AIPS_MPRA_MTW4_MASK (0x2000U) +#define AIPS_MPRA_MTW4_SHIFT (13U) +#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) +#define AIPS_MPRA_MTR4_MASK (0x4000U) +#define AIPS_MPRA_MTR4_SHIFT (14U) +#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) +#define AIPS_MPRA_MPL3_MASK (0x10000U) +#define AIPS_MPRA_MPL3_SHIFT (16U) +#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) +#define AIPS_MPRA_MTW3_MASK (0x20000U) +#define AIPS_MPRA_MTW3_SHIFT (17U) +#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) +#define AIPS_MPRA_MTR3_MASK (0x40000U) +#define AIPS_MPRA_MTR3_SHIFT (18U) +#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) +#define AIPS_MPRA_MPL2_MASK (0x100000U) +#define AIPS_MPRA_MPL2_SHIFT (20U) +#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) +#define AIPS_MPRA_MTW2_MASK (0x200000U) +#define AIPS_MPRA_MTW2_SHIFT (21U) +#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) +#define AIPS_MPRA_MTR2_MASK (0x400000U) +#define AIPS_MPRA_MTR2_SHIFT (22U) +#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) +#define AIPS_MPRA_MPL1_MASK (0x1000000U) +#define AIPS_MPRA_MPL1_SHIFT (24U) +#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) +#define AIPS_MPRA_MTW1_MASK (0x2000000U) +#define AIPS_MPRA_MTW1_SHIFT (25U) +#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) +#define AIPS_MPRA_MTR1_MASK (0x4000000U) +#define AIPS_MPRA_MTR1_SHIFT (26U) +#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) +#define AIPS_MPRA_MPL0_MASK (0x10000000U) +#define AIPS_MPRA_MPL0_SHIFT (28U) +#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) +#define AIPS_MPRA_MTW0_MASK (0x20000000U) +#define AIPS_MPRA_MTW0_SHIFT (29U) +#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) +#define AIPS_MPRA_MTR0_MASK (0x40000000U) +#define AIPS_MPRA_MTR0_SHIFT (30U) +#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) + +/*! @name PACRA - Peripheral Access Control Register */ +#define AIPS_PACRA_TP7_MASK (0x1U) +#define AIPS_PACRA_TP7_SHIFT (0U) +#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) +#define AIPS_PACRA_WP7_MASK (0x2U) +#define AIPS_PACRA_WP7_SHIFT (1U) +#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) +#define AIPS_PACRA_SP7_MASK (0x4U) +#define AIPS_PACRA_SP7_SHIFT (2U) +#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) +#define AIPS_PACRA_TP6_MASK (0x10U) +#define AIPS_PACRA_TP6_SHIFT (4U) +#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) +#define AIPS_PACRA_WP6_MASK (0x20U) +#define AIPS_PACRA_WP6_SHIFT (5U) +#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) +#define AIPS_PACRA_SP6_MASK (0x40U) +#define AIPS_PACRA_SP6_SHIFT (6U) +#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) +#define AIPS_PACRA_TP5_MASK (0x100U) +#define AIPS_PACRA_TP5_SHIFT (8U) +#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) +#define AIPS_PACRA_WP5_MASK (0x200U) +#define AIPS_PACRA_WP5_SHIFT (9U) +#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) +#define AIPS_PACRA_SP5_MASK (0x400U) +#define AIPS_PACRA_SP5_SHIFT (10U) +#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) +#define AIPS_PACRA_TP4_MASK (0x1000U) +#define AIPS_PACRA_TP4_SHIFT (12U) +#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) +#define AIPS_PACRA_WP4_MASK (0x2000U) +#define AIPS_PACRA_WP4_SHIFT (13U) +#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) +#define AIPS_PACRA_SP4_MASK (0x4000U) +#define AIPS_PACRA_SP4_SHIFT (14U) +#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) +#define AIPS_PACRA_TP3_MASK (0x10000U) +#define AIPS_PACRA_TP3_SHIFT (16U) +#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) +#define AIPS_PACRA_WP3_MASK (0x20000U) +#define AIPS_PACRA_WP3_SHIFT (17U) +#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) +#define AIPS_PACRA_SP3_MASK (0x40000U) +#define AIPS_PACRA_SP3_SHIFT (18U) +#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) +#define AIPS_PACRA_TP2_MASK (0x100000U) +#define AIPS_PACRA_TP2_SHIFT (20U) +#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) +#define AIPS_PACRA_WP2_MASK (0x200000U) +#define AIPS_PACRA_WP2_SHIFT (21U) +#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) +#define AIPS_PACRA_SP2_MASK (0x400000U) +#define AIPS_PACRA_SP2_SHIFT (22U) +#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) +#define AIPS_PACRA_TP1_MASK (0x1000000U) +#define AIPS_PACRA_TP1_SHIFT (24U) +#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) +#define AIPS_PACRA_WP1_MASK (0x2000000U) +#define AIPS_PACRA_WP1_SHIFT (25U) +#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) +#define AIPS_PACRA_SP1_MASK (0x4000000U) +#define AIPS_PACRA_SP1_SHIFT (26U) +#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) +#define AIPS_PACRA_TP0_MASK (0x10000000U) +#define AIPS_PACRA_TP0_SHIFT (28U) +#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) +#define AIPS_PACRA_WP0_MASK (0x20000000U) +#define AIPS_PACRA_WP0_SHIFT (29U) +#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) +#define AIPS_PACRA_SP0_MASK (0x40000000U) +#define AIPS_PACRA_SP0_SHIFT (30U) +#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) + +/*! @name PACRB - Peripheral Access Control Register */ +#define AIPS_PACRB_TP7_MASK (0x1U) +#define AIPS_PACRB_TP7_SHIFT (0U) +#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) +#define AIPS_PACRB_WP7_MASK (0x2U) +#define AIPS_PACRB_WP7_SHIFT (1U) +#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) +#define AIPS_PACRB_SP7_MASK (0x4U) +#define AIPS_PACRB_SP7_SHIFT (2U) +#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) +#define AIPS_PACRB_TP6_MASK (0x10U) +#define AIPS_PACRB_TP6_SHIFT (4U) +#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) +#define AIPS_PACRB_WP6_MASK (0x20U) +#define AIPS_PACRB_WP6_SHIFT (5U) +#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) +#define AIPS_PACRB_SP6_MASK (0x40U) +#define AIPS_PACRB_SP6_SHIFT (6U) +#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) +#define AIPS_PACRB_TP5_MASK (0x100U) +#define AIPS_PACRB_TP5_SHIFT (8U) +#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) +#define AIPS_PACRB_WP5_MASK (0x200U) +#define AIPS_PACRB_WP5_SHIFT (9U) +#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) +#define AIPS_PACRB_SP5_MASK (0x400U) +#define AIPS_PACRB_SP5_SHIFT (10U) +#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) +#define AIPS_PACRB_TP4_MASK (0x1000U) +#define AIPS_PACRB_TP4_SHIFT (12U) +#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) +#define AIPS_PACRB_WP4_MASK (0x2000U) +#define AIPS_PACRB_WP4_SHIFT (13U) +#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) +#define AIPS_PACRB_SP4_MASK (0x4000U) +#define AIPS_PACRB_SP4_SHIFT (14U) +#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) +#define AIPS_PACRB_TP3_MASK (0x10000U) +#define AIPS_PACRB_TP3_SHIFT (16U) +#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) +#define AIPS_PACRB_WP3_MASK (0x20000U) +#define AIPS_PACRB_WP3_SHIFT (17U) +#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) +#define AIPS_PACRB_SP3_MASK (0x40000U) +#define AIPS_PACRB_SP3_SHIFT (18U) +#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) +#define AIPS_PACRB_TP2_MASK (0x100000U) +#define AIPS_PACRB_TP2_SHIFT (20U) +#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) +#define AIPS_PACRB_WP2_MASK (0x200000U) +#define AIPS_PACRB_WP2_SHIFT (21U) +#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) +#define AIPS_PACRB_SP2_MASK (0x400000U) +#define AIPS_PACRB_SP2_SHIFT (22U) +#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) +#define AIPS_PACRB_TP1_MASK (0x1000000U) +#define AIPS_PACRB_TP1_SHIFT (24U) +#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) +#define AIPS_PACRB_WP1_MASK (0x2000000U) +#define AIPS_PACRB_WP1_SHIFT (25U) +#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) +#define AIPS_PACRB_SP1_MASK (0x4000000U) +#define AIPS_PACRB_SP1_SHIFT (26U) +#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) +#define AIPS_PACRB_TP0_MASK (0x10000000U) +#define AIPS_PACRB_TP0_SHIFT (28U) +#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) +#define AIPS_PACRB_WP0_MASK (0x20000000U) +#define AIPS_PACRB_WP0_SHIFT (29U) +#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) +#define AIPS_PACRB_SP0_MASK (0x40000000U) +#define AIPS_PACRB_SP0_SHIFT (30U) +#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) + +/*! @name PACRC - Peripheral Access Control Register */ +#define AIPS_PACRC_TP7_MASK (0x1U) +#define AIPS_PACRC_TP7_SHIFT (0U) +#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) +#define AIPS_PACRC_WP7_MASK (0x2U) +#define AIPS_PACRC_WP7_SHIFT (1U) +#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) +#define AIPS_PACRC_SP7_MASK (0x4U) +#define AIPS_PACRC_SP7_SHIFT (2U) +#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) +#define AIPS_PACRC_TP6_MASK (0x10U) +#define AIPS_PACRC_TP6_SHIFT (4U) +#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) +#define AIPS_PACRC_WP6_MASK (0x20U) +#define AIPS_PACRC_WP6_SHIFT (5U) +#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) +#define AIPS_PACRC_SP6_MASK (0x40U) +#define AIPS_PACRC_SP6_SHIFT (6U) +#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) +#define AIPS_PACRC_TP5_MASK (0x100U) +#define AIPS_PACRC_TP5_SHIFT (8U) +#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) +#define AIPS_PACRC_WP5_MASK (0x200U) +#define AIPS_PACRC_WP5_SHIFT (9U) +#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) +#define AIPS_PACRC_SP5_MASK (0x400U) +#define AIPS_PACRC_SP5_SHIFT (10U) +#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) +#define AIPS_PACRC_TP4_MASK (0x1000U) +#define AIPS_PACRC_TP4_SHIFT (12U) +#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) +#define AIPS_PACRC_WP4_MASK (0x2000U) +#define AIPS_PACRC_WP4_SHIFT (13U) +#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) +#define AIPS_PACRC_SP4_MASK (0x4000U) +#define AIPS_PACRC_SP4_SHIFT (14U) +#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) +#define AIPS_PACRC_TP3_MASK (0x10000U) +#define AIPS_PACRC_TP3_SHIFT (16U) +#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) +#define AIPS_PACRC_WP3_MASK (0x20000U) +#define AIPS_PACRC_WP3_SHIFT (17U) +#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) +#define AIPS_PACRC_SP3_MASK (0x40000U) +#define AIPS_PACRC_SP3_SHIFT (18U) +#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) +#define AIPS_PACRC_TP2_MASK (0x100000U) +#define AIPS_PACRC_TP2_SHIFT (20U) +#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) +#define AIPS_PACRC_WP2_MASK (0x200000U) +#define AIPS_PACRC_WP2_SHIFT (21U) +#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) +#define AIPS_PACRC_SP2_MASK (0x400000U) +#define AIPS_PACRC_SP2_SHIFT (22U) +#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) +#define AIPS_PACRC_TP1_MASK (0x1000000U) +#define AIPS_PACRC_TP1_SHIFT (24U) +#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) +#define AIPS_PACRC_WP1_MASK (0x2000000U) +#define AIPS_PACRC_WP1_SHIFT (25U) +#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) +#define AIPS_PACRC_SP1_MASK (0x4000000U) +#define AIPS_PACRC_SP1_SHIFT (26U) +#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) +#define AIPS_PACRC_TP0_MASK (0x10000000U) +#define AIPS_PACRC_TP0_SHIFT (28U) +#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) +#define AIPS_PACRC_WP0_MASK (0x20000000U) +#define AIPS_PACRC_WP0_SHIFT (29U) +#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) +#define AIPS_PACRC_SP0_MASK (0x40000000U) +#define AIPS_PACRC_SP0_SHIFT (30U) +#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) + +/*! @name PACRD - Peripheral Access Control Register */ +#define AIPS_PACRD_TP7_MASK (0x1U) +#define AIPS_PACRD_TP7_SHIFT (0U) +#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) +#define AIPS_PACRD_WP7_MASK (0x2U) +#define AIPS_PACRD_WP7_SHIFT (1U) +#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) +#define AIPS_PACRD_SP7_MASK (0x4U) +#define AIPS_PACRD_SP7_SHIFT (2U) +#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) +#define AIPS_PACRD_TP6_MASK (0x10U) +#define AIPS_PACRD_TP6_SHIFT (4U) +#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) +#define AIPS_PACRD_WP6_MASK (0x20U) +#define AIPS_PACRD_WP6_SHIFT (5U) +#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) +#define AIPS_PACRD_SP6_MASK (0x40U) +#define AIPS_PACRD_SP6_SHIFT (6U) +#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) +#define AIPS_PACRD_TP5_MASK (0x100U) +#define AIPS_PACRD_TP5_SHIFT (8U) +#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) +#define AIPS_PACRD_WP5_MASK (0x200U) +#define AIPS_PACRD_WP5_SHIFT (9U) +#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) +#define AIPS_PACRD_SP5_MASK (0x400U) +#define AIPS_PACRD_SP5_SHIFT (10U) +#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) +#define AIPS_PACRD_TP4_MASK (0x1000U) +#define AIPS_PACRD_TP4_SHIFT (12U) +#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) +#define AIPS_PACRD_WP4_MASK (0x2000U) +#define AIPS_PACRD_WP4_SHIFT (13U) +#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) +#define AIPS_PACRD_SP4_MASK (0x4000U) +#define AIPS_PACRD_SP4_SHIFT (14U) +#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) +#define AIPS_PACRD_TP3_MASK (0x10000U) +#define AIPS_PACRD_TP3_SHIFT (16U) +#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) +#define AIPS_PACRD_WP3_MASK (0x20000U) +#define AIPS_PACRD_WP3_SHIFT (17U) +#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) +#define AIPS_PACRD_SP3_MASK (0x40000U) +#define AIPS_PACRD_SP3_SHIFT (18U) +#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) +#define AIPS_PACRD_TP2_MASK (0x100000U) +#define AIPS_PACRD_TP2_SHIFT (20U) +#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) +#define AIPS_PACRD_WP2_MASK (0x200000U) +#define AIPS_PACRD_WP2_SHIFT (21U) +#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) +#define AIPS_PACRD_SP2_MASK (0x400000U) +#define AIPS_PACRD_SP2_SHIFT (22U) +#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) +#define AIPS_PACRD_TP1_MASK (0x1000000U) +#define AIPS_PACRD_TP1_SHIFT (24U) +#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) +#define AIPS_PACRD_WP1_MASK (0x2000000U) +#define AIPS_PACRD_WP1_SHIFT (25U) +#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) +#define AIPS_PACRD_SP1_MASK (0x4000000U) +#define AIPS_PACRD_SP1_SHIFT (26U) +#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) +#define AIPS_PACRD_TP0_MASK (0x10000000U) +#define AIPS_PACRD_TP0_SHIFT (28U) +#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) +#define AIPS_PACRD_WP0_MASK (0x20000000U) +#define AIPS_PACRD_WP0_SHIFT (29U) +#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) +#define AIPS_PACRD_SP0_MASK (0x40000000U) +#define AIPS_PACRD_SP0_SHIFT (30U) +#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) + +/*! @name PACRE - Peripheral Access Control Register */ +#define AIPS_PACRE_TP7_MASK (0x1U) +#define AIPS_PACRE_TP7_SHIFT (0U) +#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) +#define AIPS_PACRE_WP7_MASK (0x2U) +#define AIPS_PACRE_WP7_SHIFT (1U) +#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) +#define AIPS_PACRE_SP7_MASK (0x4U) +#define AIPS_PACRE_SP7_SHIFT (2U) +#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) +#define AIPS_PACRE_TP6_MASK (0x10U) +#define AIPS_PACRE_TP6_SHIFT (4U) +#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) +#define AIPS_PACRE_WP6_MASK (0x20U) +#define AIPS_PACRE_WP6_SHIFT (5U) +#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) +#define AIPS_PACRE_SP6_MASK (0x40U) +#define AIPS_PACRE_SP6_SHIFT (6U) +#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) +#define AIPS_PACRE_TP5_MASK (0x100U) +#define AIPS_PACRE_TP5_SHIFT (8U) +#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) +#define AIPS_PACRE_WP5_MASK (0x200U) +#define AIPS_PACRE_WP5_SHIFT (9U) +#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) +#define AIPS_PACRE_SP5_MASK (0x400U) +#define AIPS_PACRE_SP5_SHIFT (10U) +#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) +#define AIPS_PACRE_TP4_MASK (0x1000U) +#define AIPS_PACRE_TP4_SHIFT (12U) +#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) +#define AIPS_PACRE_WP4_MASK (0x2000U) +#define AIPS_PACRE_WP4_SHIFT (13U) +#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) +#define AIPS_PACRE_SP4_MASK (0x4000U) +#define AIPS_PACRE_SP4_SHIFT (14U) +#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) +#define AIPS_PACRE_TP3_MASK (0x10000U) +#define AIPS_PACRE_TP3_SHIFT (16U) +#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) +#define AIPS_PACRE_WP3_MASK (0x20000U) +#define AIPS_PACRE_WP3_SHIFT (17U) +#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) +#define AIPS_PACRE_SP3_MASK (0x40000U) +#define AIPS_PACRE_SP3_SHIFT (18U) +#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) +#define AIPS_PACRE_TP2_MASK (0x100000U) +#define AIPS_PACRE_TP2_SHIFT (20U) +#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) +#define AIPS_PACRE_WP2_MASK (0x200000U) +#define AIPS_PACRE_WP2_SHIFT (21U) +#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) +#define AIPS_PACRE_SP2_MASK (0x400000U) +#define AIPS_PACRE_SP2_SHIFT (22U) +#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) +#define AIPS_PACRE_TP1_MASK (0x1000000U) +#define AIPS_PACRE_TP1_SHIFT (24U) +#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) +#define AIPS_PACRE_WP1_MASK (0x2000000U) +#define AIPS_PACRE_WP1_SHIFT (25U) +#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) +#define AIPS_PACRE_SP1_MASK (0x4000000U) +#define AIPS_PACRE_SP1_SHIFT (26U) +#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) +#define AIPS_PACRE_TP0_MASK (0x10000000U) +#define AIPS_PACRE_TP0_SHIFT (28U) +#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) +#define AIPS_PACRE_WP0_MASK (0x20000000U) +#define AIPS_PACRE_WP0_SHIFT (29U) +#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) +#define AIPS_PACRE_SP0_MASK (0x40000000U) +#define AIPS_PACRE_SP0_SHIFT (30U) +#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) + +/*! @name PACRF - Peripheral Access Control Register */ +#define AIPS_PACRF_TP7_MASK (0x1U) +#define AIPS_PACRF_TP7_SHIFT (0U) +#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) +#define AIPS_PACRF_WP7_MASK (0x2U) +#define AIPS_PACRF_WP7_SHIFT (1U) +#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) +#define AIPS_PACRF_SP7_MASK (0x4U) +#define AIPS_PACRF_SP7_SHIFT (2U) +#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) +#define AIPS_PACRF_TP6_MASK (0x10U) +#define AIPS_PACRF_TP6_SHIFT (4U) +#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) +#define AIPS_PACRF_WP6_MASK (0x20U) +#define AIPS_PACRF_WP6_SHIFT (5U) +#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) +#define AIPS_PACRF_SP6_MASK (0x40U) +#define AIPS_PACRF_SP6_SHIFT (6U) +#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) +#define AIPS_PACRF_TP5_MASK (0x100U) +#define AIPS_PACRF_TP5_SHIFT (8U) +#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) +#define AIPS_PACRF_WP5_MASK (0x200U) +#define AIPS_PACRF_WP5_SHIFT (9U) +#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) +#define AIPS_PACRF_SP5_MASK (0x400U) +#define AIPS_PACRF_SP5_SHIFT (10U) +#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) +#define AIPS_PACRF_TP4_MASK (0x1000U) +#define AIPS_PACRF_TP4_SHIFT (12U) +#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) +#define AIPS_PACRF_WP4_MASK (0x2000U) +#define AIPS_PACRF_WP4_SHIFT (13U) +#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) +#define AIPS_PACRF_SP4_MASK (0x4000U) +#define AIPS_PACRF_SP4_SHIFT (14U) +#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) +#define AIPS_PACRF_TP3_MASK (0x10000U) +#define AIPS_PACRF_TP3_SHIFT (16U) +#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) +#define AIPS_PACRF_WP3_MASK (0x20000U) +#define AIPS_PACRF_WP3_SHIFT (17U) +#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) +#define AIPS_PACRF_SP3_MASK (0x40000U) +#define AIPS_PACRF_SP3_SHIFT (18U) +#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) +#define AIPS_PACRF_TP2_MASK (0x100000U) +#define AIPS_PACRF_TP2_SHIFT (20U) +#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) +#define AIPS_PACRF_WP2_MASK (0x200000U) +#define AIPS_PACRF_WP2_SHIFT (21U) +#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) +#define AIPS_PACRF_SP2_MASK (0x400000U) +#define AIPS_PACRF_SP2_SHIFT (22U) +#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) +#define AIPS_PACRF_TP1_MASK (0x1000000U) +#define AIPS_PACRF_TP1_SHIFT (24U) +#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) +#define AIPS_PACRF_WP1_MASK (0x2000000U) +#define AIPS_PACRF_WP1_SHIFT (25U) +#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) +#define AIPS_PACRF_SP1_MASK (0x4000000U) +#define AIPS_PACRF_SP1_SHIFT (26U) +#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) +#define AIPS_PACRF_TP0_MASK (0x10000000U) +#define AIPS_PACRF_TP0_SHIFT (28U) +#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) +#define AIPS_PACRF_WP0_MASK (0x20000000U) +#define AIPS_PACRF_WP0_SHIFT (29U) +#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) +#define AIPS_PACRF_SP0_MASK (0x40000000U) +#define AIPS_PACRF_SP0_SHIFT (30U) +#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) + +/*! @name PACRG - Peripheral Access Control Register */ +#define AIPS_PACRG_TP7_MASK (0x1U) +#define AIPS_PACRG_TP7_SHIFT (0U) +#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) +#define AIPS_PACRG_WP7_MASK (0x2U) +#define AIPS_PACRG_WP7_SHIFT (1U) +#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) +#define AIPS_PACRG_SP7_MASK (0x4U) +#define AIPS_PACRG_SP7_SHIFT (2U) +#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) +#define AIPS_PACRG_TP6_MASK (0x10U) +#define AIPS_PACRG_TP6_SHIFT (4U) +#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) +#define AIPS_PACRG_WP6_MASK (0x20U) +#define AIPS_PACRG_WP6_SHIFT (5U) +#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) +#define AIPS_PACRG_SP6_MASK (0x40U) +#define AIPS_PACRG_SP6_SHIFT (6U) +#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) +#define AIPS_PACRG_TP5_MASK (0x100U) +#define AIPS_PACRG_TP5_SHIFT (8U) +#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) +#define AIPS_PACRG_WP5_MASK (0x200U) +#define AIPS_PACRG_WP5_SHIFT (9U) +#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) +#define AIPS_PACRG_SP5_MASK (0x400U) +#define AIPS_PACRG_SP5_SHIFT (10U) +#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) +#define AIPS_PACRG_TP4_MASK (0x1000U) +#define AIPS_PACRG_TP4_SHIFT (12U) +#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) +#define AIPS_PACRG_WP4_MASK (0x2000U) +#define AIPS_PACRG_WP4_SHIFT (13U) +#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) +#define AIPS_PACRG_SP4_MASK (0x4000U) +#define AIPS_PACRG_SP4_SHIFT (14U) +#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) +#define AIPS_PACRG_TP3_MASK (0x10000U) +#define AIPS_PACRG_TP3_SHIFT (16U) +#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) +#define AIPS_PACRG_WP3_MASK (0x20000U) +#define AIPS_PACRG_WP3_SHIFT (17U) +#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) +#define AIPS_PACRG_SP3_MASK (0x40000U) +#define AIPS_PACRG_SP3_SHIFT (18U) +#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) +#define AIPS_PACRG_TP2_MASK (0x100000U) +#define AIPS_PACRG_TP2_SHIFT (20U) +#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) +#define AIPS_PACRG_WP2_MASK (0x200000U) +#define AIPS_PACRG_WP2_SHIFT (21U) +#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) +#define AIPS_PACRG_SP2_MASK (0x400000U) +#define AIPS_PACRG_SP2_SHIFT (22U) +#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) +#define AIPS_PACRG_TP1_MASK (0x1000000U) +#define AIPS_PACRG_TP1_SHIFT (24U) +#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) +#define AIPS_PACRG_WP1_MASK (0x2000000U) +#define AIPS_PACRG_WP1_SHIFT (25U) +#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) +#define AIPS_PACRG_SP1_MASK (0x4000000U) +#define AIPS_PACRG_SP1_SHIFT (26U) +#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) +#define AIPS_PACRG_TP0_MASK (0x10000000U) +#define AIPS_PACRG_TP0_SHIFT (28U) +#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) +#define AIPS_PACRG_WP0_MASK (0x20000000U) +#define AIPS_PACRG_WP0_SHIFT (29U) +#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) +#define AIPS_PACRG_SP0_MASK (0x40000000U) +#define AIPS_PACRG_SP0_SHIFT (30U) +#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) + +/*! @name PACRH - Peripheral Access Control Register */ +#define AIPS_PACRH_TP7_MASK (0x1U) +#define AIPS_PACRH_TP7_SHIFT (0U) +#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) +#define AIPS_PACRH_WP7_MASK (0x2U) +#define AIPS_PACRH_WP7_SHIFT (1U) +#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) +#define AIPS_PACRH_SP7_MASK (0x4U) +#define AIPS_PACRH_SP7_SHIFT (2U) +#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) +#define AIPS_PACRH_TP6_MASK (0x10U) +#define AIPS_PACRH_TP6_SHIFT (4U) +#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) +#define AIPS_PACRH_WP6_MASK (0x20U) +#define AIPS_PACRH_WP6_SHIFT (5U) +#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) +#define AIPS_PACRH_SP6_MASK (0x40U) +#define AIPS_PACRH_SP6_SHIFT (6U) +#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) +#define AIPS_PACRH_TP5_MASK (0x100U) +#define AIPS_PACRH_TP5_SHIFT (8U) +#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) +#define AIPS_PACRH_WP5_MASK (0x200U) +#define AIPS_PACRH_WP5_SHIFT (9U) +#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) +#define AIPS_PACRH_SP5_MASK (0x400U) +#define AIPS_PACRH_SP5_SHIFT (10U) +#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) +#define AIPS_PACRH_TP4_MASK (0x1000U) +#define AIPS_PACRH_TP4_SHIFT (12U) +#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) +#define AIPS_PACRH_WP4_MASK (0x2000U) +#define AIPS_PACRH_WP4_SHIFT (13U) +#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) +#define AIPS_PACRH_SP4_MASK (0x4000U) +#define AIPS_PACRH_SP4_SHIFT (14U) +#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) +#define AIPS_PACRH_TP3_MASK (0x10000U) +#define AIPS_PACRH_TP3_SHIFT (16U) +#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) +#define AIPS_PACRH_WP3_MASK (0x20000U) +#define AIPS_PACRH_WP3_SHIFT (17U) +#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) +#define AIPS_PACRH_SP3_MASK (0x40000U) +#define AIPS_PACRH_SP3_SHIFT (18U) +#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) +#define AIPS_PACRH_TP2_MASK (0x100000U) +#define AIPS_PACRH_TP2_SHIFT (20U) +#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) +#define AIPS_PACRH_WP2_MASK (0x200000U) +#define AIPS_PACRH_WP2_SHIFT (21U) +#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) +#define AIPS_PACRH_SP2_MASK (0x400000U) +#define AIPS_PACRH_SP2_SHIFT (22U) +#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) +#define AIPS_PACRH_TP1_MASK (0x1000000U) +#define AIPS_PACRH_TP1_SHIFT (24U) +#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) +#define AIPS_PACRH_WP1_MASK (0x2000000U) +#define AIPS_PACRH_WP1_SHIFT (25U) +#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) +#define AIPS_PACRH_SP1_MASK (0x4000000U) +#define AIPS_PACRH_SP1_SHIFT (26U) +#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) +#define AIPS_PACRH_TP0_MASK (0x10000000U) +#define AIPS_PACRH_TP0_SHIFT (28U) +#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) +#define AIPS_PACRH_WP0_MASK (0x20000000U) +#define AIPS_PACRH_WP0_SHIFT (29U) +#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) +#define AIPS_PACRH_SP0_MASK (0x40000000U) +#define AIPS_PACRH_SP0_SHIFT (30U) +#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) + +/*! @name PACRI - Peripheral Access Control Register */ +#define AIPS_PACRI_TP7_MASK (0x1U) +#define AIPS_PACRI_TP7_SHIFT (0U) +#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) +#define AIPS_PACRI_WP7_MASK (0x2U) +#define AIPS_PACRI_WP7_SHIFT (1U) +#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) +#define AIPS_PACRI_SP7_MASK (0x4U) +#define AIPS_PACRI_SP7_SHIFT (2U) +#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) +#define AIPS_PACRI_TP6_MASK (0x10U) +#define AIPS_PACRI_TP6_SHIFT (4U) +#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) +#define AIPS_PACRI_WP6_MASK (0x20U) +#define AIPS_PACRI_WP6_SHIFT (5U) +#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) +#define AIPS_PACRI_SP6_MASK (0x40U) +#define AIPS_PACRI_SP6_SHIFT (6U) +#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) +#define AIPS_PACRI_TP5_MASK (0x100U) +#define AIPS_PACRI_TP5_SHIFT (8U) +#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) +#define AIPS_PACRI_WP5_MASK (0x200U) +#define AIPS_PACRI_WP5_SHIFT (9U) +#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) +#define AIPS_PACRI_SP5_MASK (0x400U) +#define AIPS_PACRI_SP5_SHIFT (10U) +#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) +#define AIPS_PACRI_TP4_MASK (0x1000U) +#define AIPS_PACRI_TP4_SHIFT (12U) +#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) +#define AIPS_PACRI_WP4_MASK (0x2000U) +#define AIPS_PACRI_WP4_SHIFT (13U) +#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) +#define AIPS_PACRI_SP4_MASK (0x4000U) +#define AIPS_PACRI_SP4_SHIFT (14U) +#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) +#define AIPS_PACRI_TP3_MASK (0x10000U) +#define AIPS_PACRI_TP3_SHIFT (16U) +#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) +#define AIPS_PACRI_WP3_MASK (0x20000U) +#define AIPS_PACRI_WP3_SHIFT (17U) +#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) +#define AIPS_PACRI_SP3_MASK (0x40000U) +#define AIPS_PACRI_SP3_SHIFT (18U) +#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) +#define AIPS_PACRI_TP2_MASK (0x100000U) +#define AIPS_PACRI_TP2_SHIFT (20U) +#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) +#define AIPS_PACRI_WP2_MASK (0x200000U) +#define AIPS_PACRI_WP2_SHIFT (21U) +#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) +#define AIPS_PACRI_SP2_MASK (0x400000U) +#define AIPS_PACRI_SP2_SHIFT (22U) +#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) +#define AIPS_PACRI_TP1_MASK (0x1000000U) +#define AIPS_PACRI_TP1_SHIFT (24U) +#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) +#define AIPS_PACRI_WP1_MASK (0x2000000U) +#define AIPS_PACRI_WP1_SHIFT (25U) +#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) +#define AIPS_PACRI_SP1_MASK (0x4000000U) +#define AIPS_PACRI_SP1_SHIFT (26U) +#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) +#define AIPS_PACRI_TP0_MASK (0x10000000U) +#define AIPS_PACRI_TP0_SHIFT (28U) +#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) +#define AIPS_PACRI_WP0_MASK (0x20000000U) +#define AIPS_PACRI_WP0_SHIFT (29U) +#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) +#define AIPS_PACRI_SP0_MASK (0x40000000U) +#define AIPS_PACRI_SP0_SHIFT (30U) +#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) + +/*! @name PACRJ - Peripheral Access Control Register */ +#define AIPS_PACRJ_TP7_MASK (0x1U) +#define AIPS_PACRJ_TP7_SHIFT (0U) +#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) +#define AIPS_PACRJ_WP7_MASK (0x2U) +#define AIPS_PACRJ_WP7_SHIFT (1U) +#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) +#define AIPS_PACRJ_SP7_MASK (0x4U) +#define AIPS_PACRJ_SP7_SHIFT (2U) +#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) +#define AIPS_PACRJ_TP6_MASK (0x10U) +#define AIPS_PACRJ_TP6_SHIFT (4U) +#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) +#define AIPS_PACRJ_WP6_MASK (0x20U) +#define AIPS_PACRJ_WP6_SHIFT (5U) +#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) +#define AIPS_PACRJ_SP6_MASK (0x40U) +#define AIPS_PACRJ_SP6_SHIFT (6U) +#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) +#define AIPS_PACRJ_TP5_MASK (0x100U) +#define AIPS_PACRJ_TP5_SHIFT (8U) +#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) +#define AIPS_PACRJ_WP5_MASK (0x200U) +#define AIPS_PACRJ_WP5_SHIFT (9U) +#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) +#define AIPS_PACRJ_SP5_MASK (0x400U) +#define AIPS_PACRJ_SP5_SHIFT (10U) +#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) +#define AIPS_PACRJ_TP4_MASK (0x1000U) +#define AIPS_PACRJ_TP4_SHIFT (12U) +#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) +#define AIPS_PACRJ_WP4_MASK (0x2000U) +#define AIPS_PACRJ_WP4_SHIFT (13U) +#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) +#define AIPS_PACRJ_SP4_MASK (0x4000U) +#define AIPS_PACRJ_SP4_SHIFT (14U) +#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) +#define AIPS_PACRJ_TP3_MASK (0x10000U) +#define AIPS_PACRJ_TP3_SHIFT (16U) +#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) +#define AIPS_PACRJ_WP3_MASK (0x20000U) +#define AIPS_PACRJ_WP3_SHIFT (17U) +#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) +#define AIPS_PACRJ_SP3_MASK (0x40000U) +#define AIPS_PACRJ_SP3_SHIFT (18U) +#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) +#define AIPS_PACRJ_TP2_MASK (0x100000U) +#define AIPS_PACRJ_TP2_SHIFT (20U) +#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) +#define AIPS_PACRJ_WP2_MASK (0x200000U) +#define AIPS_PACRJ_WP2_SHIFT (21U) +#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) +#define AIPS_PACRJ_SP2_MASK (0x400000U) +#define AIPS_PACRJ_SP2_SHIFT (22U) +#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) +#define AIPS_PACRJ_TP1_MASK (0x1000000U) +#define AIPS_PACRJ_TP1_SHIFT (24U) +#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) +#define AIPS_PACRJ_WP1_MASK (0x2000000U) +#define AIPS_PACRJ_WP1_SHIFT (25U) +#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) +#define AIPS_PACRJ_SP1_MASK (0x4000000U) +#define AIPS_PACRJ_SP1_SHIFT (26U) +#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) +#define AIPS_PACRJ_TP0_MASK (0x10000000U) +#define AIPS_PACRJ_TP0_SHIFT (28U) +#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) +#define AIPS_PACRJ_WP0_MASK (0x20000000U) +#define AIPS_PACRJ_WP0_SHIFT (29U) +#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) +#define AIPS_PACRJ_SP0_MASK (0x40000000U) +#define AIPS_PACRJ_SP0_SHIFT (30U) +#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) + +/*! @name PACRK - Peripheral Access Control Register */ +#define AIPS_PACRK_TP7_MASK (0x1U) +#define AIPS_PACRK_TP7_SHIFT (0U) +#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) +#define AIPS_PACRK_WP7_MASK (0x2U) +#define AIPS_PACRK_WP7_SHIFT (1U) +#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) +#define AIPS_PACRK_SP7_MASK (0x4U) +#define AIPS_PACRK_SP7_SHIFT (2U) +#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) +#define AIPS_PACRK_TP6_MASK (0x10U) +#define AIPS_PACRK_TP6_SHIFT (4U) +#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) +#define AIPS_PACRK_WP6_MASK (0x20U) +#define AIPS_PACRK_WP6_SHIFT (5U) +#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) +#define AIPS_PACRK_SP6_MASK (0x40U) +#define AIPS_PACRK_SP6_SHIFT (6U) +#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) +#define AIPS_PACRK_TP5_MASK (0x100U) +#define AIPS_PACRK_TP5_SHIFT (8U) +#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) +#define AIPS_PACRK_WP5_MASK (0x200U) +#define AIPS_PACRK_WP5_SHIFT (9U) +#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) +#define AIPS_PACRK_SP5_MASK (0x400U) +#define AIPS_PACRK_SP5_SHIFT (10U) +#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) +#define AIPS_PACRK_TP4_MASK (0x1000U) +#define AIPS_PACRK_TP4_SHIFT (12U) +#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) +#define AIPS_PACRK_WP4_MASK (0x2000U) +#define AIPS_PACRK_WP4_SHIFT (13U) +#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) +#define AIPS_PACRK_SP4_MASK (0x4000U) +#define AIPS_PACRK_SP4_SHIFT (14U) +#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) +#define AIPS_PACRK_TP3_MASK (0x10000U) +#define AIPS_PACRK_TP3_SHIFT (16U) +#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) +#define AIPS_PACRK_WP3_MASK (0x20000U) +#define AIPS_PACRK_WP3_SHIFT (17U) +#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) +#define AIPS_PACRK_SP3_MASK (0x40000U) +#define AIPS_PACRK_SP3_SHIFT (18U) +#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) +#define AIPS_PACRK_TP2_MASK (0x100000U) +#define AIPS_PACRK_TP2_SHIFT (20U) +#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) +#define AIPS_PACRK_WP2_MASK (0x200000U) +#define AIPS_PACRK_WP2_SHIFT (21U) +#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) +#define AIPS_PACRK_SP2_MASK (0x400000U) +#define AIPS_PACRK_SP2_SHIFT (22U) +#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) +#define AIPS_PACRK_TP1_MASK (0x1000000U) +#define AIPS_PACRK_TP1_SHIFT (24U) +#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) +#define AIPS_PACRK_WP1_MASK (0x2000000U) +#define AIPS_PACRK_WP1_SHIFT (25U) +#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) +#define AIPS_PACRK_SP1_MASK (0x4000000U) +#define AIPS_PACRK_SP1_SHIFT (26U) +#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) +#define AIPS_PACRK_TP0_MASK (0x10000000U) +#define AIPS_PACRK_TP0_SHIFT (28U) +#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) +#define AIPS_PACRK_WP0_MASK (0x20000000U) +#define AIPS_PACRK_WP0_SHIFT (29U) +#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) +#define AIPS_PACRK_SP0_MASK (0x40000000U) +#define AIPS_PACRK_SP0_SHIFT (30U) +#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) + +/*! @name PACRL - Peripheral Access Control Register */ +#define AIPS_PACRL_TP7_MASK (0x1U) +#define AIPS_PACRL_TP7_SHIFT (0U) +#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) +#define AIPS_PACRL_WP7_MASK (0x2U) +#define AIPS_PACRL_WP7_SHIFT (1U) +#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) +#define AIPS_PACRL_SP7_MASK (0x4U) +#define AIPS_PACRL_SP7_SHIFT (2U) +#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) +#define AIPS_PACRL_TP6_MASK (0x10U) +#define AIPS_PACRL_TP6_SHIFT (4U) +#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) +#define AIPS_PACRL_WP6_MASK (0x20U) +#define AIPS_PACRL_WP6_SHIFT (5U) +#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) +#define AIPS_PACRL_SP6_MASK (0x40U) +#define AIPS_PACRL_SP6_SHIFT (6U) +#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) +#define AIPS_PACRL_TP5_MASK (0x100U) +#define AIPS_PACRL_TP5_SHIFT (8U) +#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) +#define AIPS_PACRL_WP5_MASK (0x200U) +#define AIPS_PACRL_WP5_SHIFT (9U) +#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) +#define AIPS_PACRL_SP5_MASK (0x400U) +#define AIPS_PACRL_SP5_SHIFT (10U) +#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) +#define AIPS_PACRL_TP4_MASK (0x1000U) +#define AIPS_PACRL_TP4_SHIFT (12U) +#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) +#define AIPS_PACRL_WP4_MASK (0x2000U) +#define AIPS_PACRL_WP4_SHIFT (13U) +#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) +#define AIPS_PACRL_SP4_MASK (0x4000U) +#define AIPS_PACRL_SP4_SHIFT (14U) +#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) +#define AIPS_PACRL_TP3_MASK (0x10000U) +#define AIPS_PACRL_TP3_SHIFT (16U) +#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) +#define AIPS_PACRL_WP3_MASK (0x20000U) +#define AIPS_PACRL_WP3_SHIFT (17U) +#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) +#define AIPS_PACRL_SP3_MASK (0x40000U) +#define AIPS_PACRL_SP3_SHIFT (18U) +#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) +#define AIPS_PACRL_TP2_MASK (0x100000U) +#define AIPS_PACRL_TP2_SHIFT (20U) +#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) +#define AIPS_PACRL_WP2_MASK (0x200000U) +#define AIPS_PACRL_WP2_SHIFT (21U) +#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) +#define AIPS_PACRL_SP2_MASK (0x400000U) +#define AIPS_PACRL_SP2_SHIFT (22U) +#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) +#define AIPS_PACRL_TP1_MASK (0x1000000U) +#define AIPS_PACRL_TP1_SHIFT (24U) +#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) +#define AIPS_PACRL_WP1_MASK (0x2000000U) +#define AIPS_PACRL_WP1_SHIFT (25U) +#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) +#define AIPS_PACRL_SP1_MASK (0x4000000U) +#define AIPS_PACRL_SP1_SHIFT (26U) +#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) +#define AIPS_PACRL_TP0_MASK (0x10000000U) +#define AIPS_PACRL_TP0_SHIFT (28U) +#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) +#define AIPS_PACRL_WP0_MASK (0x20000000U) +#define AIPS_PACRL_WP0_SHIFT (29U) +#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) +#define AIPS_PACRL_SP0_MASK (0x40000000U) +#define AIPS_PACRL_SP0_SHIFT (30U) +#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) + +/*! @name PACRM - Peripheral Access Control Register */ +#define AIPS_PACRM_TP7_MASK (0x1U) +#define AIPS_PACRM_TP7_SHIFT (0U) +#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) +#define AIPS_PACRM_WP7_MASK (0x2U) +#define AIPS_PACRM_WP7_SHIFT (1U) +#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) +#define AIPS_PACRM_SP7_MASK (0x4U) +#define AIPS_PACRM_SP7_SHIFT (2U) +#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) +#define AIPS_PACRM_TP6_MASK (0x10U) +#define AIPS_PACRM_TP6_SHIFT (4U) +#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) +#define AIPS_PACRM_WP6_MASK (0x20U) +#define AIPS_PACRM_WP6_SHIFT (5U) +#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) +#define AIPS_PACRM_SP6_MASK (0x40U) +#define AIPS_PACRM_SP6_SHIFT (6U) +#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) +#define AIPS_PACRM_TP5_MASK (0x100U) +#define AIPS_PACRM_TP5_SHIFT (8U) +#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) +#define AIPS_PACRM_WP5_MASK (0x200U) +#define AIPS_PACRM_WP5_SHIFT (9U) +#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) +#define AIPS_PACRM_SP5_MASK (0x400U) +#define AIPS_PACRM_SP5_SHIFT (10U) +#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) +#define AIPS_PACRM_TP4_MASK (0x1000U) +#define AIPS_PACRM_TP4_SHIFT (12U) +#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) +#define AIPS_PACRM_WP4_MASK (0x2000U) +#define AIPS_PACRM_WP4_SHIFT (13U) +#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) +#define AIPS_PACRM_SP4_MASK (0x4000U) +#define AIPS_PACRM_SP4_SHIFT (14U) +#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) +#define AIPS_PACRM_TP3_MASK (0x10000U) +#define AIPS_PACRM_TP3_SHIFT (16U) +#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) +#define AIPS_PACRM_WP3_MASK (0x20000U) +#define AIPS_PACRM_WP3_SHIFT (17U) +#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) +#define AIPS_PACRM_SP3_MASK (0x40000U) +#define AIPS_PACRM_SP3_SHIFT (18U) +#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) +#define AIPS_PACRM_TP2_MASK (0x100000U) +#define AIPS_PACRM_TP2_SHIFT (20U) +#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) +#define AIPS_PACRM_WP2_MASK (0x200000U) +#define AIPS_PACRM_WP2_SHIFT (21U) +#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) +#define AIPS_PACRM_SP2_MASK (0x400000U) +#define AIPS_PACRM_SP2_SHIFT (22U) +#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) +#define AIPS_PACRM_TP1_MASK (0x1000000U) +#define AIPS_PACRM_TP1_SHIFT (24U) +#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) +#define AIPS_PACRM_WP1_MASK (0x2000000U) +#define AIPS_PACRM_WP1_SHIFT (25U) +#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) +#define AIPS_PACRM_SP1_MASK (0x4000000U) +#define AIPS_PACRM_SP1_SHIFT (26U) +#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) +#define AIPS_PACRM_TP0_MASK (0x10000000U) +#define AIPS_PACRM_TP0_SHIFT (28U) +#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) +#define AIPS_PACRM_WP0_MASK (0x20000000U) +#define AIPS_PACRM_WP0_SHIFT (29U) +#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) +#define AIPS_PACRM_SP0_MASK (0x40000000U) +#define AIPS_PACRM_SP0_SHIFT (30U) +#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) + +/*! @name PACRN - Peripheral Access Control Register */ +#define AIPS_PACRN_TP7_MASK (0x1U) +#define AIPS_PACRN_TP7_SHIFT (0U) +#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) +#define AIPS_PACRN_WP7_MASK (0x2U) +#define AIPS_PACRN_WP7_SHIFT (1U) +#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) +#define AIPS_PACRN_SP7_MASK (0x4U) +#define AIPS_PACRN_SP7_SHIFT (2U) +#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) +#define AIPS_PACRN_TP6_MASK (0x10U) +#define AIPS_PACRN_TP6_SHIFT (4U) +#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) +#define AIPS_PACRN_WP6_MASK (0x20U) +#define AIPS_PACRN_WP6_SHIFT (5U) +#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) +#define AIPS_PACRN_SP6_MASK (0x40U) +#define AIPS_PACRN_SP6_SHIFT (6U) +#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) +#define AIPS_PACRN_TP5_MASK (0x100U) +#define AIPS_PACRN_TP5_SHIFT (8U) +#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) +#define AIPS_PACRN_WP5_MASK (0x200U) +#define AIPS_PACRN_WP5_SHIFT (9U) +#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) +#define AIPS_PACRN_SP5_MASK (0x400U) +#define AIPS_PACRN_SP5_SHIFT (10U) +#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) +#define AIPS_PACRN_TP4_MASK (0x1000U) +#define AIPS_PACRN_TP4_SHIFT (12U) +#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) +#define AIPS_PACRN_WP4_MASK (0x2000U) +#define AIPS_PACRN_WP4_SHIFT (13U) +#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) +#define AIPS_PACRN_SP4_MASK (0x4000U) +#define AIPS_PACRN_SP4_SHIFT (14U) +#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) +#define AIPS_PACRN_TP3_MASK (0x10000U) +#define AIPS_PACRN_TP3_SHIFT (16U) +#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) +#define AIPS_PACRN_WP3_MASK (0x20000U) +#define AIPS_PACRN_WP3_SHIFT (17U) +#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) +#define AIPS_PACRN_SP3_MASK (0x40000U) +#define AIPS_PACRN_SP3_SHIFT (18U) +#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) +#define AIPS_PACRN_TP2_MASK (0x100000U) +#define AIPS_PACRN_TP2_SHIFT (20U) +#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) +#define AIPS_PACRN_WP2_MASK (0x200000U) +#define AIPS_PACRN_WP2_SHIFT (21U) +#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) +#define AIPS_PACRN_SP2_MASK (0x400000U) +#define AIPS_PACRN_SP2_SHIFT (22U) +#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) +#define AIPS_PACRN_TP1_MASK (0x1000000U) +#define AIPS_PACRN_TP1_SHIFT (24U) +#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) +#define AIPS_PACRN_WP1_MASK (0x2000000U) +#define AIPS_PACRN_WP1_SHIFT (25U) +#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) +#define AIPS_PACRN_SP1_MASK (0x4000000U) +#define AIPS_PACRN_SP1_SHIFT (26U) +#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) +#define AIPS_PACRN_TP0_MASK (0x10000000U) +#define AIPS_PACRN_TP0_SHIFT (28U) +#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) +#define AIPS_PACRN_WP0_MASK (0x20000000U) +#define AIPS_PACRN_WP0_SHIFT (29U) +#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) +#define AIPS_PACRN_SP0_MASK (0x40000000U) +#define AIPS_PACRN_SP0_SHIFT (30U) +#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) + +/*! @name PACRO - Peripheral Access Control Register */ +#define AIPS_PACRO_TP7_MASK (0x1U) +#define AIPS_PACRO_TP7_SHIFT (0U) +#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) +#define AIPS_PACRO_WP7_MASK (0x2U) +#define AIPS_PACRO_WP7_SHIFT (1U) +#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) +#define AIPS_PACRO_SP7_MASK (0x4U) +#define AIPS_PACRO_SP7_SHIFT (2U) +#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) +#define AIPS_PACRO_TP6_MASK (0x10U) +#define AIPS_PACRO_TP6_SHIFT (4U) +#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) +#define AIPS_PACRO_WP6_MASK (0x20U) +#define AIPS_PACRO_WP6_SHIFT (5U) +#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) +#define AIPS_PACRO_SP6_MASK (0x40U) +#define AIPS_PACRO_SP6_SHIFT (6U) +#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) +#define AIPS_PACRO_TP5_MASK (0x100U) +#define AIPS_PACRO_TP5_SHIFT (8U) +#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) +#define AIPS_PACRO_WP5_MASK (0x200U) +#define AIPS_PACRO_WP5_SHIFT (9U) +#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) +#define AIPS_PACRO_SP5_MASK (0x400U) +#define AIPS_PACRO_SP5_SHIFT (10U) +#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) +#define AIPS_PACRO_TP4_MASK (0x1000U) +#define AIPS_PACRO_TP4_SHIFT (12U) +#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) +#define AIPS_PACRO_WP4_MASK (0x2000U) +#define AIPS_PACRO_WP4_SHIFT (13U) +#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) +#define AIPS_PACRO_SP4_MASK (0x4000U) +#define AIPS_PACRO_SP4_SHIFT (14U) +#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) +#define AIPS_PACRO_TP3_MASK (0x10000U) +#define AIPS_PACRO_TP3_SHIFT (16U) +#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) +#define AIPS_PACRO_WP3_MASK (0x20000U) +#define AIPS_PACRO_WP3_SHIFT (17U) +#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) +#define AIPS_PACRO_SP3_MASK (0x40000U) +#define AIPS_PACRO_SP3_SHIFT (18U) +#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) +#define AIPS_PACRO_TP2_MASK (0x100000U) +#define AIPS_PACRO_TP2_SHIFT (20U) +#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) +#define AIPS_PACRO_WP2_MASK (0x200000U) +#define AIPS_PACRO_WP2_SHIFT (21U) +#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) +#define AIPS_PACRO_SP2_MASK (0x400000U) +#define AIPS_PACRO_SP2_SHIFT (22U) +#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) +#define AIPS_PACRO_TP1_MASK (0x1000000U) +#define AIPS_PACRO_TP1_SHIFT (24U) +#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) +#define AIPS_PACRO_WP1_MASK (0x2000000U) +#define AIPS_PACRO_WP1_SHIFT (25U) +#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) +#define AIPS_PACRO_SP1_MASK (0x4000000U) +#define AIPS_PACRO_SP1_SHIFT (26U) +#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) +#define AIPS_PACRO_TP0_MASK (0x10000000U) +#define AIPS_PACRO_TP0_SHIFT (28U) +#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) +#define AIPS_PACRO_WP0_MASK (0x20000000U) +#define AIPS_PACRO_WP0_SHIFT (29U) +#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) +#define AIPS_PACRO_SP0_MASK (0x40000000U) +#define AIPS_PACRO_SP0_SHIFT (30U) +#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) + +/*! @name PACRP - Peripheral Access Control Register */ +#define AIPS_PACRP_TP7_MASK (0x1U) +#define AIPS_PACRP_TP7_SHIFT (0U) +#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) +#define AIPS_PACRP_WP7_MASK (0x2U) +#define AIPS_PACRP_WP7_SHIFT (1U) +#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) +#define AIPS_PACRP_SP7_MASK (0x4U) +#define AIPS_PACRP_SP7_SHIFT (2U) +#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) +#define AIPS_PACRP_TP6_MASK (0x10U) +#define AIPS_PACRP_TP6_SHIFT (4U) +#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) +#define AIPS_PACRP_WP6_MASK (0x20U) +#define AIPS_PACRP_WP6_SHIFT (5U) +#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) +#define AIPS_PACRP_SP6_MASK (0x40U) +#define AIPS_PACRP_SP6_SHIFT (6U) +#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) +#define AIPS_PACRP_TP5_MASK (0x100U) +#define AIPS_PACRP_TP5_SHIFT (8U) +#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) +#define AIPS_PACRP_WP5_MASK (0x200U) +#define AIPS_PACRP_WP5_SHIFT (9U) +#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) +#define AIPS_PACRP_SP5_MASK (0x400U) +#define AIPS_PACRP_SP5_SHIFT (10U) +#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) +#define AIPS_PACRP_TP4_MASK (0x1000U) +#define AIPS_PACRP_TP4_SHIFT (12U) +#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) +#define AIPS_PACRP_WP4_MASK (0x2000U) +#define AIPS_PACRP_WP4_SHIFT (13U) +#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) +#define AIPS_PACRP_SP4_MASK (0x4000U) +#define AIPS_PACRP_SP4_SHIFT (14U) +#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) +#define AIPS_PACRP_TP3_MASK (0x10000U) +#define AIPS_PACRP_TP3_SHIFT (16U) +#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) +#define AIPS_PACRP_WP3_MASK (0x20000U) +#define AIPS_PACRP_WP3_SHIFT (17U) +#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) +#define AIPS_PACRP_SP3_MASK (0x40000U) +#define AIPS_PACRP_SP3_SHIFT (18U) +#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) +#define AIPS_PACRP_TP2_MASK (0x100000U) +#define AIPS_PACRP_TP2_SHIFT (20U) +#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) +#define AIPS_PACRP_WP2_MASK (0x200000U) +#define AIPS_PACRP_WP2_SHIFT (21U) +#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) +#define AIPS_PACRP_SP2_MASK (0x400000U) +#define AIPS_PACRP_SP2_SHIFT (22U) +#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) +#define AIPS_PACRP_TP1_MASK (0x1000000U) +#define AIPS_PACRP_TP1_SHIFT (24U) +#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) +#define AIPS_PACRP_WP1_MASK (0x2000000U) +#define AIPS_PACRP_WP1_SHIFT (25U) +#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) +#define AIPS_PACRP_SP1_MASK (0x4000000U) +#define AIPS_PACRP_SP1_SHIFT (26U) +#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) +#define AIPS_PACRP_TP0_MASK (0x10000000U) +#define AIPS_PACRP_TP0_SHIFT (28U) +#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) +#define AIPS_PACRP_WP0_MASK (0x20000000U) +#define AIPS_PACRP_WP0_SHIFT (29U) +#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) +#define AIPS_PACRP_SP0_MASK (0x40000000U) +#define AIPS_PACRP_SP0_SHIFT (30U) +#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) + /*! * @} @@ -1594,70 +2001,15 @@ typedef struct { #define AIPS0_BASE (0x40000000u) /** Peripheral AIPS0 base pointer */ #define AIPS0 ((AIPS_Type *)AIPS0_BASE) -#define AIPS0_BASE_PTR (AIPS0) /** Peripheral AIPS1 base address */ #define AIPS1_BASE (0x40080000u) /** Peripheral AIPS1 base pointer */ #define AIPS1 ((AIPS_Type *)AIPS1_BASE) -#define AIPS1_BASE_PTR (AIPS1) /** Array initializer of AIPS peripheral base addresses */ #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } /** Array initializer of AIPS peripheral base pointers */ #define AIPS_BASE_PTRS { AIPS0, AIPS1 } -/* ---------------------------------------------------------------------------- - -- AIPS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros - * @{ - */ - - -/* AIPS - Register instance definitions */ -/* AIPS0 */ -#define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) -#define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) -#define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) -#define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) -#define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) -#define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) -#define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) -#define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) -#define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) -#define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) -#define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) -#define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) -#define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) -#define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) -#define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) -#define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) -#define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) -/* AIPS1 */ -#define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) -#define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) -#define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) -#define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) -#define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) -#define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) -#define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) -#define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) -#define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) -#define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) -#define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) -#define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) -#define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) -#define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) -#define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) -#define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) -#define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) - -/*! - * @} - */ /* end of group AIPS_Register_Accessor_Macros */ - - /*! * @} */ /* end of group AIPS_Peripheral_Access_Layer */ @@ -1692,32 +2044,7 @@ typedef struct { __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_5[252]; __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ -} AXBS_Type, *AXBS_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- AXBS - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros - * @{ - */ - - -/* AXBS - Register accessors */ -#define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) -#define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) -#define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) -#define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) -#define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) -#define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) -#define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) -#define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) - -/*! - * @} - */ /* end of group AXBS_Register_Accessor_Macros */ - +} AXBS_Type; /* ---------------------------------------------------------------------------- -- AXBS Register Masks @@ -1728,63 +2055,79 @@ typedef struct { * @{ */ -/* PRS Bit Fields */ -#define AXBS_PRS_M0_MASK 0x7u -#define AXBS_PRS_M0_SHIFT 0 -#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define CAN_CTRL1_REG(base) ((base)->CTRL1) -#define CAN_TIMER_REG(base) ((base)->TIMER) -#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) -#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) -#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) -#define CAN_ECR_REG(base) ((base)->ECR) -#define CAN_ESR1_REG(base) ((base)->ESR1) -#define CAN_IMASK1_REG(base) ((base)->IMASK1) -#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) -#define CAN_CTRL2_REG(base) ((base)->CTRL2) -#define CAN_ESR2_REG(base) ((base)->ESR2) -#define CAN_CRCR_REG(base) ((base)->CRCR) -#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) -#define CAN_RXFIR_REG(base) ((base)->RXFIR) -#define CAN_CS_REG(base,index) ((base)->MB[index].CS) -#define CAN_ID_REG(base,index) ((base)->MB[index].ID) -#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) -#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) -#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) - -/*! - * @} - */ /* end of group CAN_Register_Accessor_Macros */ - +} CAN_Type; /* ---------------------------------------------------------------------------- -- CAN Register Masks @@ -1932,257 +2199,349 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define CAN_MCR_MAXMB_MASK 0x7Fu -#define CAN_MCR_MAXMB_SHIFT 0 -#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) -#define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) -#define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) -#define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) -#define CAU_STR_CASR_REG(base) ((base)->STR_CASR) -#define CAU_STR_CAA_REG(base) ((base)->STR_CAA) -#define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) -#define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) -#define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) -#define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) -#define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) -#define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) -#define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) -#define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) -#define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) -#define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) -#define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) -#define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) -#define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) -#define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) -#define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) -#define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) -#define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) -#define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) -#define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) - -/*! - * @} - */ /* end of group CAU_Register_Accessor_Macros */ - +} CAU_Type; /* ---------------------------------------------------------------------------- -- CAU Register Masks @@ -2535,375 +2629,443 @@ typedef struct { * @{ */ -/* DIRECT Bit Fields */ -#define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu -#define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 -#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) -#define CMP_CR1_REG(base) ((base)->CR1) -#define CMP_FPR_REG(base) ((base)->FPR) -#define CMP_SCR_REG(base) ((base)->SCR) -#define CMP_DACCR_REG(base) ((base)->DACCR) -#define CMP_MUXCR_REG(base) ((base)->MUXCR) - -/*! - * @} - */ /* end of group CMP_Register_Accessor_Macros */ - +} CMP_Type; /* ---------------------------------------------------------------------------- -- CMP Register Masks @@ -3110,62 +3115,84 @@ typedef struct { * @{ */ -/* CR0 Bit Fields */ -#define CMP_CR0_HYSTCTR_MASK 0x3u -#define CMP_CR0_HYSTCTR_SHIFT 0 -#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) -#define CMT_CGL1_REG(base) ((base)->CGL1) -#define CMT_CGH2_REG(base) ((base)->CGH2) -#define CMT_CGL2_REG(base) ((base)->CGL2) -#define CMT_OC_REG(base) ((base)->OC) -#define CMT_MSC_REG(base) ((base)->MSC) -#define CMT_CMD1_REG(base) ((base)->CMD1) -#define CMT_CMD2_REG(base) ((base)->CMD2) -#define CMT_CMD3_REG(base) ((base)->CMD3) -#define CMT_CMD4_REG(base) ((base)->CMD4) -#define CMT_PPS_REG(base) ((base)->PPS) -#define CMT_DMA_REG(base) ((base)->DMA) - -/*! - * @} - */ /* end of group CMT_Register_Accessor_Macros */ - +} CMT_Type; /* ---------------------------------------------------------------------------- -- CMT Register Masks @@ -3301,68 +3258,90 @@ typedef struct { * @{ */ -/* CGH1 Bit Fields */ -#define CMT_CGH1_PH_MASK 0xFFu -#define CMT_CGH1_PH_SHIFT 0 -#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.CRCL) -#define CRC_CRCH_REG(base) ((base)->ACCESS16BIT.CRCH) -#define CRC_CRC_REG(base) ((base)->CRC) -#define CRC_CRCLL_REG(base) ((base)->ACCESS8BIT.CRCLL) -#define CRC_CRCLU_REG(base) ((base)->ACCESS8BIT.CRCLU) -#define CRC_CRCHL_REG(base) ((base)->ACCESS8BIT.CRCHL) -#define CRC_CRCHU_REG(base) ((base)->ACCESS8BIT.CRCHU) -#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) -#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) -#define CRC_GPOLY_REG(base) ((base)->GPOLY) -#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) -#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) -#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) -#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) -#define CRC_CTRL_REG(base) ((base)->CTRL) -#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) - -/*! - * @} - */ /* end of group CRC_Register_Accessor_Macros */ - +} CRC_Type; /* ---------------------------------------------------------------------------- -- CRC Register Masks @@ -3505,100 +3420,122 @@ typedef struct { * @{ */ -/* CRCL Bit Fields */ -#define CRC_CRCL_CRCL_MASK 0xFFFFu -#define CRC_CRCL_CRCL_SHIFT 0 -#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) -#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) -#define DAC_SR_REG(base) ((base)->SR) -#define DAC_C0_REG(base) ((base)->C0) -#define DAC_C1_REG(base) ((base)->C1) -#define DAC_C2_REG(base) ((base)->C2) - -/*! - * @} - */ /* end of group DAC_Register_Accessor_Macros */ - +} DAC_Type; /* ---------------------------------------------------------------------------- -- DAC Register Masks @@ -3708,56 +3587,81 @@ typedef struct { * @{ */ -/* DATL Bit Fields */ -#define DAC_DATL_DATA0_MASK 0xFFu -#define DAC_DATL_DATA0_SHIFT 0 -#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) -#define DMA_ES_REG(base) ((base)->ES) -#define DMA_ERQ_REG(base) ((base)->ERQ) -#define DMA_EEI_REG(base) ((base)->EEI) -#define DMA_CEEI_REG(base) ((base)->CEEI) -#define DMA_SEEI_REG(base) ((base)->SEEI) -#define DMA_CERQ_REG(base) ((base)->CERQ) -#define DMA_SERQ_REG(base) ((base)->SERQ) -#define DMA_CDNE_REG(base) ((base)->CDNE) -#define DMA_SSRT_REG(base) ((base)->SSRT) -#define DMA_CERR_REG(base) ((base)->CERR) -#define DMA_CINT_REG(base) ((base)->CINT) -#define DMA_INT_REG(base) ((base)->INT) -#define DMA_ERR_REG(base) ((base)->ERR) -#define DMA_HRS_REG(base) ((base)->HRS) -#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) -#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) -#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) -#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) -#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) -#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) -#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) -#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) -#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) -#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) -#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) -#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) -#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) -#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) -#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) -#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) -#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) -#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) -#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) -#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) -#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) -#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) -#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) -#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) -#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) -#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) -#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) -#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) -#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) -#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) -#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) - -/*! - * @} - */ /* end of group DMA_Register_Accessor_Macros */ - +} DMA_Type; /* ---------------------------------------------------------------------------- -- DMA Register Masks @@ -4030,519 +3772,773 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define DMA_CR_EDBG_MASK 0x2u -#define DMA_CR_EDBG_SHIFT 1 -#define DMA_CR_ERCA_MASK 0x4u -#define DMA_CR_ERCA_SHIFT 2 -#define DMA_CR_HOE_MASK 0x10u -#define DMA_CR_HOE_SHIFT 4 -#define DMA_CR_HALT_MASK 0x20u -#define DMA_CR_HALT_SHIFT 5 -#define DMA_CR_CLM_MASK 0x40u -#define DMA_CR_CLM_SHIFT 6 -#define DMA_CR_EMLM_MASK 0x80u -#define DMA_CR_EMLM_SHIFT 7 -#define DMA_CR_ECX_MASK 0x10000u -#define DMA_CR_ECX_SHIFT 16 -#define DMA_CR_CX_MASK 0x20000u -#define DMA_CR_CX_SHIFT 17 -/* ES Bit Fields */ -#define DMA_ES_DBE_MASK 0x1u -#define DMA_ES_DBE_SHIFT 0 -#define DMA_ES_SBE_MASK 0x2u -#define DMA_ES_SBE_SHIFT 1 -#define DMA_ES_SGE_MASK 0x4u -#define DMA_ES_SGE_SHIFT 2 -#define DMA_ES_NCE_MASK 0x8u -#define DMA_ES_NCE_SHIFT 3 -#define DMA_ES_DOE_MASK 0x10u -#define DMA_ES_DOE_SHIFT 4 -#define DMA_ES_DAE_MASK 0x20u -#define DMA_ES_DAE_SHIFT 5 -#define DMA_ES_SOE_MASK 0x40u -#define DMA_ES_SOE_SHIFT 6 -#define DMA_ES_SAE_MASK 0x80u -#define DMA_ES_SAE_SHIFT 7 -#define DMA_ES_ERRCHN_MASK 0xF00u -#define DMA_ES_ERRCHN_SHIFT 8 -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) - -/*! - * @} - */ /* end of group DMAMUX_Register_Accessor_Macros */ - +} DMAMUX_Type; /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks @@ -4915,14 +4586,20 @@ typedef struct { * @{ */ -/* CHCFG Bit Fields */ -#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu -#define DMAMUX_CHCFG_SOURCE_SHIFT 0 -#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<EIR) -#define ENET_EIMR_REG(base) ((base)->EIMR) -#define ENET_RDAR_REG(base) ((base)->RDAR) -#define ENET_TDAR_REG(base) ((base)->TDAR) -#define ENET_ECR_REG(base) ((base)->ECR) -#define ENET_MMFR_REG(base) ((base)->MMFR) -#define ENET_MSCR_REG(base) ((base)->MSCR) -#define ENET_MIBC_REG(base) ((base)->MIBC) -#define ENET_RCR_REG(base) ((base)->RCR) -#define ENET_TCR_REG(base) ((base)->TCR) -#define ENET_PALR_REG(base) ((base)->PALR) -#define ENET_PAUR_REG(base) ((base)->PAUR) -#define ENET_OPD_REG(base) ((base)->OPD) -#define ENET_IAUR_REG(base) ((base)->IAUR) -#define ENET_IALR_REG(base) ((base)->IALR) -#define ENET_GAUR_REG(base) ((base)->GAUR) -#define ENET_GALR_REG(base) ((base)->GALR) -#define ENET_TFWR_REG(base) ((base)->TFWR) -#define ENET_RDSR_REG(base) ((base)->RDSR) -#define ENET_TDSR_REG(base) ((base)->TDSR) -#define ENET_MRBR_REG(base) ((base)->MRBR) -#define ENET_RSFL_REG(base) ((base)->RSFL) -#define ENET_RSEM_REG(base) ((base)->RSEM) -#define ENET_RAEM_REG(base) ((base)->RAEM) -#define ENET_RAFL_REG(base) ((base)->RAFL) -#define ENET_TSEM_REG(base) ((base)->TSEM) -#define ENET_TAEM_REG(base) ((base)->TAEM) -#define ENET_TAFL_REG(base) ((base)->TAFL) -#define ENET_TIPG_REG(base) ((base)->TIPG) -#define ENET_FTRL_REG(base) ((base)->FTRL) -#define ENET_TACC_REG(base) ((base)->TACC) -#define ENET_RACC_REG(base) ((base)->RACC) -#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) -#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) -#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) -#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) -#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) -#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) -#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) -#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) -#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) -#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) -#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) -#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) -#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) -#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) -#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) -#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) -#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) -#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) -#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) -#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) -#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) -#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) -#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) -#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) -#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) -#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) -#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) -#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) -#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) -#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) -#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) -#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) -#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) -#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) -#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) -#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) -#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) -#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) -#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) -#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) -#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) -#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) -#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) -#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) -#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) -#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) -#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) -#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) -#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) -#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) -#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) -#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) -#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) -#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) -#define ENET_ATCR_REG(base) ((base)->ATCR) -#define ENET_ATVR_REG(base) ((base)->ATVR) -#define ENET_ATOFF_REG(base) ((base)->ATOFF) -#define ENET_ATPER_REG(base) ((base)->ATPER) -#define ENET_ATCOR_REG(base) ((base)->ATCOR) -#define ENET_ATINC_REG(base) ((base)->ATINC) -#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) -#define ENET_TGSR_REG(base) ((base)->TGSR) -#define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) -#define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ - +} ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks @@ -5232,551 +4758,739 @@ typedef struct { * @{ */ -/* EIR Bit Fields */ -#define ENET_EIR_TS_TIMER_MASK 0x8000u -#define ENET_EIR_TS_TIMER_SHIFT 15 -#define ENET_EIR_TS_AVAIL_MASK 0x10000u -#define ENET_EIR_TS_AVAIL_SHIFT 16 -#define ENET_EIR_WAKEUP_MASK 0x20000u -#define ENET_EIR_WAKEUP_SHIFT 17 -#define ENET_EIR_PLR_MASK 0x40000u -#define ENET_EIR_PLR_SHIFT 18 -#define ENET_EIR_UN_MASK 0x80000u -#define ENET_EIR_UN_SHIFT 19 -#define ENET_EIR_RL_MASK 0x100000u -#define ENET_EIR_RL_SHIFT 20 -#define ENET_EIR_LC_MASK 0x200000u -#define ENET_EIR_LC_SHIFT 21 -#define ENET_EIR_EBERR_MASK 0x400000u -#define ENET_EIR_EBERR_SHIFT 22 -#define ENET_EIR_MII_MASK 0x800000u -#define ENET_EIR_MII_SHIFT 23 -#define ENET_EIR_RXB_MASK 0x1000000u -#define ENET_EIR_RXB_SHIFT 24 -#define ENET_EIR_RXF_MASK 0x2000000u -#define ENET_EIR_RXF_SHIFT 25 -#define ENET_EIR_TXB_MASK 0x4000000u -#define ENET_EIR_TXB_SHIFT 26 -#define ENET_EIR_TXF_MASK 0x8000000u -#define ENET_EIR_TXF_SHIFT 27 -#define ENET_EIR_GRA_MASK 0x10000000u -#define ENET_EIR_GRA_SHIFT 28 -#define ENET_EIR_BABT_MASK 0x20000000u -#define ENET_EIR_BABT_SHIFT 29 -#define ENET_EIR_BABR_MASK 0x40000000u -#define ENET_EIR_BABR_SHIFT 30 -/* EIMR Bit Fields */ -#define ENET_EIMR_TS_TIMER_MASK 0x8000u -#define ENET_EIMR_TS_TIMER_SHIFT 15 -#define ENET_EIMR_TS_AVAIL_MASK 0x10000u -#define ENET_EIMR_TS_AVAIL_SHIFT 16 -#define ENET_EIMR_WAKEUP_MASK 0x20000u -#define ENET_EIMR_WAKEUP_SHIFT 17 -#define ENET_EIMR_PLR_MASK 0x40000u -#define ENET_EIMR_PLR_SHIFT 18 -#define ENET_EIMR_UN_MASK 0x80000u -#define ENET_EIMR_UN_SHIFT 19 -#define ENET_EIMR_RL_MASK 0x100000u -#define ENET_EIMR_RL_SHIFT 20 -#define ENET_EIMR_LC_MASK 0x200000u -#define ENET_EIMR_LC_SHIFT 21 -#define ENET_EIMR_EBERR_MASK 0x400000u -#define ENET_EIMR_EBERR_SHIFT 22 -#define ENET_EIMR_MII_MASK 0x800000u -#define ENET_EIMR_MII_SHIFT 23 -#define ENET_EIMR_RXB_MASK 0x1000000u -#define ENET_EIMR_RXB_SHIFT 24 -#define ENET_EIMR_RXF_MASK 0x2000000u -#define ENET_EIMR_RXF_SHIFT 25 -#define ENET_EIMR_TXB_MASK 0x4000000u -#define ENET_EIMR_TXB_SHIFT 26 -#define ENET_EIMR_TXF_MASK 0x8000000u -#define ENET_EIMR_TXF_SHIFT 27 -#define ENET_EIMR_GRA_MASK 0x10000000u -#define ENET_EIMR_GRA_SHIFT 28 -#define ENET_EIMR_BABT_MASK 0x20000000u -#define ENET_EIMR_BABT_SHIFT 29 -#define ENET_EIMR_BABR_MASK 0x40000000u -#define ENET_EIMR_BABR_SHIFT 30 -/* RDAR Bit Fields */ -#define ENET_RDAR_RDAR_MASK 0x1000000u -#define ENET_RDAR_RDAR_SHIFT 24 -/* TDAR Bit Fields */ -#define ENET_TDAR_TDAR_MASK 0x1000000u -#define ENET_TDAR_TDAR_SHIFT 24 -/* ECR Bit Fields */ -#define ENET_ECR_RESET_MASK 0x1u -#define ENET_ECR_RESET_SHIFT 0 -#define ENET_ECR_ETHEREN_MASK 0x2u -#define ENET_ECR_ETHEREN_SHIFT 1 -#define ENET_ECR_MAGICEN_MASK 0x4u -#define ENET_ECR_MAGICEN_SHIFT 2 -#define ENET_ECR_SLEEP_MASK 0x8u -#define ENET_ECR_SLEEP_SHIFT 3 -#define ENET_ECR_EN1588_MASK 0x10u -#define ENET_ECR_EN1588_SHIFT 4 -#define ENET_ECR_DBGEN_MASK 0x40u -#define ENET_ECR_DBGEN_SHIFT 6 -#define ENET_ECR_STOPEN_MASK 0x80u -#define ENET_ECR_STOPEN_SHIFT 7 -#define ENET_ECR_DBSWP_MASK 0x100u -#define ENET_ECR_DBSWP_SHIFT 8 -/* MMFR Bit Fields */ -#define ENET_MMFR_DATA_MASK 0xFFFFu -#define ENET_MMFR_DATA_SHIFT 0 -#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE) */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG) */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB) */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - RMON Tx collision count (RMON_T_COL) */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - RMON Tx 64 byte packets (RMON_T_P64) */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - RMON Tx 65 to 127 byte packets (RMON_T_P65TO127) */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - RMON Tx 128 to 255 byte packets (RMON_T_P128TO255) */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - RMON Tx 256 to 511 byte packets (RMON_T_P256TO511) */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023) */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047) */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048) */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - RMON Tx Octets (RMON_T_OCTETS) */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK (IEEE_T_FRAME_OK) */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision (IEEE_T_1COL) */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions (IEEE_T_MCOL) */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay (IEEE_T_DEF) */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision (IEEE_T_LCOL) */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL) */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR) */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR) */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause frames transmitted (IEEE_T_FDXFC) */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - RMON Rx packet count (RMON_R_PACKETS) */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - RMON Rx Broadcast Packets (RMON_R_BC_PKT) */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - RMON Rx Multicast Packets (RMON_R_MC_PKT) */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN) */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE) */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE) */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG) */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB) */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - RMON Rx 64 byte packets (RMON_R_P64) */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - RMON Rx 65 to 127 byte packets (RMON_R_P65TO127) */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - RMON Rx 128 to 255 byte packets (RMON_R_P128TO255) */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - RMON Rx 256 to 511 byte packets (RMON_R_P256TO511) */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023) */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047) */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048) */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - RMON Rx Octets (RMON_R_OCTETS) */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments. */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK (IEEE_R_FRAME_OK) */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error (IEEE_R_CRC) */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error (IEEE_R_ALIGN) */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive Fifo Overflow count (IEEE_R_MACERR) */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause frames received (IEEE_R_FDXFC) */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields). */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + /*! * @} @@ -5788,7 +5502,6 @@ typedef struct { #define ENET_BASE (0x400C0000u) /** Peripheral ENET base pointer */ #define ENET ((ENET_Type *)ENET_BASE) -#define ENET_BASE_PTR (ENET) /** Array initializer of ENET peripheral base addresses */ #define ENET_BASE_ADDRS { ENET_BASE } /** Array initializer of ENET peripheral base pointers */ @@ -5798,129 +5511,8 @@ typedef struct { #define ENET_Receive_IRQS { ENET_Receive_IRQn } #define ENET_Error_IRQS { ENET_Error_IRQn } #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn } - -/* ---------------------------------------------------------------------------- - -- ENET - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros - * @{ - */ - - -/* ENET - Register instance definitions */ -/* ENET */ -#define ENET_EIR ENET_EIR_REG(ENET) -#define ENET_EIMR ENET_EIMR_REG(ENET) -#define ENET_RDAR ENET_RDAR_REG(ENET) -#define ENET_TDAR ENET_TDAR_REG(ENET) -#define ENET_ECR ENET_ECR_REG(ENET) -#define ENET_MMFR ENET_MMFR_REG(ENET) -#define ENET_MSCR ENET_MSCR_REG(ENET) -#define ENET_MIBC ENET_MIBC_REG(ENET) -#define ENET_RCR ENET_RCR_REG(ENET) -#define ENET_TCR ENET_TCR_REG(ENET) -#define ENET_PALR ENET_PALR_REG(ENET) -#define ENET_PAUR ENET_PAUR_REG(ENET) -#define ENET_OPD ENET_OPD_REG(ENET) -#define ENET_IAUR ENET_IAUR_REG(ENET) -#define ENET_IALR ENET_IALR_REG(ENET) -#define ENET_GAUR ENET_GAUR_REG(ENET) -#define ENET_GALR ENET_GALR_REG(ENET) -#define ENET_TFWR ENET_TFWR_REG(ENET) -#define ENET_RDSR ENET_RDSR_REG(ENET) -#define ENET_TDSR ENET_TDSR_REG(ENET) -#define ENET_MRBR ENET_MRBR_REG(ENET) -#define ENET_RSFL ENET_RSFL_REG(ENET) -#define ENET_RSEM ENET_RSEM_REG(ENET) -#define ENET_RAEM ENET_RAEM_REG(ENET) -#define ENET_RAFL ENET_RAFL_REG(ENET) -#define ENET_TSEM ENET_TSEM_REG(ENET) -#define ENET_TAEM ENET_TAEM_REG(ENET) -#define ENET_TAFL ENET_TAFL_REG(ENET) -#define ENET_TIPG ENET_TIPG_REG(ENET) -#define ENET_FTRL ENET_FTRL_REG(ENET) -#define ENET_TACC ENET_TACC_REG(ENET) -#define ENET_RACC ENET_RACC_REG(ENET) -#define ENET_RMON_T_DROP ENET_RMON_T_DROP_REG(ENET) -#define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET) -#define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET) -#define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET) -#define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET) -#define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET) -#define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET) -#define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET) -#define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET) -#define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET) -#define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET) -#define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET) -#define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET) -#define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET) -#define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET) -#define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET) -#define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET) -#define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET) -#define ENET_IEEE_T_DROP ENET_IEEE_T_DROP_REG(ENET) -#define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET) -#define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET) -#define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET) -#define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET) -#define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET) -#define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET) -#define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET) -#define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET) -#define ENET_IEEE_T_SQE ENET_IEEE_T_SQE_REG(ENET) -#define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET) -#define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET) -#define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET) -#define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET) -#define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET) -#define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET) -#define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET) -#define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET) -#define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET) -#define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET) -#define ENET_RMON_R_RESVD_0 ENET_RMON_R_RESVD_0_REG(ENET) -#define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET) -#define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET) -#define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET) -#define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET) -#define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET) -#define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET) -#define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET) -#define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET) -#define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET) -#define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET) -#define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET) -#define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET) -#define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET) -#define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET) -#define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET) -#define ENET_ATCR ENET_ATCR_REG(ENET) -#define ENET_ATVR ENET_ATVR_REG(ENET) -#define ENET_ATOFF ENET_ATOFF_REG(ENET) -#define ENET_ATPER ENET_ATPER_REG(ENET) -#define ENET_ATCOR ENET_ATCOR_REG(ENET) -#define ENET_ATINC ENET_ATINC_REG(ENET) -#define ENET_ATSTMP ENET_ATSTMP_REG(ENET) -#define ENET_TGSR ENET_TGSR_REG(ENET) -#define ENET_TCSR0 ENET_TCSR_REG(ENET,0) -#define ENET_TCCR0 ENET_TCCR_REG(ENET,0) -#define ENET_TCSR1 ENET_TCSR_REG(ENET,1) -#define ENET_TCCR1 ENET_TCCR_REG(ENET,1) -#define ENET_TCSR2 ENET_TCSR_REG(ENET,2) -#define ENET_TCCR2 ENET_TCCR_REG(ENET,2) -#define ENET_TCSR3 ENET_TCSR_REG(ENET,3) -#define ENET_TCCR3 ENET_TCCR_REG(ENET,3) - -/* ENET - Register array accessors */ -#define ENET_TCSR(index) ENET_TCSR_REG(ENET,index) -#define ENET_TCCR(index) ENET_TCCR_REG(ENET,index) - -/*! - * @} - */ /* end of group ENET_Register_Accessor_Macros */ +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (16U) /*! @@ -5945,29 +5537,7 @@ typedef struct { __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ uint8_t RESERVED_0[1]; __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ -} EWM_Type, *EWM_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- EWM - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros - * @{ - */ - - -/* EWM - Register accessors */ -#define EWM_CTRL_REG(base) ((base)->CTRL) -#define EWM_SERV_REG(base) ((base)->SERV) -#define EWM_CMPL_REG(base) ((base)->CMPL) -#define EWM_CMPH_REG(base) ((base)->CMPH) -#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER) - -/*! - * @} - */ /* end of group EWM_Register_Accessor_Macros */ - +} EWM_Type; /* ---------------------------------------------------------------------------- -- EWM Register Masks @@ -5978,31 +5548,40 @@ typedef struct { * @{ */ -/* CTRL Bit Fields */ -#define EWM_CTRL_EWMEN_MASK 0x1u -#define EWM_CTRL_EWMEN_SHIFT 0 -#define EWM_CTRL_ASSIN_MASK 0x2u -#define EWM_CTRL_ASSIN_SHIFT 1 -#define EWM_CTRL_INEN_MASK 0x4u -#define EWM_CTRL_INEN_SHIFT 2 -#define EWM_CTRL_INTEN_MASK 0x8u -#define EWM_CTRL_INTEN_SHIFT 3 -/* SERV Bit Fields */ -#define EWM_SERV_SERVICE_MASK 0xFFu -#define EWM_SERV_SERVICE_SHIFT 0 -#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) -#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) -#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) -#define FB_CSPMCR_REG(base) ((base)->CSPMCR) - -/*! - * @} - */ /* end of group FB_Register_Accessor_Macros */ - +} FB_Type; /* ---------------------------------------------------------------------------- -- FB Register Masks @@ -6100,67 +5634,89 @@ typedef struct { * @{ */ -/* CSAR Bit Fields */ -#define FB_CSAR_BA_MASK 0xFFFF0000u -#define FB_CSAR_BA_SHIFT 16 -#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) -#define FMC_PFB0CR_REG(base) ((base)->PFB0CR) -#define FMC_PFB1CR_REG(base) ((base)->PFB1CR) -#define FMC_TAGVD_REG(base,index,index2) ((base)->TAGVD[index][index2]) -#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) -#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) - -/*! - * @} - */ /* end of group FMC_Register_Accessor_Macros */ - +} FMC_Type; /* ---------------------------------------------------------------------------- -- FMC Register Masks @@ -6280,106 +5770,150 @@ typedef struct { * @{ */ -/* PFAPR Bit Fields */ -#define FMC_PFAPR_M0AP_MASK 0x3u -#define FMC_PFAPR_M0AP_SHIFT 0 -#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) -#define FTFL_FCNFG_REG(base) ((base)->FCNFG) -#define FTFL_FSEC_REG(base) ((base)->FSEC) -#define FTFL_FOPT_REG(base) ((base)->FOPT) -#define FTFL_FCCOB3_REG(base) ((base)->FCCOB3) -#define FTFL_FCCOB2_REG(base) ((base)->FCCOB2) -#define FTFL_FCCOB1_REG(base) ((base)->FCCOB1) -#define FTFL_FCCOB0_REG(base) ((base)->FCCOB0) -#define FTFL_FCCOB7_REG(base) ((base)->FCCOB7) -#define FTFL_FCCOB6_REG(base) ((base)->FCCOB6) -#define FTFL_FCCOB5_REG(base) ((base)->FCCOB5) -#define FTFL_FCCOB4_REG(base) ((base)->FCCOB4) -#define FTFL_FCCOBB_REG(base) ((base)->FCCOBB) -#define FTFL_FCCOBA_REG(base) ((base)->FCCOBA) -#define FTFL_FCCOB9_REG(base) ((base)->FCCOB9) -#define FTFL_FCCOB8_REG(base) ((base)->FCCOB8) -#define FTFL_FPROT3_REG(base) ((base)->FPROT3) -#define FTFL_FPROT2_REG(base) ((base)->FPROT2) -#define FTFL_FPROT1_REG(base) ((base)->FPROT1) -#define FTFL_FPROT0_REG(base) ((base)->FPROT0) -#define FTFL_FEPROT_REG(base) ((base)->FEPROT) -#define FTFL_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group FTFL_Register_Accessor_Macros */ - +} FTFL_Type; /* ---------------------------------------------------------------------------- -- FTFL Register Masks @@ -6608,123 +5980,158 @@ typedef struct { * @{ */ -/* FSTAT Bit Fields */ -#define FTFL_FSTAT_MGSTAT0_MASK 0x1u -#define FTFL_FSTAT_MGSTAT0_SHIFT 0 -#define FTFL_FSTAT_FPVIOL_MASK 0x10u -#define FTFL_FSTAT_FPVIOL_SHIFT 4 -#define FTFL_FSTAT_ACCERR_MASK 0x20u -#define FTFL_FSTAT_ACCERR_SHIFT 5 -#define FTFL_FSTAT_RDCOLERR_MASK 0x40u -#define FTFL_FSTAT_RDCOLERR_SHIFT 6 -#define FTFL_FSTAT_CCIF_MASK 0x80u -#define FTFL_FSTAT_CCIF_SHIFT 7 -/* FCNFG Bit Fields */ -#define FTFL_FCNFG_EEERDY_MASK 0x1u -#define FTFL_FCNFG_EEERDY_SHIFT 0 -#define FTFL_FCNFG_RAMRDY_MASK 0x2u -#define FTFL_FCNFG_RAMRDY_SHIFT 1 -#define FTFL_FCNFG_PFLSH_MASK 0x4u -#define FTFL_FCNFG_PFLSH_SHIFT 2 -#define FTFL_FCNFG_SWAP_MASK 0x8u -#define FTFL_FCNFG_SWAP_SHIFT 3 -#define FTFL_FCNFG_ERSSUSP_MASK 0x10u -#define FTFL_FCNFG_ERSSUSP_SHIFT 4 -#define FTFL_FCNFG_ERSAREQ_MASK 0x20u -#define FTFL_FCNFG_ERSAREQ_SHIFT 5 -#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u -#define FTFL_FCNFG_RDCOLLIE_SHIFT 6 -#define FTFL_FCNFG_CCIE_MASK 0x80u -#define FTFL_FCNFG_CCIE_SHIFT 7 -/* FSEC Bit Fields */ -#define FTFL_FSEC_SEC_MASK 0x3u -#define FTFL_FSEC_SEC_SHIFT 0 -#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) -#define FTM_CNT_REG(base) ((base)->CNT) -#define FTM_MOD_REG(base) ((base)->MOD) -#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) -#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) -#define FTM_CNTIN_REG(base) ((base)->CNTIN) -#define FTM_STATUS_REG(base) ((base)->STATUS) -#define FTM_MODE_REG(base) ((base)->MODE) -#define FTM_SYNC_REG(base) ((base)->SYNC) -#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) -#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) -#define FTM_COMBINE_REG(base) ((base)->COMBINE) -#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) -#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) -#define FTM_POL_REG(base) ((base)->POL) -#define FTM_FMS_REG(base) ((base)->FMS) -#define FTM_FILTER_REG(base) ((base)->FILTER) -#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) -#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) -#define FTM_CONF_REG(base) ((base)->CONF) -#define FTM_FLTPOL_REG(base) ((base)->FLTPOL) -#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) -#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) -#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) -#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) - -/*! - * @} - */ /* end of group FTM_Register_Accessor_Macros */ - +} FTM_Type; /* ---------------------------------------------------------------------------- -- FTM Register Masks @@ -6881,409 +6205,605 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define FTM_SC_PS_MASK 0x7u -#define FTM_SC_PS_SHIFT 0 -#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) -#define GPIO_PSOR_REG(base) ((base)->PSOR) -#define GPIO_PCOR_REG(base) ((base)->PCOR) -#define GPIO_PTOR_REG(base) ((base)->PTOR) -#define GPIO_PDIR_REG(base) ((base)->PDIR) -#define GPIO_PDDR_REG(base) ((base)->PDDR) - -/*! - * @} - */ /* end of group GPIO_Register_Accessor_Macros */ - +} GPIO_Type; /* ---------------------------------------------------------------------------- -- GPIO Register Masks @@ -7490,30 +6863,36 @@ typedef struct { * @{ */ -/* PDOR Bit Fields */ -#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu -#define GPIO_PDOR_PDO_SHIFT 0 -#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) -#define I2C_F_REG(base) ((base)->F) -#define I2C_C1_REG(base) ((base)->C1) -#define I2C_S_REG(base) ((base)->S) -#define I2C_D_REG(base) ((base)->D) -#define I2C_C2_REG(base) ((base)->C2) -#define I2C_FLT_REG(base) ((base)->FLT) -#define I2C_RA_REG(base) ((base)->RA) -#define I2C_SMB_REG(base) ((base)->SMB) -#define I2C_A2_REG(base) ((base)->A2) -#define I2C_SLTH_REG(base) ((base)->SLTH) -#define I2C_SLTL_REG(base) ((base)->SLTL) - -/*! - * @} - */ /* end of group I2C_Register_Accessor_Macros */ - +} I2C_Type; /* ---------------------------------------------------------------------------- -- I2C Register Masks @@ -7671,106 +6964,147 @@ typedef struct { * @{ */ -/* A1 Bit Fields */ -#define I2C_A1_AD_MASK 0xFEu -#define I2C_A1_AD_SHIFT 1 -#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) -#define I2S_TCR1_REG(base) ((base)->TCR1) -#define I2S_TCR2_REG(base) ((base)->TCR2) -#define I2S_TCR3_REG(base) ((base)->TCR3) -#define I2S_TCR4_REG(base) ((base)->TCR4) -#define I2S_TCR5_REG(base) ((base)->TCR5) -#define I2S_TDR_REG(base,index) ((base)->TDR[index]) -#define I2S_TFR_REG(base,index) ((base)->TFR[index]) -#define I2S_TMR_REG(base) ((base)->TMR) -#define I2S_RCSR_REG(base) ((base)->RCSR) -#define I2S_RCR1_REG(base) ((base)->RCR1) -#define I2S_RCR2_REG(base) ((base)->RCR2) -#define I2S_RCR3_REG(base) ((base)->RCR3) -#define I2S_RCR4_REG(base) ((base)->RCR4) -#define I2S_RCR5_REG(base) ((base)->RCR5) -#define I2S_RDR_REG(base,index) ((base)->RDR[index]) -#define I2S_RFR_REG(base,index) ((base)->RFR[index]) -#define I2S_RMR_REG(base) ((base)->RMR) -#define I2S_MCR_REG(base) ((base)->MCR) -#define I2S_MDR_REG(base) ((base)->MDR) - -/*! - * @} - */ /* end of group I2S_Register_Accessor_Macros */ - +} I2S_Type; /* ---------------------------------------------------------------------------- -- I2S Register Masks @@ -7930,233 +7182,319 @@ typedef struct { * @{ */ -/* TCSR Bit Fields */ -#define I2S_TCSR_FRDE_MASK 0x1u -#define I2S_TCSR_FRDE_SHIFT 0 -#define I2S_TCSR_FWDE_MASK 0x2u -#define I2S_TCSR_FWDE_SHIFT 1 -#define I2S_TCSR_FRIE_MASK 0x100u -#define I2S_TCSR_FRIE_SHIFT 8 -#define I2S_TCSR_FWIE_MASK 0x200u -#define I2S_TCSR_FWIE_SHIFT 9 -#define I2S_TCSR_FEIE_MASK 0x400u -#define I2S_TCSR_FEIE_SHIFT 10 -#define I2S_TCSR_SEIE_MASK 0x800u -#define I2S_TCSR_SEIE_SHIFT 11 -#define I2S_TCSR_WSIE_MASK 0x1000u -#define I2S_TCSR_WSIE_SHIFT 12 -#define I2S_TCSR_FRF_MASK 0x10000u -#define I2S_TCSR_FRF_SHIFT 16 -#define I2S_TCSR_FWF_MASK 0x20000u -#define I2S_TCSR_FWF_SHIFT 17 -#define I2S_TCSR_FEF_MASK 0x40000u -#define I2S_TCSR_FEF_SHIFT 18 -#define I2S_TCSR_SEF_MASK 0x80000u -#define I2S_TCSR_SEF_SHIFT 19 -#define I2S_TCSR_WSF_MASK 0x100000u -#define I2S_TCSR_WSF_SHIFT 20 -#define I2S_TCSR_SR_MASK 0x1000000u -#define I2S_TCSR_SR_SHIFT 24 -#define I2S_TCSR_FR_MASK 0x2000000u -#define I2S_TCSR_FR_SHIFT 25 -#define I2S_TCSR_BCE_MASK 0x10000000u -#define I2S_TCSR_BCE_SHIFT 28 -#define I2S_TCSR_DBGE_MASK 0x20000000u -#define I2S_TCSR_DBGE_SHIFT 29 -#define I2S_TCSR_STOPE_MASK 0x40000000u -#define I2S_TCSR_STOPE_SHIFT 30 -#define I2S_TCSR_TE_MASK 0x80000000u -#define I2S_TCSR_TE_SHIFT 31 -/* TCR1 Bit Fields */ -#define I2S_TCR1_TFW_MASK 0x7u -#define I2S_TCR1_TFW_SHIFT 0 -#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) -#define LLWU_PE2_REG(base) ((base)->PE2) -#define LLWU_PE3_REG(base) ((base)->PE3) -#define LLWU_PE4_REG(base) ((base)->PE4) -#define LLWU_ME_REG(base) ((base)->ME) -#define LLWU_F1_REG(base) ((base)->F1) -#define LLWU_F2_REG(base) ((base)->F2) -#define LLWU_F3_REG(base) ((base)->F3) -#define LLWU_FILT1_REG(base) ((base)->FILT1) -#define LLWU_FILT2_REG(base) ((base)->FILT2) -#define LLWU_RST_REG(base) ((base)->RST) - -/*! - * @} - */ /* end of group LLWU_Register_Accessor_Macros */ - +} LLWU_Type; /* ---------------------------------------------------------------------------- -- LLWU Register Masks @@ -8291,149 +7552,196 @@ typedef struct { * @{ */ -/* PE1 Bit Fields */ -#define LLWU_PE1_WUPE0_MASK 0x3u -#define LLWU_PE1_WUPE0_SHIFT 0 -#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) -#define LPTMR_PSR_REG(base) ((base)->PSR) -#define LPTMR_CMR_REG(base) ((base)->CMR) -#define LPTMR_CNR_REG(base) ((base)->CNR) - -/*! - * @} - */ /* end of group LPTMR_Register_Accessor_Macros */ - +} LPTMR_Type; /* ---------------------------------------------------------------------------- -- LPTMR Register Masks @@ -8534,39 +7791,50 @@ typedef struct { * @{ */ -/* CSR Bit Fields */ -#define LPTMR_CSR_TEN_MASK 0x1u -#define LPTMR_CSR_TEN_SHIFT 0 -#define LPTMR_CSR_TMS_MASK 0x2u -#define LPTMR_CSR_TMS_SHIFT 1 -#define LPTMR_CSR_TFC_MASK 0x4u -#define LPTMR_CSR_TFC_SHIFT 2 -#define LPTMR_CSR_TPP_MASK 0x8u -#define LPTMR_CSR_TPP_SHIFT 3 -#define LPTMR_CSR_TPS_MASK 0x30u -#define LPTMR_CSR_TPS_SHIFT 4 -#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) -#define MCG_C2_REG(base) ((base)->C2) -#define MCG_C3_REG(base) ((base)->C3) -#define MCG_C4_REG(base) ((base)->C4) -#define MCG_C5_REG(base) ((base)->C5) -#define MCG_C6_REG(base) ((base)->C6) -#define MCG_S_REG(base) ((base)->S) -#define MCG_SC_REG(base) ((base)->SC) -#define MCG_ATCVH_REG(base) ((base)->ATCVH) -#define MCG_ATCVL_REG(base) ((base)->ATCVL) -#define MCG_C7_REG(base) ((base)->C7) -#define MCG_C8_REG(base) ((base)->C8) -#define MCG_C9_REG(base) ((base)->C9) -#define MCG_C10_REG(base) ((base)->C10) - -/*! - * @} - */ /* end of group MCG_Register_Accessor_Macros */ - +} MCG_Type; /* ---------------------------------------------------------------------------- -- MCG Register Masks @@ -8682,116 +7896,159 @@ typedef struct { * @{ */ -/* C1 Bit Fields */ -#define MCG_C1_IREFSTEN_MASK 0x1u -#define MCG_C1_IREFSTEN_SHIFT 0 -#define MCG_C1_IRCLKEN_MASK 0x2u -#define MCG_C1_IRCLKEN_SHIFT 1 -#define MCG_C1_IREFS_MASK 0x4u -#define MCG_C1_IREFS_SHIFT 2 -#define MCG_C1_FRDIV_MASK 0x38u -#define MCG_C1_FRDIV_SHIFT 3 -#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) -#define MCM_PLAMC_REG(base) ((base)->PLAMC) -#define MCM_CR_REG(base) ((base)->CR) -#define MCM_ISR_REG(base) ((base)->ISR) -#define MCM_ETBCC_REG(base) ((base)->ETBCC) -#define MCM_ETBRL_REG(base) ((base)->ETBRL) -#define MCM_ETBCNT_REG(base) ((base)->ETBCNT) -#define MCM_PID_REG(base) ((base)->PID) - -/*! - * @} - */ /* end of group MCM_Register_Accessor_Macros */ - +} MCM_Type; /* ---------------------------------------------------------------------------- -- MCM Register Masks @@ -8903,56 +8128,73 @@ typedef struct { * @{ */ -/* PLASC Bit Fields */ -#define MCM_PLASC_ASC_MASK 0xFFu -#define MCM_PLASC_ASC_SHIFT 0 -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) -#define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) -#define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) -#define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) -#define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) - -/*! - * @} - */ /* end of group MPU_Register_Accessor_Macros */ - - -/* ---------------------------------------------------------------------------- - -- MPU Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MPU_Register_Masks MPU Register Masks - * @{ - */ - -/* CESR Bit Fields */ -#define MPU_CESR_VLD_MASK 0x1u -#define MPU_CESR_VLD_SHIFT 0 -#define MPU_CESR_NRGD_MASK 0xF00u -#define MPU_CESR_NRGD_SHIFT 8 -#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) -#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) -#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) -#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) -#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) -#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) -#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) -#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) -#define NV_FPROT3_REG(base) ((base)->FPROT3) -#define NV_FPROT2_REG(base) ((base)->FPROT2) -#define NV_FPROT1_REG(base) ((base)->FPROT1) -#define NV_FPROT0_REG(base) ((base)->FPROT0) -#define NV_FSEC_REG(base) ((base)->FSEC) -#define NV_FOPT_REG(base) ((base)->FOPT) -#define NV_FEPROT_REG(base) ((base)->FEPROT) -#define NV_FDPROT_REG(base) ((base)->FDPROT) - -/*! - * @} - */ /* end of group NV_Register_Accessor_Macros */ - +} NV_Type; /* ---------------------------------------------------------------------------- -- NV Register Masks @@ -9364,82 +8256,101 @@ typedef struct { * @{ */ -/* BACKKEY3 Bit Fields */ -#define NV_BACKKEY3_KEY_MASK 0xFFu -#define NV_BACKKEY3_KEY_SHIFT 0 -#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - +} OSC_Type; /* ---------------------------------------------------------------------------- -- OSC Register Masks @@ -9537,19 +8395,26 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define OSC_CR_SC16P_MASK 0x1u -#define OSC_CR_SC16P_SHIFT 0 -#define OSC_CR_SC8P_MASK 0x2u -#define OSC_CR_SC8P_SHIFT 1 -#define OSC_CR_SC4P_MASK 0x4u -#define OSC_CR_SC4P_SHIFT 2 -#define OSC_CR_SC2P_MASK 0x8u -#define OSC_CR_SC2P_SHIFT 3 -#define OSC_CR_EREFSTEN_MASK 0x20u -#define OSC_CR_EREFSTEN_SHIFT 5 -#define OSC_CR_ERCLKEN_MASK 0x80u -#define OSC_CR_ERCLKEN_SHIFT 7 +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + /*! * @} @@ -9561,31 +8426,11 @@ typedef struct { #define OSC_BASE (0x40065000u) /** Peripheral OSC base pointer */ #define OSC ((OSC_Type *)OSC_BASE) -#define OSC_BASE_PTR (OSC) /** Array initializer of OSC peripheral base addresses */ #define OSC_BASE_ADDRS { OSC_BASE } /** Array initializer of OSC peripheral base pointers */ #define OSC_BASE_PTRS { OSC } -/* ---------------------------------------------------------------------------- - -- OSC - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros - * @{ - */ - - -/* OSC - Register instance definitions */ -/* OSC */ -#define OSC_CR OSC_CR_REG(OSC) - -/*! - * @} - */ /* end of group OSC_Register_Accessor_Macros */ - - /*! * @} */ /* end of group OSC_Peripheral_Access_Layer */ @@ -9620,35 +8465,7 @@ typedef struct { uint8_t RESERVED_1[48]; __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */ -} PDB_Type, *PDB_MemMapPtr; - -/* ---------------------------------------------------------------------------- - -- PDB - Register accessor macros - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros - * @{ - */ - - -/* PDB - Register accessors */ -#define PDB_SC_REG(base) ((base)->SC) -#define PDB_MOD_REG(base) ((base)->MOD) -#define PDB_CNT_REG(base) ((base)->CNT) -#define PDB_IDLY_REG(base) ((base)->IDLY) -#define PDB_C1_REG(base,index) ((base)->CH[index].C1) -#define PDB_S_REG(base,index) ((base)->CH[index].S) -#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) -#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) -#define PDB_INT_REG(base,index) ((base)->DAC[index].INT) -#define PDB_POEN_REG(base) ((base)->POEN) -#define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) - -/*! - * @} - */ /* end of group PDB_Register_Accessor_Macros */ - +} PDB_Type; /* ---------------------------------------------------------------------------- -- PDB Register Masks @@ -9659,88 +8476,130 @@ typedef struct { * @{ */ -/* SC Bit Fields */ -#define PDB_SC_LDOK_MASK 0x1u -#define PDB_SC_LDOK_SHIFT 0 -#define PDB_SC_CONT_MASK 0x2u -#define PDB_SC_CONT_SHIFT 1 -#define PDB_SC_MULT_MASK 0xCu -#define PDB_SC_MULT_SHIFT 2 -#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) -#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) -#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) -#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) -#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) - -/*! - * @} - */ /* end of group PIT_Register_Accessor_Macros */ - +} PIT_Type; /* ---------------------------------------------------------------------------- -- PIT Register Masks @@ -9863,29 +8653,52 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define PIT_MCR_FRZ_MASK 0x1u -#define PIT_MCR_FRZ_SHIFT 0 -#define PIT_MCR_MDIS_MASK 0x2u -#define PIT_MCR_MDIS_SHIFT 1 -/* LDVAL Bit Fields */ -#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu -#define PIT_LDVAL_TSV_SHIFT 0 -#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) -#define PMC_LVDSC2_REG(base) ((base)->LVDSC2) -#define PMC_REGSC_REG(base) ((base)->REGSC) - -/*! - * @} - */ /* end of group PMC_Register_Accessor_Macros */ - +} PMC_Type; /* ---------------------------------------------------------------------------- -- PMC Register Masks @@ -9996,37 +8747,51 @@ typedef struct { * @{ */ -/* LVDSC1 Bit Fields */ -#define PMC_LVDSC1_LVDV_MASK 0x3u -#define PMC_LVDSC1_LVDV_SHIFT 0 -#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) -#define PORT_GPCLR_REG(base) ((base)->GPCLR) -#define PORT_GPCHR_REG(base) ((base)->GPCHR) -#define PORT_ISFR_REG(base) ((base)->ISFR) -#define PORT_DFER_REG(base) ((base)->DFER) -#define PORT_DFCR_REG(base) ((base)->DFCR) -#define PORT_DFWR_REG(base) ((base)->DFWR) - -/*! - * @} - */ /* end of group PORT_Register_Accessor_Macros */ - +} PORT_Type; /* ---------------------------------------------------------------------------- -- PORT Register Masks @@ -10127,58 +8846,77 @@ typedef struct { * @{ */ -/* PCR Bit Fields */ -#define PORT_PCR_PS_MASK 0x1u -#define PORT_PCR_PS_SHIFT 0 -#define PORT_PCR_PE_MASK 0x2u -#define PORT_PCR_PE_SHIFT 1 -#define PORT_PCR_SRE_MASK 0x4u -#define PORT_PCR_SRE_SHIFT 2 -#define PORT_PCR_PFE_MASK 0x10u -#define PORT_PCR_PFE_SHIFT 4 -#define PORT_PCR_ODE_MASK 0x20u -#define PORT_PCR_ODE_SHIFT 5 -#define PORT_PCR_DSE_MASK 0x40u -#define PORT_PCR_DSE_SHIFT 6 -#define PORT_PCR_MUX_MASK 0x700u -#define PORT_PCR_MUX_SHIFT 8 -#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) -#define RCM_SRS1_REG(base) ((base)->SRS1) -#define RCM_RPFC_REG(base) ((base)->RPFC) -#define RCM_RPFW_REG(base) ((base)->RPFW) -#define RCM_MR_REG(base) ((base)->MR) - -/*! - * @} - */ /* end of group RCM_Register_Accessor_Macros */ - +} RCM_Type; /* ---------------------------------------------------------------------------- -- RCM Register Masks @@ -10493,47 +8985,67 @@ typedef struct { * @{ */ -/* SRS0 Bit Fields */ -#define RCM_SRS0_WAKEUP_MASK 0x1u -#define RCM_SRS0_WAKEUP_SHIFT 0 -#define RCM_SRS0_LVD_MASK 0x2u -#define RCM_SRS0_LVD_SHIFT 1 -#define RCM_SRS0_LOC_MASK 0x4u -#define RCM_SRS0_LOC_SHIFT 2 -#define RCM_SRS0_LOL_MASK 0x8u -#define RCM_SRS0_LOL_SHIFT 3 -#define RCM_SRS0_WDOG_MASK 0x20u -#define RCM_SRS0_WDOG_SHIFT 5 -#define RCM_SRS0_PIN_MASK 0x40u -#define RCM_SRS0_PIN_SHIFT 6 -#define RCM_SRS0_POR_MASK 0x80u -#define RCM_SRS0_POR_SHIFT 7 -/* SRS1 Bit Fields */ -#define RCM_SRS1_JTAG_MASK 0x1u -#define RCM_SRS1_JTAG_SHIFT 0 -#define RCM_SRS1_LOCKUP_MASK 0x2u -#define RCM_SRS1_LOCKUP_SHIFT 1 -#define RCM_SRS1_SW_MASK 0x4u -#define RCM_SRS1_SW_SHIFT 2 -#define RCM_SRS1_MDM_AP_MASK 0x8u -#define RCM_SRS1_MDM_AP_SHIFT 3 -#define RCM_SRS1_EZPT_MASK 0x10u -#define RCM_SRS1_EZPT_SHIFT 4 -#define RCM_SRS1_SACKERR_MASK 0x20u -#define RCM_SRS1_SACKERR_SHIFT 5 -/* RPFC Bit Fields */ -#define RCM_RPFC_RSTFLTSRW_MASK 0x3u -#define RCM_RPFC_RSTFLTSRW_SHIFT 0 -#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFSYS_Register_Accessor_Macros */ - +} RFSYS_Type; /* ---------------------------------------------------------------------------- -- RFSYS Register Masks @@ -10620,19 +9090,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFSYS_REG_LL_MASK 0xFFu -#define RFSYS_REG_LL_SHIFT 0 -#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) - -/*! - * @} - */ /* end of group RFVBAT_Register_Accessor_Macros */ - +} RFVBAT_Type; /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks @@ -10725,19 +9151,23 @@ typedef struct { * @{ */ -/* REG Bit Fields */ -#define RFVBAT_REG_LL_MASK 0xFFu -#define RFVBAT_REG_LL_SHIFT 0 -#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) -#define RNG_SR_REG(base) ((base)->SR) -#define RNG_ER_REG(base) ((base)->ER) -#define RNG_OR_REG(base) ((base)->OR) - -/*! - * @} - */ /* end of group RNG_Register_Accessor_Macros */ - +} RNG_Type; /* ---------------------------------------------------------------------------- -- RNG Register Masks @@ -10836,42 +9215,56 @@ typedef struct { * @{ */ -/* CR Bit Fields */ -#define RNG_CR_GO_MASK 0x1u -#define RNG_CR_GO_SHIFT 0 -#define RNG_CR_HA_MASK 0x2u -#define RNG_CR_HA_SHIFT 1 -#define RNG_CR_INTM_MASK 0x4u -#define RNG_CR_INTM_SHIFT 2 -#define RNG_CR_CLRI_MASK 0x8u -#define RNG_CR_CLRI_SHIFT 3 -#define RNG_CR_SLP_MASK 0x10u -#define RNG_CR_SLP_SHIFT 4 -/* SR Bit Fields */ -#define RNG_SR_SECV_MASK 0x1u -#define RNG_SR_SECV_SHIFT 0 -#define RNG_SR_LRS_MASK 0x2u -#define RNG_SR_LRS_SHIFT 1 -#define RNG_SR_ORU_MASK 0x4u -#define RNG_SR_ORU_SHIFT 2 -#define RNG_SR_ERRI_MASK 0x8u -#define RNG_SR_ERRI_SHIFT 3 -#define RNG_SR_SLP_MASK 0x10u -#define RNG_SR_SLP_SHIFT 4 -#define RNG_SR_OREG_LVL_MASK 0xFF00u -#define RNG_SR_OREG_LVL_SHIFT 8 -#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) -#define RTC_TPR_REG(base) ((base)->TPR) -#define RTC_TAR_REG(base) ((base)->TAR) -#define RTC_TCR_REG(base) ((base)->TCR) -#define RTC_CR_REG(base) ((base)->CR) -#define RTC_SR_REG(base) ((base)->SR) -#define RTC_LR_REG(base) ((base)->LR) -#define RTC_IER_REG(base) ((base)->IER) -#define RTC_WAR_REG(base) ((base)->WAR) -#define RTC_RAR_REG(base) ((base)->RAR) - -/*! - * @} - */ /* end of group RTC_Register_Accessor_Macros */ - +} RTC_Type; /* ---------------------------------------------------------------------------- -- RTC Register Masks @@ -10978,115 +9321,164 @@ typedef struct { * @{ */ -/* TSR Bit Fields */ -#define RTC_TSR_TSR_MASK 0xFFFFFFFFu -#define RTC_TSR_TSR_SHIFT 0 -#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) -#define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) -#define SDHC_CMDARG_REG(base) ((base)->CMDARG) -#define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) -#define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) -#define SDHC_DATPORT_REG(base) ((base)->DATPORT) -#define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) -#define SDHC_PROCTL_REG(base) ((base)->PROCTL) -#define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) -#define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) -#define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) -#define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) -#define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) -#define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) -#define SDHC_WML_REG(base) ((base)->WML) -#define SDHC_FEVT_REG(base) ((base)->FEVT) -#define SDHC_ADMAES_REG(base) ((base)->ADMAES) -#define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) -#define SDHC_VENDOR_REG(base) ((base)->VENDOR) -#define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) -#define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) - -/*! - * @} - */ /* end of group SDHC_Register_Accessor_Macros */ - +} SDHC_Type; /* ---------------------------------------------------------------------------- -- SDHC Register Masks @@ -11224,378 +9549,534 @@ typedef struct { * @{ */ -/* DSADDR Bit Fields */ -#define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu -#define SDHC_DSADDR_DSADDR_SHIFT 2 -#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) -#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) -#define SIM_SOPT2_REG(base) ((base)->SOPT2) -#define SIM_SOPT4_REG(base) ((base)->SOPT4) -#define SIM_SOPT5_REG(base) ((base)->SOPT5) -#define SIM_SOPT7_REG(base) ((base)->SOPT7) -#define SIM_SDID_REG(base) ((base)->SDID) -#define SIM_SCGC1_REG(base) ((base)->SCGC1) -#define SIM_SCGC2_REG(base) ((base)->SCGC2) -#define SIM_SCGC3_REG(base) ((base)->SCGC3) -#define SIM_SCGC4_REG(base) ((base)->SCGC4) -#define SIM_SCGC5_REG(base) ((base)->SCGC5) -#define SIM_SCGC6_REG(base) ((base)->SCGC6) -#define SIM_SCGC7_REG(base) ((base)->SCGC7) -#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) -#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) -#define SIM_FCFG1_REG(base) ((base)->FCFG1) -#define SIM_FCFG2_REG(base) ((base)->FCFG2) -#define SIM_UIDH_REG(base) ((base)->UIDH) -#define SIM_UIDMH_REG(base) ((base)->UIDMH) -#define SIM_UIDML_REG(base) ((base)->UIDML) -#define SIM_UIDL_REG(base) ((base)->UIDL) - -/*! - * @} - */ /* end of group SIM_Register_Accessor_Macros */ - +} SIM_Type; /* ---------------------------------------------------------------------------- -- SIM Register Masks @@ -11752,280 +10148,380 @@ typedef struct { * @{ */ -/* SOPT1 Bit Fields */ -#define SIM_SOPT1_RAMSIZE_MASK 0xF000u -#define SIM_SOPT1_RAMSIZE_SHIFT 12 -#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) -#define SMC_PMCTRL_REG(base) ((base)->PMCTRL) -#define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) -#define SMC_PMSTAT_REG(base) ((base)->PMSTAT) - -/*! - * @} - */ /* end of group SMC_Register_Accessor_Macros */ - +} SMC_Type; /* ---------------------------------------------------------------------------- -- SMC Register Masks @@ -12135,34 +10569,44 @@ typedef struct { * @{ */ -/* PMPROT Bit Fields */ -#define SMC_PMPROT_AVLLS_MASK 0x2u -#define SMC_PMPROT_AVLLS_SHIFT 1 -#define SMC_PMPROT_ALLS_MASK 0x8u -#define SMC_PMPROT_ALLS_SHIFT 3 -#define SMC_PMPROT_AVLP_MASK 0x20u -#define SMC_PMPROT_AVLP_SHIFT 5 -/* PMCTRL Bit Fields */ -#define SMC_PMCTRL_STOPM_MASK 0x7u -#define SMC_PMCTRL_STOPM_SHIFT 0 -#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) -#define SPI_TCR_REG(base) ((base)->TCR) -#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) -#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) -#define SPI_SR_REG(base) ((base)->SR) -#define SPI_RSER_REG(base) ((base)->RSER) -#define SPI_PUSHR_REG(base) ((base)->PUSHR) -#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) -#define SPI_POPR_REG(base) ((base)->POPR) -#define SPI_TXFR0_REG(base) ((base)->TXFR0) -#define SPI_TXFR1_REG(base) ((base)->TXFR1) -#define SPI_TXFR2_REG(base) ((base)->TXFR2) -#define SPI_TXFR3_REG(base) ((base)->TXFR3) -#define SPI_RXFR0_REG(base) ((base)->RXFR0) -#define SPI_RXFR1_REG(base) ((base)->RXFR1) -#define SPI_RXFR2_REG(base) ((base)->RXFR2) -#define SPI_RXFR3_REG(base) ((base)->RXFR3) - -/*! - * @} - */ /* end of group SPI_Register_Accessor_Macros */ - +} SPI_Type; /* ---------------------------------------------------------------------------- -- SPI Register Masks @@ -12287,202 +10674,262 @@ typedef struct { * @{ */ -/* MCR Bit Fields */ -#define SPI_MCR_HALT_MASK 0x1u -#define SPI_MCR_HALT_SHIFT 0 -#define SPI_MCR_SMPL_PT_MASK 0x300u -#define SPI_MCR_SMPL_PT_SHIFT 8 -#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<GENCS) -#define TSI_SCANC_REG(base) ((base)->SCANC) -#define TSI_PEN_REG(base) ((base)->PEN) -#define TSI_WUCNTR_REG(base) ((base)->WUCNTR) -#define TSI_CNTR1_REG(base) ((base)->CNTR1) -#define TSI_CNTR3_REG(base) ((base)->CNTR3) -#define TSI_CNTR5_REG(base) ((base)->CNTR5) -#define TSI_CNTR7_REG(base) ((base)->CNTR7) -#define TSI_CNTR9_REG(base) ((base)->CNTR9) -#define TSI_CNTR11_REG(base) ((base)->CNTR11) -#define TSI_CNTR13_REG(base) ((base)->CNTR13) -#define TSI_CNTR15_REG(base) ((base)->CNTR15) -#define TSI_THRESHOLD_REG(base) ((base)->THRESHOLD) - -/*! - * @} - */ /* end of group TSI_Register_Accessor_Macros */ - +} TSI_Type; /* ---------------------------------------------------------------------------- -- TSI Register Masks @@ -12665,161 +11210,203 @@ typedef struct { * @{ */ -/* GENCS Bit Fields */ -#define TSI_GENCS_STPE_MASK 0x1u -#define TSI_GENCS_STPE_SHIFT 0 -#define TSI_GENCS_STM_MASK 0x2u -#define TSI_GENCS_STM_SHIFT 1 -#define TSI_GENCS_ESOR_MASK 0x10u -#define TSI_GENCS_ESOR_SHIFT 4 -#define TSI_GENCS_ERIE_MASK 0x20u -#define TSI_GENCS_ERIE_SHIFT 5 -#define TSI_GENCS_TSIIE_MASK 0x40u -#define TSI_GENCS_TSIIE_SHIFT 6 -#define TSI_GENCS_TSIEN_MASK 0x80u -#define TSI_GENCS_TSIEN_SHIFT 7 -#define TSI_GENCS_SWTS_MASK 0x100u -#define TSI_GENCS_SWTS_SHIFT 8 -#define TSI_GENCS_SCNIP_MASK 0x200u -#define TSI_GENCS_SCNIP_SHIFT 9 -#define TSI_GENCS_OVRF_MASK 0x1000u -#define TSI_GENCS_OVRF_SHIFT 12 -#define TSI_GENCS_EXTERF_MASK 0x2000u -#define TSI_GENCS_EXTERF_SHIFT 13 -#define TSI_GENCS_OUTRGF_MASK 0x4000u -#define TSI_GENCS_OUTRGF_SHIFT 14 -#define TSI_GENCS_EOSF_MASK 0x8000u -#define TSI_GENCS_EOSF_SHIFT 15 -#define TSI_GENCS_PS_MASK 0x70000u -#define TSI_GENCS_PS_SHIFT 16 -#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<BDH) -#define UART_BDL_REG(base) ((base)->BDL) -#define UART_C1_REG(base) ((base)->C1) -#define UART_C2_REG(base) ((base)->C2) -#define UART_S1_REG(base) ((base)->S1) -#define UART_S2_REG(base) ((base)->S2) -#define UART_C3_REG(base) ((base)->C3) -#define UART_D_REG(base) ((base)->D) -#define UART_MA1_REG(base) ((base)->MA1) -#define UART_MA2_REG(base) ((base)->MA2) -#define UART_C4_REG(base) ((base)->C4) -#define UART_C5_REG(base) ((base)->C5) -#define UART_ED_REG(base) ((base)->ED) -#define UART_MODEM_REG(base) ((base)->MODEM) -#define UART_IR_REG(base) ((base)->IR) -#define UART_PFIFO_REG(base) ((base)->PFIFO) -#define UART_CFIFO_REG(base) ((base)->CFIFO) -#define UART_SFIFO_REG(base) ((base)->SFIFO) -#define UART_TWFIFO_REG(base) ((base)->TWFIFO) -#define UART_TCFIFO_REG(base) ((base)->TCFIFO) -#define UART_RWFIFO_REG(base) ((base)->RWFIFO) -#define UART_RCFIFO_REG(base) ((base)->RCFIFO) -#define UART_C7816_REG(base) ((base)->C7816) -#define UART_IE7816_REG(base) ((base)->IE7816) -#define UART_IS7816_REG(base) ((base)->IS7816) -#define UART_WP7816T0_REG(base) ((base)->WP7816T0) -#define UART_WP7816T1_REG(base) ((base)->WP7816T1) -#define UART_WN7816_REG(base) ((base)->WN7816) -#define UART_WF7816_REG(base) ((base)->WF7816) -#define UART_ET7816_REG(base) ((base)->ET7816) -#define UART_TL7816_REG(base) ((base)->TL7816) -#define UART_C6_REG(base) ((base)->C6) -#define UART_PCTH_REG(base) ((base)->PCTH) -#define UART_PCTL_REG(base) ((base)->PCTL) -#define UART_B1T_REG(base) ((base)->B1T) -#define UART_SDTH_REG(base) ((base)->SDTH) -#define UART_SDTL_REG(base) ((base)->SDTL) -#define UART_PRE_REG(base) ((base)->PRE) -#define UART_TPL_REG(base) ((base)->TPL) -#define UART_IE_REG(base) ((base)->IE) -#define UART_WB_REG(base) ((base)->WB) -#define UART_S3_REG(base) ((base)->S3) -#define UART_S4_REG(base) ((base)->S4) -#define UART_RPL_REG(base) ((base)->RPL) -#define UART_RPREL_REG(base) ((base)->RPREL) -#define UART_CPW_REG(base) ((base)->CPW) -#define UART_RIDT_REG(base) ((base)->RIDT) -#define UART_TIDT_REG(base) ((base)->TIDT) - -/*! - * @} - */ /* end of group UART_Register_Accessor_Macros */ - +} UART_Type; /* ---------------------------------------------------------------------------- -- UART Register Masks @@ -13015,373 +11505,528 @@ typedef struct { * @{ */ -/* BDH Bit Fields */ -#define UART_BDH_SBR_MASK 0x1Fu -#define UART_BDH_SBR_SHIFT 0 -#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) -#define USB_IDCOMP_REG(base) ((base)->IDCOMP) -#define USB_REV_REG(base) ((base)->REV) -#define USB_ADDINFO_REG(base) ((base)->ADDINFO) -#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) -#define USB_OTGICR_REG(base) ((base)->OTGICR) -#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) -#define USB_OTGCTL_REG(base) ((base)->OTGCTL) -#define USB_ISTAT_REG(base) ((base)->ISTAT) -#define USB_INTEN_REG(base) ((base)->INTEN) -#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) -#define USB_ERREN_REG(base) ((base)->ERREN) -#define USB_STAT_REG(base) ((base)->STAT) -#define USB_CTL_REG(base) ((base)->CTL) -#define USB_ADDR_REG(base) ((base)->ADDR) -#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) -#define USB_FRMNUML_REG(base) ((base)->FRMNUML) -#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) -#define USB_TOKEN_REG(base) ((base)->TOKEN) -#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) -#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) -#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) -#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) -#define USB_USBCTRL_REG(base) ((base)->USBCTRL) -#define USB_OBSERVE_REG(base) ((base)->OBSERVE) -#define USB_CONTROL_REG(base) ((base)->CONTROL) -#define USB_USBTRC0_REG(base) ((base)->USBTRC0) -#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) - -/*! - * @} - */ /* end of group USB_Register_Accessor_Macros */ - +} USB_Type; /* ---------------------------------------------------------------------------- -- USB Register Masks @@ -13738,241 +12151,353 @@ typedef struct { * @{ */ -/* PERID Bit Fields */ -#define USB_PERID_ID_MASK 0x3Fu -#define USB_PERID_ID_SHIFT 0 -#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) -#define USBDCD_CLOCK_REG(base) ((base)->CLOCK) -#define USBDCD_STATUS_REG(base) ((base)->STATUS) -#define USBDCD_TIMER0_REG(base) ((base)->TIMER0) -#define USBDCD_TIMER1_REG(base) ((base)->TIMER1) -#define USBDCD_TIMER2_REG(base) ((base)->TIMER2) - -/*! - * @} - */ /* end of group USBDCD_Register_Accessor_Macros */ - +} USBDCD_Type; /* ---------------------------------------------------------------------------- -- USBDCD Register Masks @@ -14113,57 +12550,72 @@ typedef struct { * @{ */ -/* CONTROL Bit Fields */ -#define USBDCD_CONTROL_IACK_MASK 0x1u -#define USBDCD_CONTROL_IACK_SHIFT 0 -#define USBDCD_CONTROL_IF_MASK 0x100u -#define USBDCD_CONTROL_IF_SHIFT 8 -#define USBDCD_CONTROL_IE_MASK 0x10000u -#define USBDCD_CONTROL_IE_SHIFT 16 -#define USBDCD_CONTROL_START_MASK 0x1000000u -#define USBDCD_CONTROL_START_SHIFT 24 -#define USBDCD_CONTROL_SR_MASK 0x2000000u -#define USBDCD_CONTROL_SR_SHIFT 25 -/* CLOCK Bit Fields */ -#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u -#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 -#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu -#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 -#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) -#define VREF_SC_REG(base) ((base)->SC) - -/*! - * @} - */ /* end of group VREF_Register_Accessor_Macros */ - +} VREF_Type; /* ---------------------------------------------------------------------------- -- VREF Register Masks @@ -14255,24 +12663,31 @@ typedef struct { * @{ */ -/* TRM Bit Fields */ -#define VREF_TRM_TRIM_MASK 0x3Fu -#define VREF_TRM_TRIM_SHIFT 0 -#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) -#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) -#define WDOG_TOVALH_REG(base) ((base)->TOVALH) -#define WDOG_TOVALL_REG(base) ((base)->TOVALL) -#define WDOG_WINH_REG(base) ((base)->WINH) -#define WDOG_WINL_REG(base) ((base)->WINL) -#define WDOG_REFRESH_REG(base) ((base)->REFRESH) -#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) -#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) -#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) -#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) -#define WDOG_PRESC_REG(base) ((base)->PRESC) - -/*! - * @} - */ /* end of group WDOG_Register_Accessor_Macros */ - +} WDOG_Type; /* ---------------------------------------------------------------------------- -- WDOG Register Masks @@ -14378,75 +12743,99 @@ typedef struct { * @{ */ -/* STCTRLH Bit Fields */ -#define WDOG_STCTRLH_WDOGEN_MASK 0x1u -#define WDOG_STCTRLH_WDOGEN_SHIFT 0 -#define WDOG_STCTRLH_CLKSRC_MASK 0x2u -#define WDOG_STCTRLH_CLKSRC_SHIFT 1 -#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u -#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 -#define WDOG_STCTRLH_WINEN_MASK 0x8u -#define WDOG_STCTRLH_WINEN_SHIFT 3 -#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u -#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 -#define WDOG_STCTRLH_DBGEN_MASK 0x20u -#define WDOG_STCTRLH_DBGEN_SHIFT 5 -#define WDOG_STCTRLH_STOPEN_MASK 0x40u -#define WDOG_STCTRLH_STOPEN_SHIFT 6 -#define WDOG_STCTRLH_WAITEN_MASK 0x80u -#define WDOG_STCTRLH_WAITEN_SHIFT 7 -#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u -#define WDOG_STCTRLH_TESTWDOG_SHIFT 10 -#define WDOG_STCTRLH_TESTSEL_MASK 0x800u -#define WDOG_STCTRLH_TESTSEL_SHIFT 11 -#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u -#define WDOG_STCTRLH_BYTESEL_SHIFT 12 -#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define DSPI2 SPI2 +#define FLEXCAN0 CAN0 +#define FLEXCAN1 CAN1 #define PTA_BASE GPIOA_BASE #define PTA GPIOA #define PTB_BASE GPIOB_BASE @@ -14541,6 +12941,7 @@ typedef struct { #define PTD GPIOD #define PTE_BASE GPIOE_BASE #define PTE GPIOE +#define DMAMUX0 DMAMUX #define WP7816_T_TYPE0 WP7816T0 #define WP7816_T_TYPE1 WP7816T1 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK @@ -14567,29 +12968,17 @@ typedef struct { #define DAC_DATH_DATA_MASK DAC_DATH_DATA1_MASK #define DAC_DATH_DATA_SHIFT DAC_DATH_DATA1_SHIFT #define DAC_DATH_DATA(x) DAC_DATH_DATA1(x) -#define MCG_S_LOLS0_MASK MCG_S_LOLS_MASK -#define MCG_S_LOLS0_SHIFT MCG_S_LOLS_SHIFT #define SIM_SCGC6_RNGA_MASK This_symbol_has_been_deprecated #define SIM_SCGC6_RNGA_SHIFT This_symbol_has_been_deprecated #define Watchdog_IRQn WDOG_EWM_IRQn #define Watchdog_IRQHandler WDOG_EWM_IRQHandler #define LPTimer_IRQn LPTMR0_IRQn #define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler /*! * @} - */ /* end of group Backward_Compatibility_Symbols */ + */ /* end of group SDK_Compatibility_Symbols */ - -#else /* #if !defined(MK60D10_H_) */ - /* There is already included the same memory map. Check if it is compatible (has the same major version) */ - #if (MCU_MEM_MAP_VERSION != 0x0100u) - #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) - #warning There are included two not compatible versions of memory maps. Please check possible differences. - #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ - #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ -#endif /* #if !defined(MK60D10_H_) */ - -#ifdef __cplusplus -} -#endif +#endif /* _MK60D10_H_ */