cpu/stm32/kconfig.clk: adapt for l4/l5/wb
This commit is contained in:
Alexandre Abadie
parent
0031b14601
commit
f111fd8447
@ -6,7 +6,7 @@
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#
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menu "STM32 clock configuration"
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depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
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depends on CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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choice
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bool "Clock source selection"
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@ -17,7 +17,7 @@ config USE_CLOCK_PLL
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config USE_CLOCK_MSI
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bool "Use direct multi-speed frequency internal oscillator (MSI)"
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depends on CPU_FAM_L0 || CPU_FAM_L1
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depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config USE_CLOCK_HSE
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bool "Direct High frequency external oscillator (HSE)"
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@ -28,33 +28,64 @@ config USE_CLOCK_HSI
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endchoice
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if CPU_FAM_G0 || CPU_FAM_G4
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if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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choice
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bool "Source clock for PLL" if USE_CLOCK_PLL
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default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE
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default CLOCK_PLL_SRC_MSI
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config CLOCK_PLL_SRC_MSI
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bool "Use MSI source clock"
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config CLOCK_PLL_SRC_HSE
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bool "Use HSE source clock"
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depends on BOARD_HAS_HSE
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config CLOCK_PLL_SRC_HSI
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bool "Use HSI16 source clock"
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endchoice
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endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CUSTOM_PLL_PARAMS
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bool "Configure PLL parameters"
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depends on USE_CLOCK_PLL
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config CLOCK_PLL_M
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int "M: PLLIN division factor" if USE_CLOCK_PLL
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int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS
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default 1 if CPU_FAM_G0
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default 4 if CPU_FAM_G4
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default 6 if CPU_FAM_G4 && BOARD_HAS_HSE
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range 1 8 if CPU_FAM_G0
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default 4 if CPU_FAM_G4
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default 6 if (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB) && CLOCK_PLL_SRC_MSI
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default 4 if CPU_FAM_WB && CLOCK_PLL_SRC_HSE
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default 2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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range 1 8 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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range 1 16 if CPU_FAM_G4
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config CLOCK_PLL_N
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int "N: PLLIN multiply factor" if USE_CLOCK_PLL
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default 20 if CPU_FAM_G0
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default 40 if CPU_FAM_G4
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range 8 86 if CPU_FAM_G0
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int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS
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default 16 if CPU_FAM_WB
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default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX
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default 27 if CPU_FAM_L5
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default 20 if CPU_FAM_G0 || CPU_FAM_L4
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default 85 if CPU_FAM_G4
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range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5
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range 8 127 if CPU_FAM_G4
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range 6 127 if CPU_FAM_WB
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if CPU_FAM_G0
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if CPU_FAM_G0 || CPU_FAM_WB
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config CLOCK_PLL_R
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int "Q: VCO division factor" if USE_CLOCK_PLL
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int "Q: VCO division factor" if CUSTOM_PLL_PARAMS
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default 2 if CPU_FAM_WB
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default 6 if BOARD_HAS_HSE
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default 5
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range 2 8
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endif # CPU_FAM_G0
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endif # CPU_FAM_G0 || CPU_FAM_WB
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if CPU_FAM_G4
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if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
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choice
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bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
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bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS
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default PLL_R_DIV_2
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config PLL_R_DIV_2
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@ -77,52 +108,9 @@ config CLOCK_PLL_R
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default 4 if PLL_R_DIV_4
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default 6 if PLL_R_DIV_6
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default 8 if PLL_R_DIV_8
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endif # CPU_FAM_G4
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endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5
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if CPU_FAM_G0
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choice
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bool "HSISYS division factor" if USE_CLOCK_HSI
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default CLOCK_HSISYS_DIV_1
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config CLOCK_HSISYS_DIV_1
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bool "Divide HSISYS by 1"
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config CLOCK_HSISYS_DIV_2
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bool "Divide HSISYS by 2"
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config CLOCK_HSISYS_DIV_4
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bool "Divide HSISYS by 4"
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config CLOCK_HSISYS_DIV_8
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bool "Divide HSISYS by 8"
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config CLOCK_HSISYS_DIV_16
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bool "Divide HSISYS by 16"
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config CLOCK_HSISYS_DIV_32
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bool "Divide HSISYS by 32"
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config CLOCK_HSISYS_DIV_64
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bool "Divide HSISYS by 64"
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config CLOCK_HSISYS_DIV_128
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bool "Divide HSISYS by 128"
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endchoice
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config CLOCK_HSISYS_DIV
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int
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default 1 if CLOCK_HSISYS_DIV_1
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default 2 if CLOCK_HSISYS_DIV_2
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default 4 if CLOCK_HSISYS_DIV_4
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default 8 if CLOCK_HSISYS_DIV_8
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default 16 if CLOCK_HSISYS_DIV_16
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default 32 if CLOCK_HSISYS_DIV_32
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default 64 if CLOCK_HSISYS_DIV_64
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default 128 if CLOCK_HSISYS_DIV_128
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endif # CPU_FAM_G0
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endif # CPU_FAM_G0 || CPU_FAM_G4
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endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_PLL_DIV
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@ -174,31 +162,107 @@ config CLOCK_PLL_MUL
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default 24 if PLL_MUL_24
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default 32 if PLL_MUL_32
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default 48 if PLL_MUL_48
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endif # CPU_FAM_L0 || CPU_FAM_L1
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if CPU_FAM_G0
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choice
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bool "Desired MSI clock frequency" if USE_CLOCK_MSI
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bool "HSISYS division factor" if USE_CLOCK_HSI
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default CLOCK_HSISYS_DIV_1
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config CLOCK_HSISYS_DIV_1
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bool "Divide HSISYS by 1"
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config CLOCK_HSISYS_DIV_2
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bool "Divide HSISYS by 2"
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config CLOCK_HSISYS_DIV_4
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bool "Divide HSISYS by 4"
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config CLOCK_HSISYS_DIV_8
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bool "Divide HSISYS by 8"
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config CLOCK_HSISYS_DIV_16
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bool "Divide HSISYS by 16"
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config CLOCK_HSISYS_DIV_32
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bool "Divide HSISYS by 32"
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config CLOCK_HSISYS_DIV_64
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bool "Divide HSISYS by 64"
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config CLOCK_HSISYS_DIV_128
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bool "Divide HSISYS by 128"
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endchoice
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config CLOCK_HSISYS_DIV
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int
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default 1 if CLOCK_HSISYS_DIV_1
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default 2 if CLOCK_HSISYS_DIV_2
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default 4 if CLOCK_HSISYS_DIV_4
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default 8 if CLOCK_HSISYS_DIV_8
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default 16 if CLOCK_HSISYS_DIV_16
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default 32 if CLOCK_HSISYS_DIV_32
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default 64 if CLOCK_HSISYS_DIV_64
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default 128 if CLOCK_HSISYS_DIV_128
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endif # CPU_FAM_G0
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if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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choice
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bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI)
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default CLOCK_MSI_48MHZ if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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default CLOCK_MSI_4MHZ
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config CLOCK_MSI_65KHZ
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bool "65.536kHz"
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bool "65.536kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_100KHZ
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bool "100kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_130KHZ
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bool "131.072kHz"
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bool "131.072kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_200KHZ
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bool "200kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_260KHZ
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bool "262.144kHz"
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bool "262.144kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_400KHZ
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bool "400kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_520KHZ
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bool "524.288kHz"
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bool "524.288kHz" if CPU_FAM_L0 || CPU_FAM_L1
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config CLOCK_MSI_800KHZ
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bool "800kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_1MHZ
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bool "1.048MHz"
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bool
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prompt "1MHz"
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config CLOCK_MSI_2MHZ
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bool "2.097MHz"
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bool
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prompt "2MHz"
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config CLOCK_MSI_4MHZ
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bool "4.194MHz"
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bool
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prompt "4MHz"
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config CLOCK_MSI_8MHZ
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bool "8MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_16MHZ
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bool "16MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_24MHZ
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bool "24MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_32MHZ
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bool "32MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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config CLOCK_MSI_48MHZ
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bool "48MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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endchoice
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@ -208,14 +272,27 @@ config CLOCK_MSI
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default 131072 if CLOCK_MSI_130KHZ
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default 262144 if CLOCK_MSI_260KHZ
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default 524288 if CLOCK_MSI_520KHZ
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default 1048000 if CLOCK_MSI_1MHZ
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default 2097000 if CLOCK_MSI_2MHZ
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default 4194000 if CLOCK_MSI_4MHZ
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default 100000 if CLOCK_MSI_100KHZ
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default 200000 if CLOCK_MSI_200KHZ
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default 400000 if CLOCK_MSI_400KHZ
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default 800000 if CLOCK_MSI_800KHZ
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default 1000000 if CLOCK_MSI_1MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB)
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default 1048000 if CLOCK_MSI_1MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 2000000 if CLOCK_MSI_2MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB)
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default 2097000 if CLOCK_MSI_2MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 4000000 if CLOCK_MSI_4MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB)
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default 4194000 if CLOCK_MSI_4MHZ && (CPU_FAM_L0 || CPU_FAM_L1)
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default 8000000 if CLOCK_MSI_8MHZ
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default 16000000 if CLOCK_MSI_16MHZ
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default 24000000 if CLOCK_MSI_24MHZ
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default 32000000 if CLOCK_MSI_32MHZ
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default 48000000 if CLOCK_MSI_48MHZ
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endif # CPU_FAM_L0 || CPU_FAM_L1
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endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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choice
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bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
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default CLOCK_APB1_DIV_4 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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default CLOCK_APB1_DIV_1
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config CLOCK_APB1_DIV_1
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@ -245,7 +322,8 @@ config CLOCK_APB1_DIV
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choice
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bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
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depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1
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depends on CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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default CLOCK_APB2_DIV_2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB
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default CLOCK_APB2_DIV_1
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config CLOCK_APB2_DIV_1
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